// Copyright (c) 2009 Nokia Corporation and/or its subsidiary(-ies).

// All rights reserved.

// This component and the accompanying materials are made available

// under the terms of the License "Eclipse Public License v1.0"

// which accompanies this distribution, and is available

// at the URL "http://www.eclipse.org/legal/epl-v10.html".

//

// Initial Contributors:

// Nokia Corporation - initial contribution.

//

// Contributors:

//

// Description:

//

#ifndef TPS65950_REGISTERS_H

#define TPS65950_REGISTERS_H

#include <e32cmn.h>

namespace TPS65950

{

namespace Register

	{

	const TUint KGroupShift = 8;

	const TUint KRegisterMask = 0xFF;

	const TUint KGroupMask = 0xFF00;

	enum TGroup

		{

		EGroup12 = (0 << KGroupShift),

		EGroup48 = (1 << KGroupShift),

		EGroup49 = (2 << KGroupShift),

		EGroup4a = (3 << KGroupShift),

		EGroup4b = (4 << KGroupShift)

		};

	enum TGroup12Registers

		{

		VDD1_SR_CONTROL = EGroup12,

		VDD2_SR_CONTROL

		};

	enum TGroup48Registers

		{

		VENDOR_ID_LO =  EGroup48,

		VENDOR_ID_HI, 

		PRODUCT_ID_LO,

		PRODUCT_ID_HI,

		FUNC_CTRL,

		FUNC_CTRL_SET,

		FUNC_CTRL_CLR,

		IFC_CTRL,

		IFC_CTRL_SET, 

		IFC_CTRL_CLR, 

		OTG_CTRL,

		OTG_CTRL_SET,

		OTG_CTRL_CLR,

		USB_INT_EN_RISE, 

		USB_INT_EN_RISE_SET,

		USB_INT_EN_RISE_CLR,

		USB_INT_EN_FALL, 

		USB_INT_EN_FALL_SET, 

		USB_INT_EN_FALL_CLR,

		USB_INT_STS, 

		USB_INT_LATCH,

		DEBUG, 

		SCRATCH_REG, 

		SCRATCH_REG_SET,

		SCRATCH_REG_CLR,

		CARKIT_CTRL, 

		CARKIT_CTRL_SET, 

		CARKIT_CTRL_CLR, 

		CARKIT_INT_DELAY,

		CARKIT_INT_EN, 

		CARKIT_INT_EN_SET,

		CARKIT_INT_EN_CLR,

		CARKIT_INT_STS, 

		CARKIT_INT_LATCH, 

		CARKIT_PLS_CTRL, 

		CARKIT_PLS_CTRL_SET, 

		CARKIT_PLS_CTRL_CLR,

		TRANS_POS_WIDTH, 

		TRANS_NEG_WIDTH,

		RCV_PLTY_RECOVERY,

		MCPC_CTRL = 0x30, 

		MCPC_CTRL_SET,

		MCPC_CTRL_CLR,

		MCPC_IO_CTRL,

		MCPC_IO_CTRL_SET, 

		MCPC_IO_CTRL_CLR,

		MCPC_CTRL2, 

		MCPC_CTRL2_SET, 

		MCPC_CTRL2_CLR, 

		OTHER_FUNC_CTRL = EGroup48 + 0x80, 

		OTHER_FUNC_CTRL_SET, 

		OTHER_FUNC_CTRL_CLR, 

		OTHER_IFC_CTRL,

		OTHER_IFC_CTRL_SET,

		OTHER_IFC_CTRL_CLR,

		OTHER_INT_EN_RISE,

		OTHER_INT_EN_RISE_SET,

		OTHER_INT_EN_RISE_CLR,

		OTHER_INT_EN_FALL,

		OTHER_INT_EN_FALL_SET,

		OTHER_INT_EN_FALL_CLR,

		OTHER_INT_STS,

		OTHER_INT_LATCH,

		ID_INT_EN_RISE,

		ID_INT_EN_RISE_SET,

		ID_INT_EN_RISE_CLR,

		ID_INT_EN_FALL,

		ID_INT_EN_FALL_SET,

		ID_INT_EN_FALL_CLR,

		ID_INT_STS,

		ID_INT_LATCH,

		ID_STATUS,

		CARKIT_SM_1_INT_EN,

		CARKIT_SM_1_INT_EN_SET,

		CARKIT_SM_1_INT_EN_CLR,

		CARKIT_SM_1_INT_STS,

		CARKIT_SM_1_INT_LATCH,

		CARKIT_SM_2_INT_EN,

		CARKIT_SM_2_INT_EN_SET,

		CARKIT_SM_2_INT_EN_CLR,

		CARKIT_SM_2_INT_STS,

		CARKIT_SM_2_INT_LATCH,

		CARKIT_SM_CTRL,

		CARKIT_SM_CTRL_SET,

		CARKIT_SM_CTRL_CLR,

		CARKIT_SM_CMD,

		CARKIT_SM_CMD_SET,

		CARKIT_SM_CMD_CLR,

		CARKIT_SM_CMD_STS,

		CARKIT_SM_STATUS,

		CARKIT_SM_NEXT_STATUS,

		CARKIT_SM_ERR_STATUS,

		CARKIT_SM_CTRL_STATE,

		POWER_CTRL,

		POWER_CTRL_SET,

		POWER_CTRL_CLR,

		OTHER_IFC_CTRL2,

		OTHER_IFC_CTRL2_SET,

		OTHER_IFC_CTRL2_CLR,

		REG_CTRL_EN,

		REG_CTRL_EN_SET,

		REG_CTRL_EN_CLR,

		REG_CTRL_ERROR,

		OTHER_FUNC_CTRL2,

		OTHER_FUNC_CTRL2_SET,

		OTHER_FUNC_CTRL2_CLR,

		CARKIT_ANA_CTRL,

		CARKIT_ANA_CTRL_SET,

		CARKIT_ANA_CTRL_CLR,

		VBUS_DEBOUNCE = EGroup48 + 0xC0,

		ID_DEBOUNCE,

		TPH_DP_CON_MIN,

		TPH_DP_CON_MAX,

		TCR_DP_CON_MIN,

		TCR_DP_CON_MAX,

		TPH_DP_PD_SHORT,

		TPH_CMD_DLY,

		TPH_DET_RST,

		TPH_AUD_BIAS,

		TCR_UART_DET_MIN,

		TCR_UART_DET_MAX,

		TPH_ID_INT_PW = EGroup48 + 0xCC,

		TACC_ID_INT_WAIT,

		TACC_ID_INT_PW,

		TPH_CMD_WAIT = EGroup48 + 0xD0,

		TPH_ACK_WAIT,

		TPH_DP_DISC_DET,

		VBAT_TIMER,

		CARKIT_4W_DEBUG = EGroup48 + 0xE0,

		CARKIT_5W_DEBUG,

		TEST_CTRL_CLR = EGroup48 + 0xEB,

		TEST_CARKIT_SET,

		TEST_CARKIT_CLR,

		TEST_POWER_SET,

		TEST_POWER_CLR,

		TEST_ULPI,

		TXVR_EN_TEST_SET,

		TXVR_EN_TEST_CLR,

		VBUS_EN_TEST,

		ID_EN_TEST,

		PSM_EN_TEST_SET,

		PSM_EN_TEST_CLR,

		PHY_TRIM_CTRL = EGroup48 + 0xFC,

		PHY_PWR_CTRL,

		PHY_CLK_CTRL,

		PHY_CLK_CTRL_STS // 0x000000ff

		};

	enum TGroup49Registers

		{

		CODEC_MODE = EGroup49 + 1,

		OPTION , 

		MICBIAS_CTL = EGroup49 + 0x04,

		ANAMICL,

		ANAMICR,

		AVADC_CTL,

		ADCMICSEL,

		DIGMIXING,

		ATXL1PGA,

		ATXR1PGA,

		AVTXL2PGA,

		AVTXR2PGA,

		AUDIO_IF,

		VOICE_IF,

		ARXR1PGA,

		ARXL1PGA,

		ARXR2PGA,

		ARXL2PGA,

		VRXPGA,

		VSTPGA,

		VRX2ARXPGA,

		AVDAC_CTL,

		ARX2VTXPGA,

		ARXL1_APGA_CTL,

		ARXR1_APGA_CTL,

		ARXL2_APGA_CTL,

		ARXR2_APGA_CTL,

		ATX2ARXPGA,

		BT_IF,

		BTPGA,

		BTSTPGA,

		EAR_CTL,

		HS_SEL,

		HS_GAIN_SET,

		HS_POPN_SET,

		PREDL_CTL,

		PREDR_CTL,

		PRECKL_CTL,

		PRECKR_CTL,

		HFL_CTL,

		HFR_CTL, 

		ALC_CTL, 

		ALC_SET1,

		ALC_SET2,

		BOOST_CTL,

		SOFTVOL_CTL,

		DTMF_FREQSEL,

		DTMF_TONEXT1H,

		DTMF_TONEXT1L,

		DTMF_TONEXT2H,

		DTMF_TONEXT2L,

		DTMF_TONOFF,

		DTMF_WANONOFF,//  8 0x0000 0036

		I2S_RX_SCRAMBLE_H, 

		I2S_RX_SCRAMBLE_M, 

		I2S_RX_SCRAMBLE_L,

		APLL_CTL,

		DTMF_CTL,

		DTMF_PGA_CTL2,

		DTMF_PGA_CTL1,

		MISC_SET_1,

		PCMBTMUX,

		RX_PATH_SEL,

		VDL_APGA_CTL,

		VIBRA_CTL,

		VIBRA_SET,

		ANAMIC_GAIN,

		MISC_SET_2,// RW 8 0x0000 0049

		AUDIO_TEST_CTL = EGroup49 + 0x0000004C,

		INT_TEST_CTL,

		DAC_ADC_TEST_CTL,

		RXTX_TRIM_IB,

		CLD_CONTROL,

		CLD_MODE_TIMING,

		CLD_TRIM_RAMP,

		CLD_TESTV_CTL,

		APLL_TEST_CTL,

		APLL_TEST_DIV,

		APLL_TEST_CTL2,

		APLL_TEST_CUR,

		DIGMIC_BIAS1_CTL,

		DIGMIC_BIAS2_CTL,

		RX_OFFSET_VOICE,

		RX_OFFSET_AL1,

		RX_OFFSET_AR1,

		RX_OFFSET_AL2,

		RX_OFFSET_AR2,

		OFFSET1,

		OFFSET2,

		GPIODATAIN1  = EGroup49 + 0x00000098,

		GPIODATAIN2, 

		GPIODATAIN3, 

		GPIODATADIR1, 

		GPIODATADIR2, 

		GPIODATADIR3, 

		GPIODATAOUT1,

		GPIODATAOUT2,

		GPIODATAOUT3,

		CLEARGPIODATAOUT1,

		CLEARGPIODATAOUT2,

		CLEARGPIODATAOUT3,

		SETGPIODATAOUT1,

		SETGPIODATAOUT2,

		SETGPIODATAOUT3,

		GPIO_DEBEN1,

		GPIO_DEBEN3,

		GPIO_CTRL ,

		GPIOPUPDCTR1,

		GPIOPUPDCTR2,

		GPIOPUPDCTR3,

		GPIOPUPDCTR4,

		GPIOPUPDCTR5,

		GPIO_TEST,

		GPIO_ISR1A = EGroup49 + 0xb1,

		GPIO_ISR2A,

		GPIO_ISR3A,

		GPIO_IMR1A, // 

		GPIO_IMR2A,

		GPIO_IMR3A,

		GPIO_ISR1B,

		GPIO_ISR2B,

		GPIO_ISR3B,

		GPIO_IMR1B,

		GPIO_IMR2B,

		GPIO_IMR3B,

		GPIO_SIR1,

		GPIO_SIR2,

		GPIO_SIR3,

		GPIO_EDR1,

		GPIO_EDR2,

		GPIO_EDR3,

		GPIO_EDR4,

		GPIO_EDR5,

		GPIO_SIH_CTRL,

		PIH_ISR_P1 = EGroup49 + 0x00000081,

		PIH_ISR_P2,

		PIH_SIR ,

		IDCODE_7_0 = EGroup49 + 0x00000085,

		IDCODE_15_8,

		IDCODE_23_16,

		IDCODE_31_24,

		DIEID_7_0,

		DIEID_15_8,

		DIEID_23_16,

		DIEID_31_24,

		DIEID_39_32,

		DIEID_47_40,

		DIEID_55_48,

		DIEID_63_56,

		GPBR1,

		PMBR1,

		PMBR2,

		GPPUPDCTR1,

		GPPUPDCTR2,

		GPPUPDCTR3,

		UNLOCK_TEST_REG,

		};

	/*

	Note: Access to the following registers is protected:

	· IDCODE_7_0

	· IDCODE_15_8

	· IDCODE_23_16

	· IDCODE_31_24

	· DIEID_7_0

	· DIEID_15_8

	· DIEID_23_16

	· DIEID_31_24

	· DIEID_39_32

	· DIEID_47_40

	· DIEID_55_48

	· DIEID_63_56

	To read these registers, the UNLOCK_TEST_REG register must first be written with 0x49.

	Table 2-29. GPPUPDCTR1

	Address Offset 0x0F

	Physical Address 0x0000 0094 Instance INT_SCINTBR

	*/

	enum TGroup4aRegisters

		{

		CTRL1 = EGroup4a + 0,

		CTRL2,

		RTSELECT_LSB,

		RTSELECT_MSB,

		RTAVERAGE_LSB,

		RTAVERAGE_MSB,

		SW1SELECT_LSB,

		SW1SELECT_MSB,

		SW1AVERAGE_LSB,

		SW1AVERAGE_MSB,

		SW2SELECT_LSB,

		SW2SELECT_MSB,

		SW2AVERAGE_LSB,

		SW2AVERAGE_MSB,

		BCI_USBAVERAGE,

		ACQUISITION,

		USBREF_LSB,

		USBREF_MSB,

		CTRL_SW1,

		CTRL_SW2,

		MADC_TEST,

		GP_MADC_TEST1,

		GP_MADC_TEST2,

		RTCH0_LSB, 

		RTCH0_MSB, 

		RTCH1_LSB, 

		RTCH1_MSB, 

		RTCH2_LSB, 

		RTCH2_MSB, 

		RTCH3_LSB, 

		RTCH3_MSB,

		RTCH4_LSB,

		RTCH4_MSB,

		RTCH5_LSB,

		RTCH5_MSB,

		RTCH6_LSB,

		RTCH6_MSB,

		RTCH7_LSB,

		RTCH7_MSB,

		RTCH8_LSB,

		RTCH8_MSB,

		RTCH9_LSB,

		RTCH9_MSB,

		RTCH10_LSB,

		RTCH10_MSB,

		RTCH11_LSB,

		RTCH11_MSB,

		RTCH12_LSB,

		RTCH12_MSB,

		RTCH13_LSB,

		RTCH13_MSB,

		RTCH14_LSB,

		RTCH14_MSB,

		RTCH15_LSB,

		RTCH15_MSB,

		GPCH0_LSB,

		GPCH0_MSB,

		GPCH1_LSB,

		GPCH1_MSB,

		GPCH2_LSB,

		GPCH2_MSB, 

		GPCH3_LSB,

		GPCH3_MSB,

		GPCH4_LSB,

		GPCH4_MSB,

		GPCH5_LSB,

		GPCH5_MSB,

		GPCH6_LSB,

		GPCH6_MSB,

		GPCH7_LSB,

		GPCH7_MSB,

		GPCH8_LSB,

		GPCH8_MSB,

		GPCH9_LSB,

		GPCH9_MSB,

		GPCH10_LSB,

		GPCH10_MSB,

		GPCH11_LSB,

		GPCH11_MSB,

		GPCH12_LSB,

		GPCH12_MSB,

		GPCH13_LSB,

		GPCH13_MSB,

		GPCH14_LSB,

		GPCH14_MSB,

		GPCH15_LSB,

		GPCH15_MSB,

		BCICH0_LSB,

		BCICH0_MSB,

		BCICH1_LSB,

		BCICH1_MSB,

		BCICH2_LSB,

		BCICH2_MSB,

		BCICH3_LSB,

		BCICH3_MSB,

		BCICH4_LSB,

		BCICH4_MSB,

		MADC_ISR1,

		MADC_IMR1,

		MADC_ISR2,

		MADC_IMR2,

		MADC_SIR,

		MADC_EDR,

		MADC_SIH_CTRL,

		BCIMDEN,

		BCIMDKEY,

		BCIMSTATEC,

		BCIMSTATEP,

		BCIVBAT1,

		BCIVBAT2,

		BCITBAT1,

		BCITBAT2,

		BCIICHG1,

		BCIICHG2,

		BCIVAC1,

		BCIVAC2,

		BCIVBUS1,

		BCIVBUS2,

		BCIMFSTS2,

		BCIMFSTS3,

		BCIMFSTS4,

		BCIMFKEY,

		BCIMFEN1,

		BCIMFEN2,

		BCIMFEN3,

		BCIMFEN4,

		BCIMFTH1,

		BCIMFTH2,

		BCIMFTH3,

		BCIMFTH4,

		BCIMFTH5,

		BCIMFTH6,

		BCIMFTH7,

		BCIMFTH8,	

		BCIMFTH9, 

		BCITIMER1,

		BCITIMER2,

		BCIWDKEY,

		BCIWD,

		BCICTL1,

		BCICTL2,

		BCIVREF1,

		BCIVREF2,

		BCIIREF1,