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/*
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pm_definitions_chipset_api.h
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Copyright (c) 2009 Nokia Corporation and/or its subsidiary(-ies).
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All rights reserved.
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This program and the accompanying materials are made available
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under the terms of the Eclipse Public License v1.0 which accompanies
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this distribution, and is available at
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http://www.eclipse.org/legal/epl-v10.html
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Initial Contributors:
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Nokia Corporation - initial contribution.
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Contributors:
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*/
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/** @file
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@brief PM Definitions Chipset API H
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Purpose of this header is to describe the protocol that should be followed by
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Nokia and chipset vendor regarding some of the parameters used in power
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management chipset API specifications. The aim of this definition is to specify
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platform specific entities in an abstract way and at the same time, providing an
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option for some level of granularity for possible performance optimizations.
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Definition of the following parameters is included in this document.
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@publishedDeviceAbstraction
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*/
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#ifndef PM_DEFINITIONS_CHIPSET_API_H
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#define PM_DEFINITIONS_CHIPSET_API_H
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// Include files
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#include <kern_priv.h>
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// Constants
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/**
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Latency resource minimum value
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*/
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const TInt KMinLatency = 0;
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/**
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Latency resource maximum values
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*/
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const TInt KMaxLatency = KMaxTInt32;
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/**
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Maximum level of any performance resource
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*/
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const TInt KPerfMax = 100;
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/**
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CPU normal performance level
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*/
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const TInt KPerfNormalCpu = 100;
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/**
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Memory normal performance level
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*/
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const TInt KPerfNormalMemory = 100;
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/**
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Bus normal performance level
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*/
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const TInt KPerfNormalBus = 100;
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/**
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Audio HWA normal performance level
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*/
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const TInt KPerfNormalHwaAudio = 100;
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/**
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Graphics HWA normal performance level
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*/
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const TInt KPerfNormalHwaGfx = 100;
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/**
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Imaging HWA normal performance level
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*/
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const TInt KPerfNormalHwaImg = 100;
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/**
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Video HWA normal performance level
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*/
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const TInt KPerfNormalHwaVideo = 100;
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/**
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Modem normal performance level
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*/
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const TInt KPerfNormalModem = 100;
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/**
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Minimum level of any performance level
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*/
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const TInt KPerfMin = 0;
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// Data types
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/**
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Symbian power resource IDs
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*/
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enum TPowerRes
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{
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EPwrResLatency = 0, /**< latency */
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EPwrResAnalogAcc = 0, /**< analog accessory */
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EPwrResBT = 0, /**< bluetooth */
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EPwrResCamera1 = 0, /**< camera#1 */
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EPwrResCamera2 = 0, /**< camera#2 */
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EPwrResDBR = 0, /**< DBR */
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EPwrResDigMic = 0, /**< digital mic */
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EPwrResDisplay1 = 0, /**< display#1 */
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EPwrResDisplay2 = 0, /**< display#2 */
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EPwrResEAR = 0, /**< EAR */
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EPwrRes_eMMC = 0, /**< eMMC */
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EPwrResFMRadioTx = 0, /**< FM radio transmitter */
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EPwrResFMRadioRx = 0, /**< FM radio receiver */
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EPwrResGPS = 0, /**< GPS */
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EPwrResHSUSB = 0, /**< HS-USB */
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EPwrResIHF = 0, /**< IHF */
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EPwrResIrDA = 0, /**< IrDA */
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EPwrResKeypad = 0, /**< keypad */
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EPwrResMassStorage = 0, /**< mass storage */
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EPwrResMemCard = 0, /**< memory card */
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EPwrResMic = 0, /**< mic */
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EPwrResNFC = 0, /**< NFC */
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EPwrResSIMIF = 0, /**< SIM IF */
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EPwrResTouchScreen = 0, /**< touch screen */
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EPwrResTVOut = 0, /**< TV out */
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EPwrResULP = 0, /**< ULP */
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EPwrResUSBOTG = 0, /**< USB OTG */
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EPwrResUWB = 0, /**< UWB */
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EPwrResVibra = 0, /**< vibra */
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EPwrResWiMax = 0, /**< WiMax */
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EPwrResWLAN = 0, /**< WLAN */
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EPwrResHDMI = 0, /**< HDMI */
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EPwrResUSB_UICC_IF = 0, /**< USB UICC IF */
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EPwrResExtClk1 = 0, /**< External clock 1 */
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EPwrResExtClk2 = 0, /**< External clock 2 */
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EPwrResExtClk3 = 0, /**< External clock 3 */
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EPwrResExtClk4 = 0, /**< External clock 4 */
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EPwrResExtClk5 = 0, /**< External clock 5 */
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EPwrResExtClk6 = 0, /**< External clock 6 */
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EPwrResExtClk7 = 0, /**< External clock 7 */
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EPwrResExtClk8 = 0, /**< External clock 8 */
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EPwrResExtClk9 = 0, /**< External clock 9 */
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EPwrResExtClk10 = 0, /**< External clock 10 */
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EPwrResExtVoltage1 = 0, /**< External voltage 1 */
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EPwrResExtVoltage2 = 0, /**< External voltage 2 */
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EPwrResExtVoltage3 = 0, /**< External voltage 3 */
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EPwrResExtVoltage4 = 0, /**< External voltage 4 */
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EPwrResExtVoltage5 = 0, /**< External voltage 5 */
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EPwrResExtVoltage6 = 0, /**< External voltage 6 */
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EPwrResExtVoltage7 = 0, /**< External voltage 7 */
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EPwrResExtVoltage8 = 0, /**< External voltage 8 */
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EPwrResExtVoltage9 = 0, /**< External voltage 9 */
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EPwrResExtVoltage10 = 0, /**< External voltage 10 */
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};
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/**
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Symbian performance resource IDs
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*/
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enum TPerfRes
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{
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EPwrResPerfCpu = 0, /**< CPU performance */
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EPwrResPerfMemory = 0, /**< Main memory */
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EPwrResPerfBus = 0, /**< Main interconnect bus */
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EPwrResPerfHwaAudio = 0, /**< Audio HW accelerator */
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EPwrResPerfHwaGfx = 0, /**< Graphics HW accelerator */
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EPwrResPerfHwaImg = 0, /**< Imaging HW accelerator */
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EPwrResPerfHwaVideo = 0, /**< Video HW accelerator */
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EPwrResPerfModem = 0 /**< Modem */
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};
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/**
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Possible resource levels
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*/
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enum TDevState
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{
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EDevD0 = 0xf, /**< (fixed) highest power state */
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EDevD1 = 0xe, /**< (fixed) */
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EDevD2 = 0xd, /**< (fixed) */
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EDevD3 = 0xc, /**< (fixed) */
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EDevD4 = 0xb, /**< (fixed) */
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EDevD5 = 0xa, /**< (fixed) */
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EDevD6 = 0x9, /**< (fixed) */
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EDevD7 = 0x8, /**< (fixed) */
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EDevD8 = 0x7, /**< (fixed) */
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EDevD9 = 0x6, /**< (fixed) */
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EDevD10 = 0x5, /**< (fixed) */
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EDevD11 = 0x4, /**< (fixed) */
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EDevD12 = 0x3, /**< (fixed) */
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EDevD13 = 0x2, /**< (fixed) */
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EDevD14 = 0x1, /**< (fixed) */
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EDevD15 = 0x0 /**< (fixed) lowest power state */
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};
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/**
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Power is fully off. Least power consuming state.
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*/
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const TInt KDevOff = EDevD15;
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/**
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Device is in reset state.
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*/
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const TInt KDevReset = EDevD14;
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/**
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Device is in retention state
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*/
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const TInt KDevRetention = EDevD13;
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/**
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Device is in sleep state.
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An intermediate state whose definition varies by device.
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*/
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const TInt KDevSleep = EDevD12;
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/**
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Device is in idle state.
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An intermediate state whose definition varies by device.
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*/
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const TInt KDevIdle = EDevD2;
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/**
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Device is capable itself to control power states.
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*/
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const TInt KDevAuto = EDevD1;
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/**
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Power is fully on.
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*/
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const TInt KDevOn = EDevD0;
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/**
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The set of HW blocks whose load is monitored by the DVFS algorithms. Each
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scalable domain may consist of one or more of such blocks.
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*/
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enum TDvfsMonitor
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{
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EDvfsMonCpu1 = 0, /**< General purpose CPU 1 */
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EDvfsMonCpu2 = 0, /**< General purpose CPU 2 */
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EDvfsMonMemory = 0, /**< Main program memory (RAM) */
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EDvfsMonBus = 0, /**< Main bus */
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EDvfsMonDma = 0, /**< System DMA */
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EDvfsMonAudio = 0, /**< Audio HW accelerator */
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EDvfsMonHwaGfx = 0, /**< Graphics HW accelerator */
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EDvfsMonHwaImg = 0, /**< Imaging HW accelerator */
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EDvfsMonHwaVideo = 0, /**< Video HW accelerator */
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EDvfsMonModem = 0, /**< Modem */
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EDvfsMonResv0 = 0, /**< Reserved */
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EDvfsMonResv1 = 0, /**< Reserved */
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EDvfsMonResv2 = 0, /**< Reserved */
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EDvfsMonResv3 = 0, /**< Reserved */
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EDvfsMonResv4 = 0, /**< Reserved */
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EDvfsMonResv5 = 0, /**< Reserved */
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EDvfsMonResv6 = 0, /**< Reserved */
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};
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/**
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Global (system wide) sleep states from a software point of view. The system
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shall have up to 16 different sleep states. EGblG0 is the most power consuming
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and EGblG1S15 is the least power consuming states.
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*/
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enum TGlobalState
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{
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EGblG0 = 0xf, /**< (fixed) highest power state */
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EGblG1S1 = 0xe, /**< (fixed) */
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EGblG1S2 = 0xd, /**< (fixed) */
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EGblG1S3 = 0xc, /**< (fixed) */
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EGblG1S4 = 0xb, /**< (fixed) */
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EGblG1S5 = 0xa, /**< (fixed) */
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EGblG1S6 = 0x9, /**< (fixed) */
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EGblG1S7 = 0x8, /**< (fixed) */
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EGblG1S8 = 0x7, /**< (fixed) */
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EGblG1S9 = 0x6, /**< (fixed) */
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EGblG1S10 = 0x5, /**< (fixed) */
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EGblG1S11 = 0x4, /**< (fixed) */
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EGblG1S12 = 0x3, /**< (fixed) */
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EGblG1S13 = 0x2, /**< (fixed) */
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EGblG1S14 = 0x1, /**< (fixed) */
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EGblG1S15 = 0x0 /**< (fixed) lowest power state */
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};
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/**
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The least power consuming mode of the chipset (also called the deep sleep).
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*/
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const TInt KGblDeepSleep = EGblG1S15; /**< (fixed) */
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/**
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Power state when at least one of the generic CPUs are active (not in WFI state).
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This is the most power consuming mode of the chipset.
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*/
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const TInt KGblActive = EGblG0; /**< (fixed) */
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#endif // PM_DEFINITIONS_CHIPSET_API_H
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