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1 /* |
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2 * QEMU ETRAX Ethernet Controller. |
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3 * |
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4 * Copyright (c) 2008 Edgar E. Iglesias, Axis Communications AB. |
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5 * |
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6 * Permission is hereby granted, free of charge, to any person obtaining a copy |
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7 * of this software and associated documentation files (the "Software"), to deal |
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8 * in the Software without restriction, including without limitation the rights |
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9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
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10 * copies of the Software, and to permit persons to whom the Software is |
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11 * furnished to do so, subject to the following conditions: |
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12 * |
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13 * The above copyright notice and this permission notice shall be included in |
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14 * all copies or substantial portions of the Software. |
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15 * |
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16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
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22 * THE SOFTWARE. |
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23 */ |
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24 |
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25 #include <stdio.h> |
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26 #include "hw.h" |
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27 #include "net.h" |
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28 |
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29 #include "etraxfs_dma.h" |
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30 |
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31 #define D(x) |
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32 |
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33 /* Advertisement control register. */ |
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34 #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ |
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35 #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ |
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36 #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ |
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37 #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ |
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38 |
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39 /* |
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40 * The MDIO extensions in the TDK PHY model were reversed engineered from the |
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41 * linux driver (PHYID and Diagnostics reg). |
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42 * TODO: Add friendly names for the register nums. |
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43 */ |
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44 struct qemu_phy |
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45 { |
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46 uint32_t regs[32]; |
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47 |
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48 unsigned int (*read)(struct qemu_phy *phy, unsigned int req); |
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49 void (*write)(struct qemu_phy *phy, unsigned int req, |
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50 unsigned int data); |
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51 }; |
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52 |
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53 static unsigned int tdk_read(struct qemu_phy *phy, unsigned int req) |
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54 { |
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55 int regnum; |
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56 unsigned r = 0; |
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57 |
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58 regnum = req & 0x1f; |
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59 |
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60 switch (regnum) { |
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61 case 1: |
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62 /* MR1. */ |
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63 /* Speeds and modes. */ |
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64 r |= (1 << 13) | (1 << 14); |
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65 r |= (1 << 11) | (1 << 12); |
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66 r |= (1 << 5); /* Autoneg complete. */ |
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67 r |= (1 << 3); /* Autoneg able. */ |
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68 r |= (1 << 2); /* Link. */ |
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69 break; |
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70 case 5: |
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71 /* Link partner ability. |
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72 We are kind; always agree with whatever best mode |
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73 the guest advertises. */ |
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74 r = 1 << 14; /* Success. */ |
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75 /* Copy advertised modes. */ |
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76 r |= phy->regs[4] & (15 << 5); |
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77 /* Autoneg support. */ |
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78 r |= 1; |
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79 break; |
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80 case 18: |
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81 { |
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82 /* Diagnostics reg. */ |
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83 int duplex = 0; |
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84 int speed_100 = 0; |
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85 |
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86 /* Are we advertising 100 half or 100 duplex ? */ |
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87 speed_100 = !!(phy->regs[4] & ADVERTISE_100HALF); |
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88 speed_100 |= !!(phy->regs[4] & ADVERTISE_100FULL); |
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89 |
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90 /* Are we advertising 10 duplex or 100 duplex ? */ |
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91 duplex = !!(phy->regs[4] & ADVERTISE_100FULL); |
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92 duplex |= !!(phy->regs[4] & ADVERTISE_10FULL); |
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93 r = (speed_100 << 10) | (duplex << 11); |
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94 } |
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95 break; |
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96 |
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97 default: |
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98 r = phy->regs[regnum]; |
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99 break; |
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100 } |
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101 D(printf("\n%s %x = reg[%d]\n", __func__, r, regnum)); |
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102 return r; |
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103 } |
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104 |
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105 static void |
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106 tdk_write(struct qemu_phy *phy, unsigned int req, unsigned int data) |
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107 { |
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108 int regnum; |
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109 |
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110 regnum = req & 0x1f; |
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111 D(printf("%s reg[%d] = %x\n", __func__, regnum, data)); |
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112 switch (regnum) { |
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113 default: |
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114 phy->regs[regnum] = data; |
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115 break; |
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116 } |
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117 } |
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118 |
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119 static void |
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120 tdk_init(struct qemu_phy *phy) |
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121 { |
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122 phy->regs[0] = 0x3100; |
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123 /* PHY Id. */ |
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124 phy->regs[2] = 0x0300; |
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125 phy->regs[3] = 0xe400; |
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126 /* Autonegotiation advertisement reg. */ |
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127 phy->regs[4] = 0x01E1; |
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128 |
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129 phy->read = tdk_read; |
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130 phy->write = tdk_write; |
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131 } |
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132 |
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133 struct qemu_mdio |
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134 { |
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135 /* bus. */ |
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136 int mdc; |
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137 int mdio; |
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138 |
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139 /* decoder. */ |
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140 enum { |
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141 PREAMBLE, |
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142 SOF, |
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143 OPC, |
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144 ADDR, |
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145 REQ, |
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146 TURNAROUND, |
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147 DATA |
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148 } state; |
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149 unsigned int drive; |
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150 |
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151 unsigned int cnt; |
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152 unsigned int addr; |
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153 unsigned int opc; |
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154 unsigned int req; |
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155 unsigned int data; |
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156 |
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157 struct qemu_phy *devs[32]; |
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158 }; |
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159 |
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160 static void |
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161 mdio_attach(struct qemu_mdio *bus, struct qemu_phy *phy, unsigned int addr) |
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162 { |
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163 bus->devs[addr & 0x1f] = phy; |
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164 } |
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165 |
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166 #ifdef USE_THIS_DEAD_CODE |
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167 static void |
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168 mdio_detach(struct qemu_mdio *bus, struct qemu_phy *phy, unsigned int addr) |
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169 { |
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170 bus->devs[addr & 0x1f] = NULL; |
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171 } |
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172 #endif |
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173 |
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174 static void mdio_read_req(struct qemu_mdio *bus) |
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175 { |
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176 struct qemu_phy *phy; |
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177 |
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178 phy = bus->devs[bus->addr]; |
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179 if (phy && phy->read) |
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180 bus->data = phy->read(phy, bus->req); |
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181 else |
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182 bus->data = 0xffff; |
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183 } |
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184 |
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185 static void mdio_write_req(struct qemu_mdio *bus) |
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186 { |
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187 struct qemu_phy *phy; |
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188 |
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189 phy = bus->devs[bus->addr]; |
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190 if (phy && phy->write) |
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191 phy->write(phy, bus->req, bus->data); |
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192 } |
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193 |
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194 static void mdio_cycle(struct qemu_mdio *bus) |
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195 { |
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196 bus->cnt++; |
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197 |
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198 D(printf("mdc=%d mdio=%d state=%d cnt=%d drv=%d\n", |
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199 bus->mdc, bus->mdio, bus->state, bus->cnt, bus->drive)); |
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200 #if 0 |
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201 if (bus->mdc) |
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202 printf("%d", bus->mdio); |
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203 #endif |
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204 switch (bus->state) |
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205 { |
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206 case PREAMBLE: |
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207 if (bus->mdc) { |
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208 if (bus->cnt >= (32 * 2) && !bus->mdio) { |
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209 bus->cnt = 0; |
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210 bus->state = SOF; |
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211 bus->data = 0; |
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212 } |
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213 } |
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214 break; |
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215 case SOF: |
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216 if (bus->mdc) { |
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217 if (bus->mdio != 1) |
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218 printf("WARNING: no SOF\n"); |
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219 if (bus->cnt == 1*2) { |
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220 bus->cnt = 0; |
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221 bus->opc = 0; |
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222 bus->state = OPC; |
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223 } |
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224 } |
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225 break; |
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226 case OPC: |
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227 if (bus->mdc) { |
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228 bus->opc <<= 1; |
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229 bus->opc |= bus->mdio & 1; |
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230 if (bus->cnt == 2*2) { |
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231 bus->cnt = 0; |
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232 bus->addr = 0; |
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233 bus->state = ADDR; |
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234 } |
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235 } |
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236 break; |
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237 case ADDR: |
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238 if (bus->mdc) { |
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239 bus->addr <<= 1; |
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240 bus->addr |= bus->mdio & 1; |
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241 |
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242 if (bus->cnt == 5*2) { |
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243 bus->cnt = 0; |
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244 bus->req = 0; |
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245 bus->state = REQ; |
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246 } |
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247 } |
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248 break; |
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249 case REQ: |
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250 if (bus->mdc) { |
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251 bus->req <<= 1; |
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252 bus->req |= bus->mdio & 1; |
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253 if (bus->cnt == 5*2) { |
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254 bus->cnt = 0; |
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255 bus->state = TURNAROUND; |
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256 } |
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257 } |
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258 break; |
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259 case TURNAROUND: |
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260 if (bus->mdc && bus->cnt == 2*2) { |
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261 bus->mdio = 0; |
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262 bus->cnt = 0; |
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263 |
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264 if (bus->opc == 2) { |
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265 bus->drive = 1; |
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266 mdio_read_req(bus); |
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267 bus->mdio = bus->data & 1; |
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268 } |
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269 bus->state = DATA; |
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270 } |
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271 break; |
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272 case DATA: |
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273 if (!bus->mdc) { |
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274 if (bus->drive) { |
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275 bus->mdio = !!(bus->data & (1 << 15)); |
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276 bus->data <<= 1; |
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277 } |
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278 } else { |
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279 if (!bus->drive) { |
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280 bus->data <<= 1; |
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281 bus->data |= bus->mdio; |
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282 } |
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283 if (bus->cnt == 16 * 2) { |
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284 bus->cnt = 0; |
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285 bus->state = PREAMBLE; |
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286 if (!bus->drive) |
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287 mdio_write_req(bus); |
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288 bus->drive = 0; |
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289 } |
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290 } |
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291 break; |
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292 default: |
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293 break; |
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294 } |
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295 } |
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296 |
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297 /* ETRAX-FS Ethernet MAC block starts here. */ |
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298 |
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299 #define RW_MA0_LO 0x00 |
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300 #define RW_MA0_HI 0x04 |
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301 #define RW_MA1_LO 0x08 |
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302 #define RW_MA1_HI 0x0c |
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303 #define RW_GA_LO 0x10 |
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304 #define RW_GA_HI 0x14 |
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305 #define RW_GEN_CTRL 0x18 |
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306 #define RW_REC_CTRL 0x1c |
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307 #define RW_TR_CTRL 0x20 |
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308 #define RW_CLR_ERR 0x24 |
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309 #define RW_MGM_CTRL 0x28 |
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310 #define R_STAT 0x2c |
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311 #define FS_ETH_MAX_REGS 0x5c |
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312 |
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313 struct fs_eth |
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314 { |
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315 CPUState *env; |
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316 qemu_irq *irq; |
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317 VLANClientState *vc; |
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318 int ethregs; |
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319 |
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320 /* Two addrs in the filter. */ |
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321 uint8_t macaddr[2][6]; |
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322 uint32_t regs[FS_ETH_MAX_REGS]; |
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323 |
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324 struct etraxfs_dma_client *dma_out; |
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325 struct etraxfs_dma_client *dma_in; |
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326 |
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327 /* MDIO bus. */ |
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328 struct qemu_mdio mdio_bus; |
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329 unsigned int phyaddr; |
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330 int duplex_mismatch; |
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331 |
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332 /* PHY. */ |
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333 struct qemu_phy phy; |
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334 }; |
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335 |
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336 static void eth_validate_duplex(struct fs_eth *eth) |
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337 { |
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338 struct qemu_phy *phy; |
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339 unsigned int phy_duplex; |
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340 unsigned int mac_duplex; |
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341 int new_mm = 0; |
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342 |
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343 phy = eth->mdio_bus.devs[eth->phyaddr]; |
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344 phy_duplex = !!(phy->read(phy, 18) & (1 << 11)); |
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345 mac_duplex = !!(eth->regs[RW_REC_CTRL] & 128); |
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346 |
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347 if (mac_duplex != phy_duplex) |
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348 new_mm = 1; |
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349 |
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350 if (eth->regs[RW_GEN_CTRL] & 1) { |
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351 if (new_mm != eth->duplex_mismatch) { |
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352 if (new_mm) |
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353 printf("HW: WARNING " |
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354 "ETH duplex mismatch MAC=%d PHY=%d\n", |
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355 mac_duplex, phy_duplex); |
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356 else |
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357 printf("HW: ETH duplex ok.\n"); |
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358 } |
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359 eth->duplex_mismatch = new_mm; |
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360 } |
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361 } |
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362 |
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363 static uint32_t eth_rinvalid (void *opaque, target_phys_addr_t addr) |
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364 { |
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365 struct fs_eth *eth = opaque; |
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366 CPUState *env = eth->env; |
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367 cpu_abort(env, "Unsupported short access. reg=" TARGET_FMT_plx "\n", |
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368 addr); |
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369 return 0; |
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370 } |
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371 |
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372 static uint32_t eth_readl (void *opaque, target_phys_addr_t addr) |
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373 { |
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374 struct fs_eth *eth = opaque; |
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375 uint32_t r = 0; |
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376 |
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377 switch (addr) { |
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378 case R_STAT: |
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379 /* Attach an MDIO/PHY abstraction. */ |
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380 r = eth->mdio_bus.mdio & 1; |
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381 break; |
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382 default: |
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383 r = eth->regs[addr]; |
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384 D(printf ("%s %x\n", __func__, addr)); |
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385 break; |
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386 } |
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387 return r; |
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388 } |
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389 |
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390 static void |
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391 eth_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value) |
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392 { |
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393 struct fs_eth *eth = opaque; |
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394 CPUState *env = eth->env; |
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395 cpu_abort(env, "Unsupported short access. reg=" TARGET_FMT_plx "\n", |
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396 addr); |
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397 } |
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398 |
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399 static void eth_update_ma(struct fs_eth *eth, int ma) |
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400 { |
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401 int reg; |
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402 int i = 0; |
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403 |
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404 ma &= 1; |
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405 |
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406 reg = RW_MA0_LO; |
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407 if (ma) |
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408 reg = RW_MA1_LO; |
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409 |
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410 eth->macaddr[ma][i++] = eth->regs[reg]; |
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411 eth->macaddr[ma][i++] = eth->regs[reg] >> 8; |
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412 eth->macaddr[ma][i++] = eth->regs[reg] >> 16; |
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413 eth->macaddr[ma][i++] = eth->regs[reg] >> 24; |
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414 eth->macaddr[ma][i++] = eth->regs[reg + 4]; |
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415 eth->macaddr[ma][i++] = eth->regs[reg + 4] >> 8; |
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416 |
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417 D(printf("set mac%d=%x.%x.%x.%x.%x.%x\n", ma, |
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418 eth->macaddr[ma][0], eth->macaddr[ma][1], |
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419 eth->macaddr[ma][2], eth->macaddr[ma][3], |
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420 eth->macaddr[ma][4], eth->macaddr[ma][5])); |
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421 } |
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422 |
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423 static void |
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424 eth_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
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425 { |
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426 struct fs_eth *eth = opaque; |
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427 |
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428 switch (addr) |
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429 { |
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430 case RW_MA0_LO: |
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431 eth->regs[addr] = value; |
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432 eth_update_ma(eth, 0); |
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433 break; |
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434 case RW_MA0_HI: |
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435 eth->regs[addr] = value; |
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436 eth_update_ma(eth, 0); |
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437 break; |
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438 case RW_MA1_LO: |
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439 eth->regs[addr] = value; |
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440 eth_update_ma(eth, 1); |
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441 break; |
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442 case RW_MA1_HI: |
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443 eth->regs[addr] = value; |
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444 eth_update_ma(eth, 1); |
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445 break; |
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446 |
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447 case RW_MGM_CTRL: |
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448 /* Attach an MDIO/PHY abstraction. */ |
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449 if (value & 2) |
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450 eth->mdio_bus.mdio = value & 1; |
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451 if (eth->mdio_bus.mdc != (value & 4)) { |
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452 mdio_cycle(ð->mdio_bus); |
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453 eth_validate_duplex(eth); |
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454 } |
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455 eth->mdio_bus.mdc = !!(value & 4); |
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456 break; |
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457 |
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458 case RW_REC_CTRL: |
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459 eth->regs[addr] = value; |
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460 eth_validate_duplex(eth); |
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461 break; |
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462 |
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463 default: |
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464 eth->regs[addr] = value; |
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465 D(printf ("%s %x %x\n", |
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466 __func__, addr, value)); |
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467 break; |
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468 } |
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469 } |
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470 |
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471 /* The ETRAX FS has a groupt address table (GAT) which works like a k=1 bloom |
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472 filter dropping group addresses we have not joined. The filter has 64 |
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473 bits (m). The has function is a simple nible xor of the group addr. */ |
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474 static int eth_match_groupaddr(struct fs_eth *eth, const unsigned char *sa) |
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475 { |
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476 unsigned int hsh; |
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477 int m_individual = eth->regs[RW_REC_CTRL] & 4; |
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478 int match; |
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479 |
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480 /* First bit on the wire of a MAC address signals multicast or |
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481 physical address. */ |
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482 if (!m_individual && !sa[0] & 1) |
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483 return 0; |
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484 |
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485 /* Calculate the hash index for the GA registers. */ |
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486 hsh = 0; |
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487 hsh ^= (*sa) & 0x3f; |
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488 hsh ^= ((*sa) >> 6) & 0x03; |
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489 ++sa; |
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490 hsh ^= ((*sa) << 2) & 0x03c; |
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491 hsh ^= ((*sa) >> 4) & 0xf; |
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492 ++sa; |
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493 hsh ^= ((*sa) << 4) & 0x30; |
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494 hsh ^= ((*sa) >> 2) & 0x3f; |
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495 ++sa; |
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496 hsh ^= (*sa) & 0x3f; |
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497 hsh ^= ((*sa) >> 6) & 0x03; |
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498 ++sa; |
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499 hsh ^= ((*sa) << 2) & 0x03c; |
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500 hsh ^= ((*sa) >> 4) & 0xf; |
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501 ++sa; |
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502 hsh ^= ((*sa) << 4) & 0x30; |
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503 hsh ^= ((*sa) >> 2) & 0x3f; |
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504 |
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505 hsh &= 63; |
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506 if (hsh > 31) |
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507 match = eth->regs[RW_GA_HI] & (1 << (hsh - 32)); |
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508 else |
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509 match = eth->regs[RW_GA_LO] & (1 << hsh); |
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510 D(printf("hsh=%x ga=%x.%x mtch=%d\n", hsh, |
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511 eth->regs[RW_GA_HI], eth->regs[RW_GA_LO], match)); |
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512 return match; |
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513 } |
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514 |
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515 static int eth_can_receive(void *opaque) |
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516 { |
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517 return 1; |
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518 } |
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519 |
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520 static void eth_receive(void *opaque, const uint8_t *buf, int size) |
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521 { |
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522 unsigned char sa_bcast[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; |
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523 struct fs_eth *eth = opaque; |
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524 int use_ma0 = eth->regs[RW_REC_CTRL] & 1; |
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525 int use_ma1 = eth->regs[RW_REC_CTRL] & 2; |
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526 int r_bcast = eth->regs[RW_REC_CTRL] & 8; |
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527 |
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528 if (size < 12) |
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529 return; |
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530 |
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531 D(printf("%x.%x.%x.%x.%x.%x ma=%d %d bc=%d\n", |
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532 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], |
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533 use_ma0, use_ma1, r_bcast)); |
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534 |
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535 /* Does the frame get through the address filters? */ |
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536 if ((!use_ma0 || memcmp(buf, eth->macaddr[0], 6)) |
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537 && (!use_ma1 || memcmp(buf, eth->macaddr[1], 6)) |
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538 && (!r_bcast || memcmp(buf, sa_bcast, 6)) |
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539 && !eth_match_groupaddr(eth, buf)) |
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540 return; |
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541 |
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542 /* FIXME: Find another way to pass on the fake csum. */ |
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543 etraxfs_dmac_input(eth->dma_in, (void *)buf, size + 4, 1); |
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544 } |
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545 |
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546 static int eth_tx_push(void *opaque, unsigned char *buf, int len) |
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547 { |
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548 struct fs_eth *eth = opaque; |
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549 |
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550 D(printf("%s buf=%p len=%d\n", __func__, buf, len)); |
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551 qemu_send_packet(eth->vc, buf, len); |
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552 return len; |
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553 } |
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554 |
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555 static CPUReadMemoryFunc *eth_read[] = { |
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556 ð_rinvalid, |
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557 ð_rinvalid, |
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558 ð_readl, |
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559 }; |
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560 |
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561 static CPUWriteMemoryFunc *eth_write[] = { |
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562 ð_winvalid, |
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563 ð_winvalid, |
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564 ð_writel, |
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565 }; |
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566 |
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567 void *etraxfs_eth_init(NICInfo *nd, CPUState *env, |
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568 qemu_irq *irq, target_phys_addr_t base) |
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569 { |
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570 struct etraxfs_dma_client *dma = NULL; |
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571 struct fs_eth *eth = NULL; |
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572 |
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573 dma = qemu_mallocz(sizeof *dma * 2); |
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574 if (!dma) |
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575 return NULL; |
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576 |
|
577 eth = qemu_mallocz(sizeof *eth); |
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578 if (!eth) |
|
579 goto err; |
|
580 |
|
581 dma[0].client.push = eth_tx_push; |
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582 dma[0].client.opaque = eth; |
|
583 dma[1].client.opaque = eth; |
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584 dma[1].client.pull = NULL; |
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585 |
|
586 eth->env = env; |
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587 eth->irq = irq; |
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588 eth->dma_out = dma; |
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589 eth->dma_in = dma + 1; |
|
590 |
|
591 /* Connect the phy. */ |
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592 eth->phyaddr = 1; |
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593 tdk_init(ð->phy); |
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594 mdio_attach(ð->mdio_bus, ð->phy, eth->phyaddr); |
|
595 |
|
596 eth->ethregs = cpu_register_io_memory(0, eth_read, eth_write, eth); |
|
597 cpu_register_physical_memory (base, 0x5c, eth->ethregs); |
|
598 |
|
599 eth->vc = qemu_new_vlan_client(nd->vlan, |
|
600 eth_receive, eth_can_receive, eth); |
|
601 |
|
602 return dma; |
|
603 err: |
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604 qemu_free(eth); |
|
605 qemu_free(dma); |
|
606 return NULL; |
|
607 } |