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1 /* |
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2 * National Semiconductor LM8322/8323 GPIO keyboard & PWM chips. |
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3 * |
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4 * Copyright (C) 2008 Nokia Corporation |
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5 * Written by Andrzej Zaborowski <andrew@openedhand.com> |
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6 * |
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7 * This program is free software; you can redistribute it and/or |
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8 * modify it under the terms of the GNU General Public License as |
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9 * published by the Free Software Foundation; either version 2 or |
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10 * (at your option) version 3 of the License. |
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11 * |
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12 * This program is distributed in the hope that it will be useful, |
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13 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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15 * GNU General Public License for more details. |
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16 * |
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17 * You should have received a copy of the GNU General Public License |
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18 * along with this program; if not, write to the Free Software |
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19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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20 * MA 02111-1307 USA |
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21 */ |
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22 |
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23 #include "hw.h" |
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24 #include "i2c.h" |
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25 #include "qemu-timer.h" |
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26 #include "console.h" |
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27 |
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28 struct lm_kbd_s { |
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29 i2c_slave i2c; |
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30 int i2c_dir; |
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31 int i2c_cycle; |
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32 int reg; |
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33 |
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34 qemu_irq nirq; |
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35 uint16_t model; |
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36 |
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37 struct { |
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38 qemu_irq out[2]; |
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39 int in[2][2]; |
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40 } mux; |
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41 |
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42 uint8_t config; |
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43 uint8_t status; |
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44 uint8_t acttime; |
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45 uint8_t error; |
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46 uint8_t clock; |
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47 |
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48 struct { |
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49 uint16_t pull; |
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50 uint16_t mask; |
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51 uint16_t dir; |
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52 uint16_t level; |
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53 qemu_irq out[16]; |
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54 } gpio; |
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55 |
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56 struct { |
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57 uint8_t dbnctime; |
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58 uint8_t size; |
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59 int start; |
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60 int len; |
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61 uint8_t fifo[16]; |
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62 } kbd; |
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63 |
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64 struct { |
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65 uint16_t file[256]; |
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66 uint8_t faddr; |
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67 uint8_t addr[3]; |
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68 QEMUTimer *tm[3]; |
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69 } pwm; |
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70 }; |
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71 |
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72 #define INT_KEYPAD (1 << 0) |
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73 #define INT_ERROR (1 << 3) |
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74 #define INT_NOINIT (1 << 4) |
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75 #define INT_PWMEND(n) (1 << (5 + n)) |
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76 |
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77 #define ERR_BADPAR (1 << 0) |
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78 #define ERR_CMDUNK (1 << 1) |
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79 #define ERR_KEYOVR (1 << 2) |
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80 #define ERR_FIFOOVR (1 << 6) |
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81 |
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82 static void lm_kbd_irq_update(struct lm_kbd_s *s) |
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83 { |
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84 qemu_set_irq(s->nirq, !s->status); |
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85 } |
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86 |
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87 static void lm_kbd_gpio_update(struct lm_kbd_s *s) |
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88 { |
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89 } |
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90 |
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91 static void lm_kbd_reset(struct lm_kbd_s *s) |
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92 { |
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93 s->config = 0x80; |
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94 s->status = INT_NOINIT; |
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95 s->acttime = 125; |
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96 s->kbd.dbnctime = 3; |
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97 s->kbd.size = 0x33; |
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98 s->clock = 0x08; |
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99 |
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100 lm_kbd_irq_update(s); |
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101 lm_kbd_gpio_update(s); |
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102 } |
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103 |
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104 static void lm_kbd_error(struct lm_kbd_s *s, int err) |
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105 { |
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106 s->error |= err; |
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107 s->status |= INT_ERROR; |
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108 lm_kbd_irq_update(s); |
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109 } |
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110 |
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111 static void lm_kbd_pwm_tick(struct lm_kbd_s *s, int line) |
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112 { |
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113 } |
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114 |
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115 static void lm_kbd_pwm_start(struct lm_kbd_s *s, int line) |
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116 { |
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117 lm_kbd_pwm_tick(s, line); |
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118 } |
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119 |
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120 static void lm_kbd_pwm0_tick(void *opaque) |
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121 { |
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122 lm_kbd_pwm_tick(opaque, 0); |
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123 } |
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124 static void lm_kbd_pwm1_tick(void *opaque) |
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125 { |
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126 lm_kbd_pwm_tick(opaque, 1); |
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127 } |
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128 static void lm_kbd_pwm2_tick(void *opaque) |
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129 { |
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130 lm_kbd_pwm_tick(opaque, 2); |
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131 } |
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132 |
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133 enum { |
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134 LM832x_CMD_READ_ID = 0x80, /* Read chip ID. */ |
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135 LM832x_CMD_WRITE_CFG = 0x81, /* Set configuration item. */ |
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136 LM832x_CMD_READ_INT = 0x82, /* Get interrupt status. */ |
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137 LM832x_CMD_RESET = 0x83, /* Reset, same as external one */ |
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138 LM823x_CMD_WRITE_PULL_DOWN = 0x84, /* Select GPIO pull-up/down. */ |
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139 LM832x_CMD_WRITE_PORT_SEL = 0x85, /* Select GPIO in/out. */ |
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140 LM832x_CMD_WRITE_PORT_STATE = 0x86, /* Set GPIO pull-up/down. */ |
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141 LM832x_CMD_READ_PORT_SEL = 0x87, /* Get GPIO in/out. */ |
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142 LM832x_CMD_READ_PORT_STATE = 0x88, /* Get GPIO pull-up/down. */ |
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143 LM832x_CMD_READ_FIFO = 0x89, /* Read byte from FIFO. */ |
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144 LM832x_CMD_RPT_READ_FIFO = 0x8a, /* Read FIFO (no increment). */ |
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145 LM832x_CMD_SET_ACTIVE = 0x8b, /* Set active time. */ |
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146 LM832x_CMD_READ_ERROR = 0x8c, /* Get error status. */ |
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147 LM832x_CMD_READ_ROTATOR = 0x8e, /* Read rotator status. */ |
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148 LM832x_CMD_SET_DEBOUNCE = 0x8f, /* Set debouncing time. */ |
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149 LM832x_CMD_SET_KEY_SIZE = 0x90, /* Set keypad size. */ |
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150 LM832x_CMD_READ_KEY_SIZE = 0x91, /* Get keypad size. */ |
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151 LM832x_CMD_READ_CFG = 0x92, /* Get configuration item. */ |
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152 LM832x_CMD_WRITE_CLOCK = 0x93, /* Set clock config. */ |
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153 LM832x_CMD_READ_CLOCK = 0x94, /* Get clock config. */ |
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154 LM832x_CMD_PWM_WRITE = 0x95, /* Write PWM script. */ |
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155 LM832x_CMD_PWM_START = 0x96, /* Start PWM engine. */ |
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156 LM832x_CMD_PWM_STOP = 0x97, /* Stop PWM engine. */ |
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157 }; |
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158 |
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159 #define LM832x_MAX_KPX 8 |
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160 #define LM832x_MAX_KPY 12 |
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161 |
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162 static uint8_t lm_kbd_read(struct lm_kbd_s *s, int reg, int byte) |
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163 { |
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164 int ret; |
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165 |
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166 switch (reg) { |
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167 case LM832x_CMD_READ_ID: |
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168 ret = 0x0400; |
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169 break; |
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170 |
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171 case LM832x_CMD_READ_INT: |
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172 ret = s->status; |
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173 if (!(s->status & INT_NOINIT)) { |
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174 s->status = 0; |
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175 lm_kbd_irq_update(s); |
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176 } |
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177 break; |
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178 |
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179 case LM832x_CMD_READ_PORT_SEL: |
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180 ret = s->gpio.dir; |
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181 break; |
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182 case LM832x_CMD_READ_PORT_STATE: |
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183 ret = s->gpio.mask; |
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184 break; |
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185 |
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186 case LM832x_CMD_READ_FIFO: |
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187 if (s->kbd.len <= 1) |
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188 return 0x00; |
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189 |
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190 /* Example response from the two commands after a INT_KEYPAD |
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191 * interrupt caused by the key 0x3c being pressed: |
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192 * RPT_READ_FIFO: 55 bc 00 4e ff 0a 50 08 00 29 d9 08 01 c9 01 |
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193 * READ_FIFO: bc 00 00 4e ff 0a 50 08 00 29 d9 08 01 c9 01 |
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194 * RPT_READ_FIFO: bc 00 00 4e ff 0a 50 08 00 29 d9 08 01 c9 01 |
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195 * |
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196 * 55 is the code of the key release event serviced in the previous |
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197 * interrupt handling. |
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198 * |
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199 * TODO: find out whether the FIFO is advanced a single character |
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200 * before reading every byte or the whole size of the FIFO at the |
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201 * last LM832x_CMD_READ_FIFO. This affects LM832x_CMD_RPT_READ_FIFO |
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202 * output in cases where there are more than one event in the FIFO. |
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203 * Assume 0xbc and 0x3c events are in the FIFO: |
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204 * RPT_READ_FIFO: 55 bc 3c 00 4e ff 0a 50 08 00 29 d9 08 01 c9 |
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205 * READ_FIFO: bc 3c 00 00 4e ff 0a 50 08 00 29 d9 08 01 c9 |
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206 * Does RPT_READ_FIFO now return 0xbc and 0x3c or only 0x3c? |
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207 */ |
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208 s->kbd.start ++; |
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209 s->kbd.start &= sizeof(s->kbd.fifo) - 1; |
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210 s->kbd.len --; |
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211 |
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212 return s->kbd.fifo[s->kbd.start]; |
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213 case LM832x_CMD_RPT_READ_FIFO: |
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214 if (byte >= s->kbd.len) |
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215 return 0x00; |
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216 |
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217 return s->kbd.fifo[(s->kbd.start + byte) & (sizeof(s->kbd.fifo) - 1)]; |
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218 |
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219 case LM832x_CMD_READ_ERROR: |
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220 return s->error; |
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221 |
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222 case LM832x_CMD_READ_ROTATOR: |
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223 return 0; |
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224 |
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225 case LM832x_CMD_READ_KEY_SIZE: |
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226 return s->kbd.size; |
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227 |
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228 case LM832x_CMD_READ_CFG: |
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229 return s->config & 0xf; |
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230 |
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231 case LM832x_CMD_READ_CLOCK: |
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232 return (s->clock & 0xfc) | 2; |
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233 |
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234 default: |
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235 lm_kbd_error(s, ERR_CMDUNK); |
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236 fprintf(stderr, "%s: unknown command %02x\n", __FUNCTION__, reg); |
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237 return 0x00; |
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238 } |
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239 |
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240 return ret >> (byte << 3); |
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241 } |
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242 |
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243 static void lm_kbd_write(struct lm_kbd_s *s, int reg, int byte, uint8_t value) |
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244 { |
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245 switch (reg) { |
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246 case LM832x_CMD_WRITE_CFG: |
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247 s->config = value; |
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248 /* This must be done whenever s->mux.in is updated (never). */ |
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249 if ((s->config >> 1) & 1) /* MUX1EN */ |
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250 qemu_set_irq(s->mux.out[0], s->mux.in[0][(s->config >> 0) & 1]); |
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251 if ((s->config >> 3) & 1) /* MUX2EN */ |
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252 qemu_set_irq(s->mux.out[0], s->mux.in[0][(s->config >> 2) & 1]); |
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253 /* TODO: check that this is issued only following the chip reset |
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254 * and not in the middle of operation and that it is followed by |
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255 * the GPIO ports re-resablishing through WRITE_PORT_SEL and |
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256 * WRITE_PORT_STATE (using a timer perhaps) and otherwise output |
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257 * warnings. */ |
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258 s->status = 0; |
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259 lm_kbd_irq_update(s); |
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260 s->kbd.len = 0; |
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261 s->kbd.start = 0; |
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262 s->reg = -1; |
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263 break; |
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264 |
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265 case LM832x_CMD_RESET: |
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266 if (value == 0xaa) |
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267 lm_kbd_reset(s); |
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268 else |
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269 lm_kbd_error(s, ERR_BADPAR); |
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270 s->reg = -1; |
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271 break; |
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272 |
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273 case LM823x_CMD_WRITE_PULL_DOWN: |
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274 if (!byte) |
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275 s->gpio.pull = value; |
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276 else { |
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277 s->gpio.pull |= value << 8; |
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278 lm_kbd_gpio_update(s); |
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279 s->reg = -1; |
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280 } |
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281 break; |
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282 case LM832x_CMD_WRITE_PORT_SEL: |
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283 if (!byte) |
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284 s->gpio.dir = value; |
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285 else { |
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286 s->gpio.dir |= value << 8; |
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287 lm_kbd_gpio_update(s); |
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288 s->reg = -1; |
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289 } |
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290 break; |
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291 case LM832x_CMD_WRITE_PORT_STATE: |
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292 if (!byte) |
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293 s->gpio.mask = value; |
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294 else { |
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295 s->gpio.mask |= value << 8; |
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296 lm_kbd_gpio_update(s); |
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297 s->reg = -1; |
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298 } |
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299 break; |
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300 |
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301 case LM832x_CMD_SET_ACTIVE: |
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302 s->acttime = value; |
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303 s->reg = -1; |
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304 break; |
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305 |
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306 case LM832x_CMD_SET_DEBOUNCE: |
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307 s->kbd.dbnctime = value; |
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308 s->reg = -1; |
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309 if (!value) |
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310 lm_kbd_error(s, ERR_BADPAR); |
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311 break; |
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312 |
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313 case LM832x_CMD_SET_KEY_SIZE: |
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314 s->kbd.size = value; |
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315 s->reg = -1; |
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316 if ( |
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317 (value & 0xf) < 3 || (value & 0xf) > LM832x_MAX_KPY || |
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318 (value >> 4) < 3 || (value >> 4) > LM832x_MAX_KPX) |
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319 lm_kbd_error(s, ERR_BADPAR); |
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320 break; |
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321 |
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322 case LM832x_CMD_WRITE_CLOCK: |
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323 s->clock = value; |
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324 s->reg = -1; |
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325 if ((value & 3) && (value & 3) != 3) { |
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326 lm_kbd_error(s, ERR_BADPAR); |
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327 fprintf(stderr, "%s: invalid clock setting in RCPWM\n", |
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328 __FUNCTION__); |
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329 } |
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330 /* TODO: Validate that the command is only issued once */ |
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331 break; |
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332 |
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333 case LM832x_CMD_PWM_WRITE: |
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334 if (byte == 0) { |
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335 if (!(value & 3) || (value >> 2) > 59) { |
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336 lm_kbd_error(s, ERR_BADPAR); |
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337 s->reg = -1; |
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338 break; |
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339 } |
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340 |
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341 s->pwm.faddr = value; |
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342 s->pwm.file[s->pwm.faddr] = 0; |
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343 } else if (byte == 1) { |
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344 s->pwm.file[s->pwm.faddr] |= value << 8; |
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345 } else if (byte == 2) { |
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346 s->pwm.file[s->pwm.faddr] |= value << 0; |
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347 s->reg = -1; |
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348 } |
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349 break; |
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350 case LM832x_CMD_PWM_START: |
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351 s->reg = -1; |
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352 if (!(value & 3) || (value >> 2) > 59) { |
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353 lm_kbd_error(s, ERR_BADPAR); |
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354 break; |
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355 } |
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356 |
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357 s->pwm.addr[(value & 3) - 1] = value >> 2; |
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358 lm_kbd_pwm_start(s, (value & 3) - 1); |
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359 break; |
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360 case LM832x_CMD_PWM_STOP: |
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361 s->reg = -1; |
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362 if (!(value & 3)) { |
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363 lm_kbd_error(s, ERR_BADPAR); |
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364 break; |
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365 } |
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366 |
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367 qemu_del_timer(s->pwm.tm[(value & 3) - 1]); |
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368 break; |
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369 |
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370 case -1: |
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371 lm_kbd_error(s, ERR_BADPAR); |
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372 break; |
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373 default: |
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374 lm_kbd_error(s, ERR_CMDUNK); |
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375 fprintf(stderr, "%s: unknown command %02x\n", __FUNCTION__, reg); |
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376 break; |
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377 } |
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378 } |
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379 |
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380 static void lm_i2c_event(i2c_slave *i2c, enum i2c_event event) |
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381 { |
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382 struct lm_kbd_s *s = (struct lm_kbd_s *) i2c; |
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383 |
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384 switch (event) { |
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385 case I2C_START_RECV: |
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386 case I2C_START_SEND: |
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387 s->i2c_cycle = 0; |
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388 s->i2c_dir = (event == I2C_START_SEND); |
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389 break; |
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390 |
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391 default: |
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392 break; |
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393 } |
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394 } |
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395 |
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396 static int lm_i2c_rx(i2c_slave *i2c) |
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397 { |
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398 struct lm_kbd_s *s = (struct lm_kbd_s *) i2c; |
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399 |
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400 return lm_kbd_read(s, s->reg, s->i2c_cycle ++); |
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401 } |
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402 |
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403 static int lm_i2c_tx(i2c_slave *i2c, uint8_t data) |
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404 { |
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405 struct lm_kbd_s *s = (struct lm_kbd_s *) i2c; |
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406 |
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407 if (!s->i2c_cycle) |
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408 s->reg = data; |
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409 else |
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410 lm_kbd_write(s, s->reg, s->i2c_cycle - 1, data); |
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411 s->i2c_cycle ++; |
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412 |
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413 return 0; |
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414 } |
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415 |
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416 static void lm_kbd_save(QEMUFile *f, void *opaque) |
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417 { |
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418 struct lm_kbd_s *s = (struct lm_kbd_s *) opaque; |
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419 int i; |
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420 |
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421 i2c_slave_save(f, &s->i2c); |
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422 qemu_put_byte(f, s->i2c_dir); |
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423 qemu_put_byte(f, s->i2c_cycle); |
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424 qemu_put_byte(f, (uint8_t) s->reg); |
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425 |
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426 qemu_put_8s(f, &s->config); |
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427 qemu_put_8s(f, &s->status); |
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428 qemu_put_8s(f, &s->acttime); |
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429 qemu_put_8s(f, &s->error); |
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430 qemu_put_8s(f, &s->clock); |
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431 |
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432 qemu_put_be16s(f, &s->gpio.pull); |
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433 qemu_put_be16s(f, &s->gpio.mask); |
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434 qemu_put_be16s(f, &s->gpio.dir); |
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435 qemu_put_be16s(f, &s->gpio.level); |
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436 |
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437 qemu_put_byte(f, s->kbd.dbnctime); |
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438 qemu_put_byte(f, s->kbd.size); |
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439 qemu_put_byte(f, s->kbd.start); |
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440 qemu_put_byte(f, s->kbd.len); |
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441 qemu_put_buffer(f, s->kbd.fifo, sizeof(s->kbd.fifo)); |
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442 |
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443 for (i = 0; i < sizeof(s->pwm.file); i ++) |
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444 qemu_put_be16s(f, &s->pwm.file[i]); |
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445 qemu_put_8s(f, &s->pwm.faddr); |
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446 qemu_put_buffer(f, s->pwm.addr, sizeof(s->pwm.addr)); |
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447 qemu_put_timer(f, s->pwm.tm[0]); |
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448 qemu_put_timer(f, s->pwm.tm[1]); |
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449 qemu_put_timer(f, s->pwm.tm[2]); |
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450 } |
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451 |
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452 static int lm_kbd_load(QEMUFile *f, void *opaque, int version_id) |
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453 { |
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454 struct lm_kbd_s *s = (struct lm_kbd_s *) opaque; |
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455 int i; |
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456 |
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457 i2c_slave_load(f, &s->i2c); |
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458 s->i2c_dir = qemu_get_byte(f); |
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459 s->i2c_cycle = qemu_get_byte(f); |
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460 s->reg = (int8_t) qemu_get_byte(f); |
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461 |
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462 qemu_get_8s(f, &s->config); |
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463 qemu_get_8s(f, &s->status); |
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464 qemu_get_8s(f, &s->acttime); |
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465 qemu_get_8s(f, &s->error); |
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466 qemu_get_8s(f, &s->clock); |
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467 |
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468 qemu_get_be16s(f, &s->gpio.pull); |
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469 qemu_get_be16s(f, &s->gpio.mask); |
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470 qemu_get_be16s(f, &s->gpio.dir); |
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471 qemu_get_be16s(f, &s->gpio.level); |
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472 |
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473 s->kbd.dbnctime = qemu_get_byte(f); |
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474 s->kbd.size = qemu_get_byte(f); |
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475 s->kbd.start = qemu_get_byte(f); |
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476 s->kbd.len = qemu_get_byte(f); |
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477 qemu_get_buffer(f, s->kbd.fifo, sizeof(s->kbd.fifo)); |
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478 |
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479 for (i = 0; i < sizeof(s->pwm.file); i ++) |
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480 qemu_get_be16s(f, &s->pwm.file[i]); |
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481 qemu_get_8s(f, &s->pwm.faddr); |
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482 qemu_get_buffer(f, s->pwm.addr, sizeof(s->pwm.addr)); |
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483 qemu_get_timer(f, s->pwm.tm[0]); |
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484 qemu_get_timer(f, s->pwm.tm[1]); |
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485 qemu_get_timer(f, s->pwm.tm[2]); |
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486 |
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487 lm_kbd_irq_update(s); |
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488 lm_kbd_gpio_update(s); |
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489 |
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490 return 0; |
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491 } |
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492 |
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493 struct i2c_slave *lm8323_init(i2c_bus *bus, qemu_irq nirq) |
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494 { |
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495 struct lm_kbd_s *s; |
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496 |
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497 s = (struct lm_kbd_s *) i2c_slave_init(bus, 0, sizeof(struct lm_kbd_s)); |
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498 s->model = 0x8323; |
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499 s->pwm.tm[0] = qemu_new_timer(vm_clock, lm_kbd_pwm0_tick, s); |
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500 s->pwm.tm[1] = qemu_new_timer(vm_clock, lm_kbd_pwm1_tick, s); |
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501 s->pwm.tm[2] = qemu_new_timer(vm_clock, lm_kbd_pwm2_tick, s); |
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502 s->nirq = nirq; |
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503 |
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504 s->i2c.event = lm_i2c_event; |
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505 s->i2c.recv = lm_i2c_rx; |
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506 s->i2c.send = lm_i2c_tx; |
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507 |
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508 lm_kbd_reset(s); |
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509 |
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510 qemu_register_reset((void *) lm_kbd_reset, s); |
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511 register_savevm("LM8323", -1, 0, lm_kbd_save, lm_kbd_load, s); |
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512 |
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513 return &s->i2c; |
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514 } |
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515 |
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516 void lm832x_key_event(struct i2c_slave *i2c, int key, int state) |
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517 { |
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518 struct lm_kbd_s *s = (struct lm_kbd_s *) i2c; |
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519 |
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520 if ((s->status & INT_ERROR) && (s->error & ERR_FIFOOVR)) |
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521 return; |
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522 |
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523 if (s->kbd.len >= sizeof(s->kbd.fifo)) |
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524 return lm_kbd_error(s, ERR_FIFOOVR); |
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525 |
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526 s->kbd.fifo[(s->kbd.start + s->kbd.len ++) & (sizeof(s->kbd.fifo) - 1)] = |
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527 key | (state << 7); |
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528 |
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529 /* We never set ERR_KEYOVR because we support multiple keys fine. */ |
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530 s->status |= INT_KEYPAD; |
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531 lm_kbd_irq_update(s); |
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532 } |