|
1 /* |
|
2 * Nokia N-series internet tablets. |
|
3 * |
|
4 * Copyright (C) 2007 Nokia Corporation |
|
5 * Written by Andrzej Zaborowski <andrew@openedhand.com> |
|
6 * |
|
7 * This program is free software; you can redistribute it and/or |
|
8 * modify it under the terms of the GNU General Public License as |
|
9 * published by the Free Software Foundation; either version 2 or |
|
10 * (at your option) version 3 of the License. |
|
11 * |
|
12 * This program is distributed in the hope that it will be useful, |
|
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
15 * GNU General Public License for more details. |
|
16 * |
|
17 * You should have received a copy of the GNU General Public License |
|
18 * along with this program; if not, write to the Free Software |
|
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
|
20 * MA 02111-1307 USA |
|
21 */ |
|
22 |
|
23 #include "qemu-common.h" |
|
24 #include "sysemu.h" |
|
25 #include "omap.h" |
|
26 #include "arm-misc.h" |
|
27 #include "irq.h" |
|
28 #include "console.h" |
|
29 #include "gui.h" |
|
30 #include "boards.h" |
|
31 #include "i2c.h" |
|
32 #include "devices.h" |
|
33 #include "flash.h" |
|
34 #include "hw.h" |
|
35 #include "bt.h" |
|
36 |
|
37 /* Nokia N8x0 support */ |
|
38 struct n800_s { |
|
39 struct omap_mpu_state_s *cpu; |
|
40 |
|
41 struct rfbi_chip_s blizzard; |
|
42 struct { |
|
43 void *opaque; |
|
44 uint32_t (*txrx)(void *opaque, uint32_t value, int len); |
|
45 struct uwire_slave_s *chip; |
|
46 } ts; |
|
47 i2c_bus *i2c; |
|
48 |
|
49 int keymap[0x80]; |
|
50 i2c_slave *kbd; |
|
51 |
|
52 struct tusb_s *usb; |
|
53 void *retu; |
|
54 void *tahvo; |
|
55 void *nand; |
|
56 }; |
|
57 |
|
58 /* GPIO pins */ |
|
59 #define N8X0_TUSB_ENABLE_GPIO 0 |
|
60 #define N800_MMC2_WP_GPIO 8 |
|
61 #define N800_UNKNOWN_GPIO0 9 /* out */ |
|
62 #define N810_MMC2_VIOSD_GPIO 9 |
|
63 #define N810_HEADSET_AMP_GPIO 10 |
|
64 #define N800_CAM_TURN_GPIO 12 |
|
65 #define N810_GPS_RESET_GPIO 12 |
|
66 #define N800_BLIZZARD_POWERDOWN_GPIO 15 |
|
67 #define N800_MMC1_WP_GPIO 23 |
|
68 #define N810_MMC2_VSD_GPIO 23 |
|
69 #define N8X0_ONENAND_GPIO 26 |
|
70 #define N810_BLIZZARD_RESET_GPIO 30 |
|
71 #define N800_UNKNOWN_GPIO2 53 /* out */ |
|
72 #define N8X0_TUSB_INT_GPIO 58 |
|
73 #define N8X0_BT_WKUP_GPIO 61 |
|
74 #define N8X0_STI_GPIO 62 |
|
75 #define N8X0_CBUS_SEL_GPIO 64 |
|
76 #define N8X0_CBUS_DAT_GPIO 65 |
|
77 #define N8X0_CBUS_CLK_GPIO 66 |
|
78 #define N8X0_WLAN_IRQ_GPIO 87 |
|
79 #define N8X0_BT_RESET_GPIO 92 |
|
80 #define N8X0_TEA5761_CS_GPIO 93 |
|
81 #define N800_UNKNOWN_GPIO 94 |
|
82 #define N810_TSC_RESET_GPIO 94 |
|
83 #define N800_CAM_ACT_GPIO 95 |
|
84 #define N810_GPS_WAKEUP_GPIO 95 |
|
85 #define N8X0_MMC_CS_GPIO 96 |
|
86 #define N8X0_WLAN_PWR_GPIO 97 |
|
87 #define N8X0_BT_HOST_WKUP_GPIO 98 |
|
88 #define N810_SPEAKER_AMP_GPIO 101 |
|
89 #define N810_KB_LOCK_GPIO 102 |
|
90 #define N800_TSC_TS_GPIO 103 |
|
91 #define N810_TSC_TS_GPIO 106 |
|
92 #define N8X0_HEADPHONE_GPIO 107 |
|
93 #define N8X0_RETU_GPIO 108 |
|
94 #define N800_TSC_KP_IRQ_GPIO 109 |
|
95 #define N810_KEYBOARD_GPIO 109 |
|
96 #define N800_BAT_COVER_GPIO 110 |
|
97 #define N810_SLIDE_GPIO 110 |
|
98 #define N8X0_TAHVO_GPIO 111 |
|
99 #define N800_UNKNOWN_GPIO4 112 /* out */ |
|
100 #define N810_SLEEPX_LED_GPIO 112 |
|
101 #define N800_TSC_RESET_GPIO 118 /* ? */ |
|
102 #define N810_AIC33_RESET_GPIO 118 |
|
103 #define N800_TSC_UNKNOWN_GPIO 119 /* out */ |
|
104 #define N8X0_TMP105_GPIO 125 |
|
105 |
|
106 /* Config */ |
|
107 #define BT_UART 0 |
|
108 #define XLDR_LL_UART 1 |
|
109 |
|
110 /* Addresses on the I2C bus 0 */ |
|
111 #define N810_TLV320AIC33_ADDR 0x18 /* Audio CODEC */ |
|
112 #define N8X0_TCM825x_ADDR 0x29 /* Camera */ |
|
113 #define N810_LP5521_ADDR 0x32 /* LEDs */ |
|
114 #define N810_TSL2563_ADDR 0x3d /* Light sensor */ |
|
115 #define N810_LM8323_ADDR 0x45 /* Keyboard */ |
|
116 /* Addresses on the I2C bus 1 */ |
|
117 #define N8X0_TMP105_ADDR 0x48 /* Temperature sensor */ |
|
118 #define N8X0_MENELAUS_ADDR 0x72 /* Power management */ |
|
119 |
|
120 /* Chipselects on GPMC NOR interface */ |
|
121 #define N8X0_ONENAND_CS 0 |
|
122 #define N8X0_USB_ASYNC_CS 1 |
|
123 #define N8X0_USB_SYNC_CS 4 |
|
124 |
|
125 #define N8X0_BD_ADDR 0x00, 0x1a, 0x89, 0x9e, 0x3e, 0x81 |
|
126 |
|
127 static void n800_mmc_cs_cb(void *opaque, int line, int level) |
|
128 { |
|
129 /* TODO: this seems to actually be connected to the menelaus, to |
|
130 * which also both MMC slots connect. */ |
|
131 omap_mmc_enable((struct omap_mmc_s *) opaque, !level); |
|
132 |
|
133 printf("%s: MMC slot %i active\n", __FUNCTION__, level + 1); |
|
134 } |
|
135 |
|
136 static void n8x0_gpio_setup(struct n800_s *s) |
|
137 { |
|
138 qemu_irq *mmc_cs = qemu_allocate_irqs(n800_mmc_cs_cb, s->cpu->mmc, 1); |
|
139 omap2_gpio_out_set(s->cpu->gpif, N8X0_MMC_CS_GPIO, mmc_cs[0]); |
|
140 |
|
141 qemu_irq_lower(omap2_gpio_in_get(s->cpu->gpif, N800_BAT_COVER_GPIO)[0]); |
|
142 } |
|
143 |
|
144 #define MAEMO_CAL_HEADER(...) \ |
|
145 'C', 'o', 'n', 'F', 0x02, 0x00, 0x04, 0x00, \ |
|
146 __VA_ARGS__, \ |
|
147 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, |
|
148 |
|
149 static const uint8_t n8x0_cal_wlan_mac[] = { |
|
150 MAEMO_CAL_HEADER('w', 'l', 'a', 'n', '-', 'm', 'a', 'c') |
|
151 0x1c, 0x00, 0x00, 0x00, 0x47, 0xd6, 0x69, 0xb3, |
|
152 0x30, 0x08, 0xa0, 0x83, 0x00, 0x00, 0x00, 0x00, |
|
153 0x00, 0x00, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x00, |
|
154 0x89, 0x00, 0x00, 0x00, 0x9e, 0x00, 0x00, 0x00, |
|
155 0x5d, 0x00, 0x00, 0x00, 0xc1, 0x00, 0x00, 0x00, |
|
156 }; |
|
157 |
|
158 static const uint8_t n8x0_cal_bt_id[] = { |
|
159 MAEMO_CAL_HEADER('b', 't', '-', 'i', 'd', 0, 0, 0) |
|
160 0x0a, 0x00, 0x00, 0x00, 0xa3, 0x4b, 0xf6, 0x96, |
|
161 0xa8, 0xeb, 0xb2, 0x41, 0x00, 0x00, 0x00, 0x00, |
|
162 N8X0_BD_ADDR, |
|
163 }; |
|
164 |
|
165 static void n8x0_nand_setup(struct n800_s *s) |
|
166 { |
|
167 char *otp_region; |
|
168 |
|
169 /* Either ec40xx or ec48xx are OK for the ID */ |
|
170 omap_gpmc_attach(s->cpu->gpmc, N8X0_ONENAND_CS, 0, onenand_base_update, |
|
171 onenand_base_unmap, |
|
172 (s->nand = onenand_init(0xec4800, 1, |
|
173 omap2_gpio_in_get(s->cpu->gpif, |
|
174 N8X0_ONENAND_GPIO)[0]))); |
|
175 otp_region = onenand_raw_otp(s->nand); |
|
176 |
|
177 memcpy(otp_region + 0x000, n8x0_cal_wlan_mac, sizeof(n8x0_cal_wlan_mac)); |
|
178 memcpy(otp_region + 0x800, n8x0_cal_bt_id, sizeof(n8x0_cal_bt_id)); |
|
179 /* XXX: in theory should also update the OOB for both pages */ |
|
180 } |
|
181 |
|
182 static void n8x0_i2c_setup(struct n800_s *s) |
|
183 { |
|
184 qemu_irq tmp_irq = omap2_gpio_in_get(s->cpu->gpif, N8X0_TMP105_GPIO)[0]; |
|
185 |
|
186 /* Attach the CPU on one end of our I2C bus. */ |
|
187 s->i2c = omap_i2c_bus(s->cpu->i2c[0]); |
|
188 |
|
189 /* Attach a menelaus PM chip */ |
|
190 i2c_set_slave_address( |
|
191 twl92230_init(s->i2c, |
|
192 s->cpu->irq[0][OMAP_INT_24XX_SYS_NIRQ]), |
|
193 N8X0_MENELAUS_ADDR); |
|
194 |
|
195 /* Attach a TMP105 PM chip (A0 wired to ground) */ |
|
196 i2c_set_slave_address(tmp105_init(s->i2c, tmp_irq), N8X0_TMP105_ADDR); |
|
197 } |
|
198 |
|
199 /* Touchscreen and keypad controller */ |
|
200 static struct mouse_transform_info_s n800_pointercal = { |
|
201 .x = 800, |
|
202 .y = 480, |
|
203 .a = { 14560, -68, -3455208, -39, -9621, 35152972, 65536 }, |
|
204 }; |
|
205 |
|
206 static struct mouse_transform_info_s n810_pointercal = { |
|
207 .x = 800, |
|
208 .y = 480, |
|
209 .a = { 15041, 148, -4731056, 171, -10238, 35933380, 65536 }, |
|
210 }; |
|
211 |
|
212 #define RETU_KEYCODE 61 /* F3 */ |
|
213 |
|
214 static void n800_key_event(void *opaque, int keycode) |
|
215 { |
|
216 struct n800_s *s = (struct n800_s *) opaque; |
|
217 int code = s->keymap[keycode & 0x7f]; |
|
218 |
|
219 if (code == -1) { |
|
220 if ((keycode & 0x7f) == RETU_KEYCODE) |
|
221 retu_key_event(s->retu, !(keycode & 0x80)); |
|
222 return; |
|
223 } |
|
224 |
|
225 tsc210x_key_event(s->ts.chip, code, !(keycode & 0x80)); |
|
226 } |
|
227 |
|
228 static const int n800_keys[16] = { |
|
229 -1, |
|
230 72, /* Up */ |
|
231 63, /* Home (F5) */ |
|
232 -1, |
|
233 75, /* Left */ |
|
234 28, /* Enter */ |
|
235 77, /* Right */ |
|
236 -1, |
|
237 1, /* Cycle (ESC) */ |
|
238 80, /* Down */ |
|
239 62, /* Menu (F4) */ |
|
240 -1, |
|
241 66, /* Zoom- (F8) */ |
|
242 64, /* FullScreen (F6) */ |
|
243 65, /* Zoom+ (F7) */ |
|
244 -1, |
|
245 }; |
|
246 |
|
247 static void n800_tsc_kbd_setup(struct n800_s *s) |
|
248 { |
|
249 int i; |
|
250 |
|
251 /* XXX: are the three pins inverted inside the chip between the |
|
252 * tsc and the cpu (N4111)? */ |
|
253 qemu_irq penirq = 0; /* NC */ |
|
254 qemu_irq kbirq = omap2_gpio_in_get(s->cpu->gpif, N800_TSC_KP_IRQ_GPIO)[0]; |
|
255 qemu_irq dav = omap2_gpio_in_get(s->cpu->gpif, N800_TSC_TS_GPIO)[0]; |
|
256 |
|
257 s->ts.chip = tsc2301_init(penirq, kbirq, dav, 0); |
|
258 s->ts.opaque = s->ts.chip->opaque; |
|
259 s->ts.txrx = tsc210x_txrx; |
|
260 |
|
261 for (i = 0; i < 0x80; i ++) |
|
262 s->keymap[i] = -1; |
|
263 for (i = 0; i < 0x10; i ++) |
|
264 if (n800_keys[i] >= 0) |
|
265 s->keymap[n800_keys[i]] = i; |
|
266 |
|
267 gui_register_dev_key_callback(n800_key_event, s); |
|
268 |
|
269 tsc210x_set_transform(s->ts.chip, &n800_pointercal); |
|
270 } |
|
271 |
|
272 static void n810_tsc_setup(struct n800_s *s) |
|
273 { |
|
274 qemu_irq pintdav = omap2_gpio_in_get(s->cpu->gpif, N810_TSC_TS_GPIO)[0]; |
|
275 |
|
276 s->ts.opaque = tsc2005_init(pintdav); |
|
277 s->ts.txrx = tsc2005_txrx; |
|
278 |
|
279 tsc2005_set_transform(s->ts.opaque, &n810_pointercal); |
|
280 } |
|
281 |
|
282 /* N810 Keyboard controller */ |
|
283 static void n810_key_event(void *opaque, int keycode) |
|
284 { |
|
285 struct n800_s *s = (struct n800_s *) opaque; |
|
286 int code = s->keymap[keycode & 0x7f]; |
|
287 |
|
288 if (code == -1) { |
|
289 if ((keycode & 0x7f) == RETU_KEYCODE) |
|
290 retu_key_event(s->retu, !(keycode & 0x80)); |
|
291 return; |
|
292 } |
|
293 |
|
294 lm832x_key_event(s->kbd, code, !(keycode & 0x80)); |
|
295 } |
|
296 |
|
297 #define M 0 |
|
298 |
|
299 static int n810_keys[0x80] = { |
|
300 [0x01] = 16, /* Q */ |
|
301 [0x02] = 37, /* K */ |
|
302 [0x03] = 24, /* O */ |
|
303 [0x04] = 25, /* P */ |
|
304 [0x05] = 14, /* Backspace */ |
|
305 [0x06] = 30, /* A */ |
|
306 [0x07] = 31, /* S */ |
|
307 [0x08] = 32, /* D */ |
|
308 [0x09] = 33, /* F */ |
|
309 [0x0a] = 34, /* G */ |
|
310 [0x0b] = 35, /* H */ |
|
311 [0x0c] = 36, /* J */ |
|
312 |
|
313 [0x11] = 17, /* W */ |
|
314 [0x12] = 62, /* Menu (F4) */ |
|
315 [0x13] = 38, /* L */ |
|
316 [0x14] = 40, /* ' (Apostrophe) */ |
|
317 [0x16] = 44, /* Z */ |
|
318 [0x17] = 45, /* X */ |
|
319 [0x18] = 46, /* C */ |
|
320 [0x19] = 47, /* V */ |
|
321 [0x1a] = 48, /* B */ |
|
322 [0x1b] = 49, /* N */ |
|
323 [0x1c] = 42, /* Shift (Left shift) */ |
|
324 [0x1f] = 65, /* Zoom+ (F7) */ |
|
325 |
|
326 [0x21] = 18, /* E */ |
|
327 [0x22] = 39, /* ; (Semicolon) */ |
|
328 [0x23] = 12, /* - (Minus) */ |
|
329 [0x24] = 13, /* = (Equal) */ |
|
330 [0x2b] = 56, /* Fn (Left Alt) */ |
|
331 [0x2c] = 50, /* M */ |
|
332 [0x2f] = 66, /* Zoom- (F8) */ |
|
333 |
|
334 [0x31] = 19, /* R */ |
|
335 [0x32] = 29 | M, /* Right Ctrl */ |
|
336 [0x34] = 57, /* Space */ |
|
337 [0x35] = 51, /* , (Comma) */ |
|
338 [0x37] = 72 | M, /* Up */ |
|
339 [0x3c] = 82 | M, /* Compose (Insert) */ |
|
340 [0x3f] = 64, /* FullScreen (F6) */ |
|
341 |
|
342 [0x41] = 20, /* T */ |
|
343 [0x44] = 52, /* . (Dot) */ |
|
344 [0x46] = 77 | M, /* Right */ |
|
345 [0x4f] = 63, /* Home (F5) */ |
|
346 [0x51] = 21, /* Y */ |
|
347 [0x53] = 80 | M, /* Down */ |
|
348 [0x55] = 28, /* Enter */ |
|
349 [0x5f] = 1, /* Cycle (ESC) */ |
|
350 |
|
351 [0x61] = 22, /* U */ |
|
352 [0x64] = 75 | M, /* Left */ |
|
353 |
|
354 [0x71] = 23, /* I */ |
|
355 #if 0 |
|
356 [0x75] = 28 | M, /* KP Enter (KP Enter) */ |
|
357 #else |
|
358 [0x75] = 15, /* KP Enter (Tab) */ |
|
359 #endif |
|
360 }; |
|
361 |
|
362 #undef M |
|
363 |
|
364 static void n810_kbd_setup(struct n800_s *s) |
|
365 { |
|
366 qemu_irq kbd_irq = omap2_gpio_in_get(s->cpu->gpif, N810_KEYBOARD_GPIO)[0]; |
|
367 int i; |
|
368 |
|
369 for (i = 0; i < 0x80; i ++) |
|
370 s->keymap[i] = -1; |
|
371 for (i = 0; i < 0x80; i ++) |
|
372 if (n810_keys[i] > 0) |
|
373 s->keymap[n810_keys[i]] = i; |
|
374 |
|
375 gui_register_dev_key_callback(n810_key_event, s); |
|
376 |
|
377 /* Attach the LM8322 keyboard to the I2C bus, |
|
378 * should happen in n8x0_i2c_setup and s->kbd be initialised here. */ |
|
379 s->kbd = lm8323_init(s->i2c, kbd_irq); |
|
380 i2c_set_slave_address(s->kbd, N810_LM8323_ADDR); |
|
381 } |
|
382 |
|
383 /* LCD MIPI DBI-C controller (URAL) */ |
|
384 struct mipid_s { |
|
385 int resp[4]; |
|
386 int param[4]; |
|
387 int p; |
|
388 int pm; |
|
389 int cmd; |
|
390 |
|
391 int sleep; |
|
392 int booster; |
|
393 int te; |
|
394 int selfcheck; |
|
395 int partial; |
|
396 int normal; |
|
397 int vscr; |
|
398 int invert; |
|
399 int onoff; |
|
400 int gamma; |
|
401 uint32_t id; |
|
402 }; |
|
403 |
|
404 static void mipid_reset(struct mipid_s *s) |
|
405 { |
|
406 if (!s->sleep) |
|
407 fprintf(stderr, "%s: Display off\n", __FUNCTION__); |
|
408 |
|
409 s->pm = 0; |
|
410 s->cmd = 0; |
|
411 |
|
412 s->sleep = 1; |
|
413 s->booster = 0; |
|
414 s->selfcheck = |
|
415 (1 << 7) | /* Register loading OK. */ |
|
416 (1 << 5) | /* The chip is attached. */ |
|
417 (1 << 4); /* Display glass still in one piece. */ |
|
418 s->te = 0; |
|
419 s->partial = 0; |
|
420 s->normal = 1; |
|
421 s->vscr = 0; |
|
422 s->invert = 0; |
|
423 s->onoff = 1; |
|
424 s->gamma = 0; |
|
425 } |
|
426 |
|
427 static uint32_t mipid_txrx(void *opaque, uint32_t cmd, int len) |
|
428 { |
|
429 struct mipid_s *s = (struct mipid_s *) opaque; |
|
430 uint8_t ret; |
|
431 |
|
432 if (len > 9) |
|
433 cpu_abort(cpu_single_env, "%s: FIXME: bad SPI word width %i\n", |
|
434 __FUNCTION__, len); |
|
435 |
|
436 if (s->p >= ARRAY_SIZE(s->resp)) |
|
437 ret = 0; |
|
438 else |
|
439 ret = s->resp[s->p ++]; |
|
440 if (s->pm --> 0) |
|
441 s->param[s->pm] = cmd; |
|
442 else |
|
443 s->cmd = cmd; |
|
444 |
|
445 switch (s->cmd) { |
|
446 case 0x00: /* NOP */ |
|
447 break; |
|
448 |
|
449 case 0x01: /* SWRESET */ |
|
450 mipid_reset(s); |
|
451 break; |
|
452 |
|
453 case 0x02: /* BSTROFF */ |
|
454 s->booster = 0; |
|
455 break; |
|
456 case 0x03: /* BSTRON */ |
|
457 s->booster = 1; |
|
458 break; |
|
459 |
|
460 case 0x04: /* RDDID */ |
|
461 s->p = 0; |
|
462 s->resp[0] = (s->id >> 16) & 0xff; |
|
463 s->resp[1] = (s->id >> 8) & 0xff; |
|
464 s->resp[2] = (s->id >> 0) & 0xff; |
|
465 break; |
|
466 |
|
467 case 0x06: /* RD_RED */ |
|
468 case 0x07: /* RD_GREEN */ |
|
469 /* XXX the bootloader sometimes issues RD_BLUE meaning RDDID so |
|
470 * for the bootloader one needs to change this. */ |
|
471 case 0x08: /* RD_BLUE */ |
|
472 s->p = 0; |
|
473 /* TODO: return first pixel components */ |
|
474 s->resp[0] = 0x01; |
|
475 break; |
|
476 |
|
477 case 0x09: /* RDDST */ |
|
478 s->p = 0; |
|
479 s->resp[0] = s->booster << 7; |
|
480 s->resp[1] = (5 << 4) | (s->partial << 2) | |
|
481 (s->sleep << 1) | s->normal; |
|
482 s->resp[2] = (s->vscr << 7) | (s->invert << 5) | |
|
483 (s->onoff << 2) | (s->te << 1) | (s->gamma >> 2); |
|
484 s->resp[3] = s->gamma << 6; |
|
485 break; |
|
486 |
|
487 case 0x0a: /* RDDPM */ |
|
488 s->p = 0; |
|
489 s->resp[0] = (s->onoff << 2) | (s->normal << 3) | (s->sleep << 4) | |
|
490 (s->partial << 5) | (s->sleep << 6) | (s->booster << 7); |
|
491 break; |
|
492 case 0x0b: /* RDDMADCTR */ |
|
493 s->p = 0; |
|
494 s->resp[0] = 0; |
|
495 break; |
|
496 case 0x0c: /* RDDCOLMOD */ |
|
497 s->p = 0; |
|
498 s->resp[0] = 5; /* 65K colours */ |
|
499 break; |
|
500 case 0x0d: /* RDDIM */ |
|
501 s->p = 0; |
|
502 s->resp[0] = (s->invert << 5) | (s->vscr << 7) | s->gamma; |
|
503 break; |
|
504 case 0x0e: /* RDDSM */ |
|
505 s->p = 0; |
|
506 s->resp[0] = s->te << 7; |
|
507 break; |
|
508 case 0x0f: /* RDDSDR */ |
|
509 s->p = 0; |
|
510 s->resp[0] = s->selfcheck; |
|
511 break; |
|
512 |
|
513 case 0x10: /* SLPIN */ |
|
514 s->sleep = 1; |
|
515 break; |
|
516 case 0x11: /* SLPOUT */ |
|
517 s->sleep = 0; |
|
518 s->selfcheck ^= 1 << 6; /* POFF self-diagnosis Ok */ |
|
519 break; |
|
520 |
|
521 case 0x12: /* PTLON */ |
|
522 s->partial = 1; |
|
523 s->normal = 0; |
|
524 s->vscr = 0; |
|
525 break; |
|
526 case 0x13: /* NORON */ |
|
527 s->partial = 0; |
|
528 s->normal = 1; |
|
529 s->vscr = 0; |
|
530 break; |
|
531 |
|
532 case 0x20: /* INVOFF */ |
|
533 s->invert = 0; |
|
534 break; |
|
535 case 0x21: /* INVON */ |
|
536 s->invert = 1; |
|
537 break; |
|
538 |
|
539 case 0x22: /* APOFF */ |
|
540 case 0x23: /* APON */ |
|
541 goto bad_cmd; |
|
542 |
|
543 case 0x25: /* WRCNTR */ |
|
544 if (s->pm < 0) |
|
545 s->pm = 1; |
|
546 goto bad_cmd; |
|
547 |
|
548 case 0x26: /* GAMSET */ |
|
549 if (!s->pm) |
|
550 s->gamma = ffs(s->param[0] & 0xf) - 1; |
|
551 else if (s->pm < 0) |
|
552 s->pm = 1; |
|
553 break; |
|
554 |
|
555 case 0x28: /* DISPOFF */ |
|
556 s->onoff = 0; |
|
557 fprintf(stderr, "%s: Display off\n", __FUNCTION__); |
|
558 break; |
|
559 case 0x29: /* DISPON */ |
|
560 s->onoff = 1; |
|
561 fprintf(stderr, "%s: Display on\n", __FUNCTION__); |
|
562 break; |
|
563 |
|
564 case 0x2a: /* CASET */ |
|
565 case 0x2b: /* RASET */ |
|
566 case 0x2c: /* RAMWR */ |
|
567 case 0x2d: /* RGBSET */ |
|
568 case 0x2e: /* RAMRD */ |
|
569 case 0x30: /* PTLAR */ |
|
570 case 0x33: /* SCRLAR */ |
|
571 goto bad_cmd; |
|
572 |
|
573 case 0x34: /* TEOFF */ |
|
574 s->te = 0; |
|
575 break; |
|
576 case 0x35: /* TEON */ |
|
577 if (!s->pm) |
|
578 s->te = 1; |
|
579 else if (s->pm < 0) |
|
580 s->pm = 1; |
|
581 break; |
|
582 |
|
583 case 0x36: /* MADCTR */ |
|
584 goto bad_cmd; |
|
585 |
|
586 case 0x37: /* VSCSAD */ |
|
587 s->partial = 0; |
|
588 s->normal = 0; |
|
589 s->vscr = 1; |
|
590 break; |
|
591 |
|
592 case 0x38: /* IDMOFF */ |
|
593 case 0x39: /* IDMON */ |
|
594 case 0x3a: /* COLMOD */ |
|
595 goto bad_cmd; |
|
596 |
|
597 case 0xb0: /* CLKINT / DISCTL */ |
|
598 case 0xb1: /* CLKEXT */ |
|
599 if (s->pm < 0) |
|
600 s->pm = 2; |
|
601 break; |
|
602 |
|
603 case 0xb4: /* FRMSEL */ |
|
604 break; |
|
605 |
|
606 case 0xb5: /* FRM8SEL */ |
|
607 case 0xb6: /* TMPRNG / INIESC */ |
|
608 case 0xb7: /* TMPHIS / NOP2 */ |
|
609 case 0xb8: /* TMPREAD / MADCTL */ |
|
610 case 0xba: /* DISTCTR */ |
|
611 case 0xbb: /* EPVOL */ |
|
612 goto bad_cmd; |
|
613 |
|
614 case 0xbd: /* Unknown */ |
|
615 s->p = 0; |
|
616 s->resp[0] = 0; |
|
617 s->resp[1] = 1; |
|
618 break; |
|
619 |
|
620 case 0xc2: /* IFMOD */ |
|
621 if (s->pm < 0) |
|
622 s->pm = 2; |
|
623 break; |
|
624 |
|
625 case 0xc6: /* PWRCTL */ |
|
626 case 0xc7: /* PPWRCTL */ |
|
627 case 0xd0: /* EPWROUT */ |
|
628 case 0xd1: /* EPWRIN */ |
|
629 case 0xd4: /* RDEV */ |
|
630 case 0xd5: /* RDRR */ |
|
631 goto bad_cmd; |
|
632 |
|
633 case 0xda: /* RDID1 */ |
|
634 s->p = 0; |
|
635 s->resp[0] = (s->id >> 16) & 0xff; |
|
636 break; |
|
637 case 0xdb: /* RDID2 */ |
|
638 s->p = 0; |
|
639 s->resp[0] = (s->id >> 8) & 0xff; |
|
640 break; |
|
641 case 0xdc: /* RDID3 */ |
|
642 s->p = 0; |
|
643 s->resp[0] = (s->id >> 0) & 0xff; |
|
644 break; |
|
645 |
|
646 default: |
|
647 bad_cmd: |
|
648 fprintf(stderr, "%s: unknown command %02x\n", __FUNCTION__, s->cmd); |
|
649 break; |
|
650 } |
|
651 |
|
652 return ret; |
|
653 } |
|
654 |
|
655 static void *mipid_init(void) |
|
656 { |
|
657 struct mipid_s *s = (struct mipid_s *) qemu_mallocz(sizeof(*s)); |
|
658 |
|
659 s->id = 0x838f03; |
|
660 mipid_reset(s); |
|
661 |
|
662 return s; |
|
663 } |
|
664 |
|
665 static void n8x0_spi_setup(struct n800_s *s) |
|
666 { |
|
667 void *tsc = s->ts.opaque; |
|
668 void *mipid = mipid_init(); |
|
669 |
|
670 omap_mcspi_attach(s->cpu->mcspi[0], s->ts.txrx, tsc, 0); |
|
671 omap_mcspi_attach(s->cpu->mcspi[0], mipid_txrx, mipid, 1); |
|
672 } |
|
673 |
|
674 /* This task is normally performed by the bootloader. If we're loading |
|
675 * a kernel directly, we need to enable the Blizzard ourselves. */ |
|
676 static void n800_dss_init(struct rfbi_chip_s *chip) |
|
677 { |
|
678 uint8_t *fb_blank; |
|
679 |
|
680 chip->write(chip->opaque, 0, 0x2a); /* LCD Width register */ |
|
681 chip->write(chip->opaque, 1, 0x64); |
|
682 chip->write(chip->opaque, 0, 0x2c); /* LCD HNDP register */ |
|
683 chip->write(chip->opaque, 1, 0x1e); |
|
684 chip->write(chip->opaque, 0, 0x2e); /* LCD Height 0 register */ |
|
685 chip->write(chip->opaque, 1, 0xe0); |
|
686 chip->write(chip->opaque, 0, 0x30); /* LCD Height 1 register */ |
|
687 chip->write(chip->opaque, 1, 0x01); |
|
688 chip->write(chip->opaque, 0, 0x32); /* LCD VNDP register */ |
|
689 chip->write(chip->opaque, 1, 0x06); |
|
690 chip->write(chip->opaque, 0, 0x68); /* Display Mode register */ |
|
691 chip->write(chip->opaque, 1, 1); /* Enable bit */ |
|
692 |
|
693 chip->write(chip->opaque, 0, 0x6c); |
|
694 chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */ |
|
695 chip->write(chip->opaque, 1, 0x00); /* Input X Start Position */ |
|
696 chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */ |
|
697 chip->write(chip->opaque, 1, 0x00); /* Input Y Start Position */ |
|
698 chip->write(chip->opaque, 1, 0x1f); /* Input X End Position */ |
|
699 chip->write(chip->opaque, 1, 0x03); /* Input X End Position */ |
|
700 chip->write(chip->opaque, 1, 0xdf); /* Input Y End Position */ |
|
701 chip->write(chip->opaque, 1, 0x01); /* Input Y End Position */ |
|
702 chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */ |
|
703 chip->write(chip->opaque, 1, 0x00); /* Output X Start Position */ |
|
704 chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */ |
|
705 chip->write(chip->opaque, 1, 0x00); /* Output Y Start Position */ |
|
706 chip->write(chip->opaque, 1, 0x1f); /* Output X End Position */ |
|
707 chip->write(chip->opaque, 1, 0x03); /* Output X End Position */ |
|
708 chip->write(chip->opaque, 1, 0xdf); /* Output Y End Position */ |
|
709 chip->write(chip->opaque, 1, 0x01); /* Output Y End Position */ |
|
710 chip->write(chip->opaque, 1, 0x01); /* Input Data Format */ |
|
711 chip->write(chip->opaque, 1, 0x01); /* Data Source Select */ |
|
712 |
|
713 fb_blank = memset(qemu_malloc(800 * 480 * 2), 0xff, 800 * 480 * 2); |
|
714 /* Display Memory Data Port */ |
|
715 chip->block(chip->opaque, 1, fb_blank, 800 * 480 * 2, 800); |
|
716 free(fb_blank); |
|
717 } |
|
718 |
|
719 static void n8x0_dss_setup(struct n800_s *s, DisplayState *ds) |
|
720 { |
|
721 s->blizzard.opaque = s1d13745_init(0, ds); |
|
722 s->blizzard.block = s1d13745_write_block; |
|
723 s->blizzard.write = s1d13745_write; |
|
724 s->blizzard.read = s1d13745_read; |
|
725 |
|
726 omap_rfbi_attach(s->cpu->dss, 0, &s->blizzard); |
|
727 } |
|
728 |
|
729 static void n8x0_cbus_setup(struct n800_s *s) |
|
730 { |
|
731 qemu_irq dat_out = omap2_gpio_in_get(s->cpu->gpif, N8X0_CBUS_DAT_GPIO)[0]; |
|
732 qemu_irq retu_irq = omap2_gpio_in_get(s->cpu->gpif, N8X0_RETU_GPIO)[0]; |
|
733 qemu_irq tahvo_irq = omap2_gpio_in_get(s->cpu->gpif, N8X0_TAHVO_GPIO)[0]; |
|
734 |
|
735 struct cbus_s *cbus = cbus_init(dat_out); |
|
736 |
|
737 omap2_gpio_out_set(s->cpu->gpif, N8X0_CBUS_CLK_GPIO, cbus->clk); |
|
738 omap2_gpio_out_set(s->cpu->gpif, N8X0_CBUS_DAT_GPIO, cbus->dat); |
|
739 omap2_gpio_out_set(s->cpu->gpif, N8X0_CBUS_SEL_GPIO, cbus->sel); |
|
740 |
|
741 cbus_attach(cbus, s->retu = retu_init(retu_irq, 1)); |
|
742 cbus_attach(cbus, s->tahvo = tahvo_init(tahvo_irq, 1)); |
|
743 } |
|
744 |
|
745 static void n8x0_uart_setup(struct n800_s *s) |
|
746 { |
|
747 CharDriverState *radio = uart_hci_init( |
|
748 omap2_gpio_in_get(s->cpu->gpif, |
|
749 N8X0_BT_HOST_WKUP_GPIO)[0]); |
|
750 |
|
751 omap2_gpio_out_set(s->cpu->gpif, N8X0_BT_RESET_GPIO, |
|
752 csrhci_pins_get(radio)[csrhci_pin_reset]); |
|
753 omap2_gpio_out_set(s->cpu->gpif, N8X0_BT_WKUP_GPIO, |
|
754 csrhci_pins_get(radio)[csrhci_pin_wakeup]); |
|
755 |
|
756 omap_uart_attach(s->cpu->uart[BT_UART], radio); |
|
757 } |
|
758 |
|
759 static void n8x0_usb_power_cb(void *opaque, int line, int level) |
|
760 { |
|
761 struct n800_s *s = opaque; |
|
762 |
|
763 tusb6010_power(s->usb, level); |
|
764 } |
|
765 |
|
766 static void n8x0_usb_setup(struct n800_s *s) |
|
767 { |
|
768 qemu_irq tusb_irq = omap2_gpio_in_get(s->cpu->gpif, N8X0_TUSB_INT_GPIO)[0]; |
|
769 qemu_irq tusb_pwr = qemu_allocate_irqs(n8x0_usb_power_cb, s, 1)[0]; |
|
770 struct tusb_s *tusb = tusb6010_init(tusb_irq); |
|
771 |
|
772 /* Using the NOR interface */ |
|
773 omap_gpmc_attach(s->cpu->gpmc, N8X0_USB_ASYNC_CS, |
|
774 tusb6010_async_io(tusb), 0, 0, tusb); |
|
775 omap_gpmc_attach(s->cpu->gpmc, N8X0_USB_SYNC_CS, |
|
776 tusb6010_sync_io(tusb), 0, 0, tusb); |
|
777 |
|
778 s->usb = tusb; |
|
779 omap2_gpio_out_set(s->cpu->gpif, N8X0_TUSB_ENABLE_GPIO, tusb_pwr); |
|
780 } |
|
781 |
|
782 /* Setup done before the main bootloader starts by some early setup code |
|
783 * - used when we want to run the main bootloader in emulation. This |
|
784 * isn't documented. */ |
|
785 static uint32_t n800_pinout[104] = { |
|
786 0x080f00d8, 0x00d40808, 0x03080808, 0x080800d0, |
|
787 0x00dc0808, 0x0b0f0f00, 0x080800b4, 0x00c00808, |
|
788 0x08080808, 0x180800c4, 0x00b80000, 0x08080808, |
|
789 0x080800bc, 0x00cc0808, 0x08081818, 0x18180128, |
|
790 0x01241800, 0x18181818, 0x000000f0, 0x01300000, |
|
791 0x00001b0b, 0x1b0f0138, 0x00e0181b, 0x1b031b0b, |
|
792 0x180f0078, 0x00740018, 0x0f0f0f1a, 0x00000080, |
|
793 0x007c0000, 0x00000000, 0x00000088, 0x00840000, |
|
794 0x00000000, 0x00000094, 0x00980300, 0x0f180003, |
|
795 0x0000008c, 0x00900f0f, 0x0f0f1b00, 0x0f00009c, |
|
796 0x01140000, 0x1b1b0f18, 0x0818013c, 0x01400008, |
|
797 0x00001818, 0x000b0110, 0x010c1800, 0x0b030b0f, |
|
798 0x181800f4, 0x00f81818, 0x00000018, 0x000000fc, |
|
799 0x00401808, 0x00000000, 0x0f1b0030, 0x003c0008, |
|
800 0x00000000, 0x00000038, 0x00340000, 0x00000000, |
|
801 0x1a080070, 0x00641a1a, 0x08080808, 0x08080060, |
|
802 0x005c0808, 0x08080808, 0x08080058, 0x00540808, |
|
803 0x08080808, 0x0808006c, 0x00680808, 0x08080808, |
|
804 0x000000a8, 0x00b00000, 0x08080808, 0x000000a0, |
|
805 0x00a40000, 0x00000000, 0x08ff0050, 0x004c0808, |
|
806 0xffffffff, 0xffff0048, 0x0044ffff, 0xffffffff, |
|
807 0x000000ac, 0x01040800, 0x08080b0f, 0x18180100, |
|
808 0x01081818, 0x0b0b1808, 0x1a0300e4, 0x012c0b1a, |
|
809 0x02020018, 0x0b000134, 0x011c0800, 0x0b1b1b00, |
|
810 0x0f0000c8, 0x00ec181b, 0x000f0f02, 0x00180118, |
|
811 0x01200000, 0x0f0b1b1b, 0x0f0200e8, 0x0000020b, |
|
812 }; |
|
813 |
|
814 static void n800_setup_nolo_tags(void *sram_base) |
|
815 { |
|
816 int i; |
|
817 uint32_t *p = sram_base + 0x8000; |
|
818 uint32_t *v = sram_base + 0xa000; |
|
819 |
|
820 memset(p, 0, 0x3000); |
|
821 |
|
822 strcpy((void *) (p + 0), "QEMU N800"); |
|
823 |
|
824 strcpy((void *) (p + 8), "F5"); |
|
825 |
|
826 stl_raw(p + 10, 0x04f70000); |
|
827 strcpy((void *) (p + 9), "RX-34"); |
|
828 |
|
829 /* RAM size in MB? */ |
|
830 stl_raw(p + 12, 0x80); |
|
831 |
|
832 /* Pointer to the list of tags */ |
|
833 stl_raw(p + 13, OMAP2_SRAM_BASE + 0x9000); |
|
834 |
|
835 /* The NOLO tags start here */ |
|
836 p = sram_base + 0x9000; |
|
837 #define ADD_TAG(tag, len) \ |
|
838 stw_raw((uint16_t *) p + 0, tag); \ |
|
839 stw_raw((uint16_t *) p + 1, len); p ++; \ |
|
840 stl_raw(p ++, OMAP2_SRAM_BASE | (((void *) v - sram_base) & 0xffff)); |
|
841 |
|
842 /* OMAP STI console? Pin out settings? */ |
|
843 ADD_TAG(0x6e01, 414); |
|
844 for (i = 0; i < ARRAY_SIZE(n800_pinout); i ++) |
|
845 stl_raw(v ++, n800_pinout[i]); |
|
846 |
|
847 /* Kernel memsize? */ |
|
848 ADD_TAG(0x6e05, 1); |
|
849 stl_raw(v ++, 2); |
|
850 |
|
851 /* NOLO serial console */ |
|
852 ADD_TAG(0x6e02, 4); |
|
853 stl_raw(v ++, XLDR_LL_UART); /* UART number (1 - 3) */ |
|
854 |
|
855 #if 0 |
|
856 /* CBUS settings (Retu/AVilma) */ |
|
857 ADD_TAG(0x6e03, 6); |
|
858 stw_raw((uint16_t *) v + 0, 65); /* CBUS GPIO0 */ |
|
859 stw_raw((uint16_t *) v + 1, 66); /* CBUS GPIO1 */ |
|
860 stw_raw((uint16_t *) v + 2, 64); /* CBUS GPIO2 */ |
|
861 v += 2; |
|
862 #endif |
|
863 |
|
864 /* Nokia ASIC BB5 (Retu/Tahvo) */ |
|
865 ADD_TAG(0x6e0a, 4); |
|
866 stw_raw((uint16_t *) v + 0, 111); /* "Retu" interrupt GPIO */ |
|
867 stw_raw((uint16_t *) v + 1, 108); /* "Tahvo" interrupt GPIO */ |
|
868 v ++; |
|
869 |
|
870 /* LCD console? */ |
|
871 ADD_TAG(0x6e04, 4); |
|
872 stw_raw((uint16_t *) v + 0, 30); /* ??? */ |
|
873 stw_raw((uint16_t *) v + 1, 24); /* ??? */ |
|
874 v ++; |
|
875 |
|
876 #if 0 |
|
877 /* LCD settings */ |
|
878 ADD_TAG(0x6e06, 2); |
|
879 stw_raw((uint16_t *) (v ++), 15); /* ??? */ |
|
880 #endif |
|
881 |
|
882 /* I^2C (Menelaus) */ |
|
883 ADD_TAG(0x6e07, 4); |
|
884 stl_raw(v ++, 0x00720000); /* ??? */ |
|
885 |
|
886 /* Unknown */ |
|
887 ADD_TAG(0x6e0b, 6); |
|
888 stw_raw((uint16_t *) v + 0, 94); /* ??? */ |
|
889 stw_raw((uint16_t *) v + 1, 23); /* ??? */ |
|
890 stw_raw((uint16_t *) v + 2, 0); /* ??? */ |
|
891 v += 2; |
|
892 |
|
893 /* OMAP gpio switch info */ |
|
894 ADD_TAG(0x6e0c, 80); |
|
895 strcpy((void *) v, "bat_cover"); v += 3; |
|
896 stw_raw((uint16_t *) v + 0, 110); /* GPIO num ??? */ |
|
897 stw_raw((uint16_t *) v + 1, 1); /* GPIO num ??? */ |
|
898 v += 2; |
|
899 strcpy((void *) v, "cam_act"); v += 3; |
|
900 stw_raw((uint16_t *) v + 0, 95); /* GPIO num ??? */ |
|
901 stw_raw((uint16_t *) v + 1, 32); /* GPIO num ??? */ |
|
902 v += 2; |
|
903 strcpy((void *) v, "cam_turn"); v += 3; |
|
904 stw_raw((uint16_t *) v + 0, 12); /* GPIO num ??? */ |
|
905 stw_raw((uint16_t *) v + 1, 33); /* GPIO num ??? */ |
|
906 v += 2; |
|
907 strcpy((void *) v, "headphone"); v += 3; |
|
908 stw_raw((uint16_t *) v + 0, 107); /* GPIO num ??? */ |
|
909 stw_raw((uint16_t *) v + 1, 17); /* GPIO num ??? */ |
|
910 v += 2; |
|
911 |
|
912 /* Bluetooth */ |
|
913 ADD_TAG(0x6e0e, 12); |
|
914 stl_raw(v ++, 0x5c623d01); /* ??? */ |
|
915 stl_raw(v ++, 0x00000201); /* ??? */ |
|
916 stl_raw(v ++, 0x00000000); /* ??? */ |
|
917 |
|
918 /* CX3110x WLAN settings */ |
|
919 ADD_TAG(0x6e0f, 8); |
|
920 stl_raw(v ++, 0x00610025); /* ??? */ |
|
921 stl_raw(v ++, 0xffff0057); /* ??? */ |
|
922 |
|
923 /* MMC host settings */ |
|
924 ADD_TAG(0x6e10, 12); |
|
925 stl_raw(v ++, 0xffff000f); /* ??? */ |
|
926 stl_raw(v ++, 0xffffffff); /* ??? */ |
|
927 stl_raw(v ++, 0x00000060); /* ??? */ |
|
928 |
|
929 /* OneNAND chip select */ |
|
930 ADD_TAG(0x6e11, 10); |
|
931 stl_raw(v ++, 0x00000401); /* ??? */ |
|
932 stl_raw(v ++, 0x0002003a); /* ??? */ |
|
933 stl_raw(v ++, 0x00000002); /* ??? */ |
|
934 |
|
935 /* TEA5761 sensor settings */ |
|
936 ADD_TAG(0x6e12, 2); |
|
937 stl_raw(v ++, 93); /* GPIO num ??? */ |
|
938 |
|
939 #if 0 |
|
940 /* Unknown tag */ |
|
941 ADD_TAG(6e09, 0); |
|
942 |
|
943 /* Kernel UART / console */ |
|
944 ADD_TAG(6e12, 0); |
|
945 #endif |
|
946 |
|
947 /* End of the list */ |
|
948 stl_raw(p ++, 0x00000000); |
|
949 stl_raw(p ++, 0x00000000); |
|
950 } |
|
951 |
|
952 /* This task is normally performed by the bootloader. If we're loading |
|
953 * a kernel directly, we need to set up GPMC mappings ourselves. */ |
|
954 static void n800_gpmc_init(struct n800_s *s) |
|
955 { |
|
956 uint32_t config7 = |
|
957 (0xf << 8) | /* MASKADDRESS */ |
|
958 (1 << 6) | /* CSVALID */ |
|
959 (4 << 0); /* BASEADDRESS */ |
|
960 |
|
961 cpu_physical_memory_write(0x6800a078, /* GPMC_CONFIG7_0 */ |
|
962 (void *) &config7, sizeof(config7)); |
|
963 } |
|
964 |
|
965 /* Setup sequence done by the bootloader */ |
|
966 static void n8x0_boot_init(void *opaque) |
|
967 { |
|
968 struct n800_s *s = (struct n800_s *) opaque; |
|
969 uint32_t buf; |
|
970 |
|
971 /* PRCM setup */ |
|
972 #define omap_writel(addr, val) \ |
|
973 buf = (val); \ |
|
974 cpu_physical_memory_write(addr, (void *) &buf, sizeof(buf)) |
|
975 |
|
976 omap_writel(0x48008060, 0x41); /* PRCM_CLKSRC_CTRL */ |
|
977 omap_writel(0x48008070, 1); /* PRCM_CLKOUT_CTRL */ |
|
978 omap_writel(0x48008078, 0); /* PRCM_CLKEMUL_CTRL */ |
|
979 omap_writel(0x48008090, 0); /* PRCM_VOLTSETUP */ |
|
980 omap_writel(0x48008094, 0); /* PRCM_CLKSSETUP */ |
|
981 omap_writel(0x48008098, 0); /* PRCM_POLCTRL */ |
|
982 omap_writel(0x48008140, 2); /* CM_CLKSEL_MPU */ |
|
983 omap_writel(0x48008148, 0); /* CM_CLKSTCTRL_MPU */ |
|
984 omap_writel(0x48008158, 1); /* RM_RSTST_MPU */ |
|
985 omap_writel(0x480081c8, 0x15); /* PM_WKDEP_MPU */ |
|
986 omap_writel(0x480081d4, 0x1d4); /* PM_EVGENCTRL_MPU */ |
|
987 omap_writel(0x480081d8, 0); /* PM_EVEGENONTIM_MPU */ |
|
988 omap_writel(0x480081dc, 0); /* PM_EVEGENOFFTIM_MPU */ |
|
989 omap_writel(0x480081e0, 0xc); /* PM_PWSTCTRL_MPU */ |
|
990 omap_writel(0x48008200, 0x047e7ff7); /* CM_FCLKEN1_CORE */ |
|
991 omap_writel(0x48008204, 0x00000004); /* CM_FCLKEN2_CORE */ |
|
992 omap_writel(0x48008210, 0x047e7ff1); /* CM_ICLKEN1_CORE */ |
|
993 omap_writel(0x48008214, 0x00000004); /* CM_ICLKEN2_CORE */ |
|
994 omap_writel(0x4800821c, 0x00000000); /* CM_ICLKEN4_CORE */ |
|
995 omap_writel(0x48008230, 0); /* CM_AUTOIDLE1_CORE */ |
|
996 omap_writel(0x48008234, 0); /* CM_AUTOIDLE2_CORE */ |
|
997 omap_writel(0x48008238, 7); /* CM_AUTOIDLE3_CORE */ |
|
998 omap_writel(0x4800823c, 0); /* CM_AUTOIDLE4_CORE */ |
|
999 omap_writel(0x48008240, 0x04360626); /* CM_CLKSEL1_CORE */ |
|
1000 omap_writel(0x48008244, 0x00000014); /* CM_CLKSEL2_CORE */ |
|
1001 omap_writel(0x48008248, 0); /* CM_CLKSTCTRL_CORE */ |
|
1002 omap_writel(0x48008300, 0x00000000); /* CM_FCLKEN_GFX */ |
|
1003 omap_writel(0x48008310, 0x00000000); /* CM_ICLKEN_GFX */ |
|
1004 omap_writel(0x48008340, 0x00000001); /* CM_CLKSEL_GFX */ |
|
1005 omap_writel(0x48008400, 0x00000004); /* CM_FCLKEN_WKUP */ |
|
1006 omap_writel(0x48008410, 0x00000004); /* CM_ICLKEN_WKUP */ |
|
1007 omap_writel(0x48008440, 0x00000000); /* CM_CLKSEL_WKUP */ |
|
1008 omap_writel(0x48008500, 0x000000cf); /* CM_CLKEN_PLL */ |
|
1009 omap_writel(0x48008530, 0x0000000c); /* CM_AUTOIDLE_PLL */ |
|
1010 omap_writel(0x48008540, /* CM_CLKSEL1_PLL */ |
|
1011 (0x78 << 12) | (6 << 8)); |
|
1012 omap_writel(0x48008544, 2); /* CM_CLKSEL2_PLL */ |
|
1013 |
|
1014 /* GPMC setup */ |
|
1015 n800_gpmc_init(s); |
|
1016 |
|
1017 /* Video setup */ |
|
1018 n800_dss_init(&s->blizzard); |
|
1019 |
|
1020 /* CPU setup */ |
|
1021 s->cpu->env->regs[15] = s->cpu->env->boot_info->loader_start; |
|
1022 s->cpu->env->GE = 0x5; |
|
1023 |
|
1024 /* If the machine has a slided keyboard, open it */ |
|
1025 if (s->kbd) |
|
1026 qemu_irq_raise(omap2_gpio_in_get(s->cpu->gpif, N810_SLIDE_GPIO)[0]); |
|
1027 } |
|
1028 |
|
1029 #define OMAP_TAG_NOKIA_BT 0x4e01 |
|
1030 #define OMAP_TAG_WLAN_CX3110X 0x4e02 |
|
1031 #define OMAP_TAG_CBUS 0x4e03 |
|
1032 #define OMAP_TAG_EM_ASIC_BB5 0x4e04 |
|
1033 |
|
1034 static struct omap_gpiosw_info_s { |
|
1035 const char *name; |
|
1036 int line; |
|
1037 int type; |
|
1038 } n800_gpiosw_info[] = { |
|
1039 { |
|
1040 "bat_cover", N800_BAT_COVER_GPIO, |
|
1041 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED, |
|
1042 }, { |
|
1043 "cam_act", N800_CAM_ACT_GPIO, |
|
1044 OMAP_GPIOSW_TYPE_ACTIVITY, |
|
1045 }, { |
|
1046 "cam_turn", N800_CAM_TURN_GPIO, |
|
1047 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED, |
|
1048 }, { |
|
1049 "headphone", N8X0_HEADPHONE_GPIO, |
|
1050 OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED, |
|
1051 }, |
|
1052 { 0 } |
|
1053 }, n810_gpiosw_info[] = { |
|
1054 { |
|
1055 "gps_reset", N810_GPS_RESET_GPIO, |
|
1056 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT, |
|
1057 }, { |
|
1058 "gps_wakeup", N810_GPS_WAKEUP_GPIO, |
|
1059 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_OUTPUT, |
|
1060 }, { |
|
1061 "headphone", N8X0_HEADPHONE_GPIO, |
|
1062 OMAP_GPIOSW_TYPE_CONNECTION | OMAP_GPIOSW_INVERTED, |
|
1063 }, { |
|
1064 "kb_lock", N810_KB_LOCK_GPIO, |
|
1065 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED, |
|
1066 }, { |
|
1067 "sleepx_led", N810_SLEEPX_LED_GPIO, |
|
1068 OMAP_GPIOSW_TYPE_ACTIVITY | OMAP_GPIOSW_INVERTED | OMAP_GPIOSW_OUTPUT, |
|
1069 }, { |
|
1070 "slide", N810_SLIDE_GPIO, |
|
1071 OMAP_GPIOSW_TYPE_COVER | OMAP_GPIOSW_INVERTED, |
|
1072 }, |
|
1073 { 0 } |
|
1074 }; |
|
1075 |
|
1076 static struct omap_partition_info_s { |
|
1077 uint32_t offset; |
|
1078 uint32_t size; |
|
1079 int mask; |
|
1080 const char *name; |
|
1081 } n800_part_info[] = { |
|
1082 { 0x00000000, 0x00020000, 0x3, "bootloader" }, |
|
1083 { 0x00020000, 0x00060000, 0x0, "config" }, |
|
1084 { 0x00080000, 0x00200000, 0x0, "kernel" }, |
|
1085 { 0x00280000, 0x00200000, 0x3, "initfs" }, |
|
1086 { 0x00480000, 0x0fb80000, 0x3, "rootfs" }, |
|
1087 |
|
1088 { 0, 0, 0, 0 } |
|
1089 }, n810_part_info[] = { |
|
1090 { 0x00000000, 0x00020000, 0x3, "bootloader" }, |
|
1091 { 0x00020000, 0x00060000, 0x0, "config" }, |
|
1092 { 0x00080000, 0x00220000, 0x0, "kernel" }, |
|
1093 { 0x002a0000, 0x00400000, 0x0, "initfs" }, |
|
1094 { 0x006a0000, 0x0f960000, 0x0, "rootfs" }, |
|
1095 |
|
1096 { 0, 0, 0, 0 } |
|
1097 }; |
|
1098 |
|
1099 static bdaddr_t n8x0_bd_addr = {{ N8X0_BD_ADDR }}; |
|
1100 |
|
1101 static int n8x0_atag_setup(void *p, int model) |
|
1102 { |
|
1103 uint8_t *b; |
|
1104 uint16_t *w; |
|
1105 uint32_t *l; |
|
1106 struct omap_gpiosw_info_s *gpiosw; |
|
1107 struct omap_partition_info_s *partition; |
|
1108 const char *tag; |
|
1109 |
|
1110 w = p; |
|
1111 |
|
1112 stw_raw(w ++, OMAP_TAG_UART); /* u16 tag */ |
|
1113 stw_raw(w ++, 4); /* u16 len */ |
|
1114 stw_raw(w ++, (1 << 2) | (1 << 1) | (1 << 0)); /* uint enabled_uarts */ |
|
1115 w ++; |
|
1116 |
|
1117 #if 0 |
|
1118 stw_raw(w ++, OMAP_TAG_SERIAL_CONSOLE); /* u16 tag */ |
|
1119 stw_raw(w ++, 4); /* u16 len */ |
|
1120 stw_raw(w ++, XLDR_LL_UART + 1); /* u8 console_uart */ |
|
1121 stw_raw(w ++, 115200); /* u32 console_speed */ |
|
1122 #endif |
|
1123 |
|
1124 stw_raw(w ++, OMAP_TAG_LCD); /* u16 tag */ |
|
1125 stw_raw(w ++, 36); /* u16 len */ |
|
1126 strcpy((void *) w, "QEMU LCD panel"); /* char panel_name[16] */ |
|
1127 w += 8; |
|
1128 strcpy((void *) w, "blizzard"); /* char ctrl_name[16] */ |
|
1129 w += 8; |
|
1130 stw_raw(w ++, N810_BLIZZARD_RESET_GPIO); /* TODO: n800 s16 nreset_gpio */ |
|
1131 stw_raw(w ++, 24); /* u8 data_lines */ |
|
1132 |
|
1133 stw_raw(w ++, OMAP_TAG_CBUS); /* u16 tag */ |
|
1134 stw_raw(w ++, 8); /* u16 len */ |
|
1135 stw_raw(w ++, N8X0_CBUS_CLK_GPIO); /* s16 clk_gpio */ |
|
1136 stw_raw(w ++, N8X0_CBUS_DAT_GPIO); /* s16 dat_gpio */ |
|
1137 stw_raw(w ++, N8X0_CBUS_SEL_GPIO); /* s16 sel_gpio */ |
|
1138 w ++; |
|
1139 |
|
1140 stw_raw(w ++, OMAP_TAG_EM_ASIC_BB5); /* u16 tag */ |
|
1141 stw_raw(w ++, 4); /* u16 len */ |
|
1142 stw_raw(w ++, N8X0_RETU_GPIO); /* s16 retu_irq_gpio */ |
|
1143 stw_raw(w ++, N8X0_TAHVO_GPIO); /* s16 tahvo_irq_gpio */ |
|
1144 |
|
1145 gpiosw = (model == 810) ? n810_gpiosw_info : n800_gpiosw_info; |
|
1146 for (; gpiosw->name; gpiosw ++) { |
|
1147 stw_raw(w ++, OMAP_TAG_GPIO_SWITCH); /* u16 tag */ |
|
1148 stw_raw(w ++, 20); /* u16 len */ |
|
1149 strcpy((void *) w, gpiosw->name); /* char name[12] */ |
|
1150 w += 6; |
|
1151 stw_raw(w ++, gpiosw->line); /* u16 gpio */ |
|
1152 stw_raw(w ++, gpiosw->type); |
|
1153 stw_raw(w ++, 0); |
|
1154 stw_raw(w ++, 0); |
|
1155 } |
|
1156 |
|
1157 stw_raw(w ++, OMAP_TAG_NOKIA_BT); /* u16 tag */ |
|
1158 stw_raw(w ++, 12); /* u16 len */ |
|
1159 b = (void *) w; |
|
1160 stb_raw(b ++, 0x01); /* u8 chip_type (CSR) */ |
|
1161 stb_raw(b ++, N8X0_BT_WKUP_GPIO); /* u8 bt_wakeup_gpio */ |
|
1162 stb_raw(b ++, N8X0_BT_HOST_WKUP_GPIO); /* u8 host_wakeup_gpio */ |
|
1163 stb_raw(b ++, N8X0_BT_RESET_GPIO); /* u8 reset_gpio */ |
|
1164 stb_raw(b ++, BT_UART + 1); /* u8 bt_uart */ |
|
1165 memcpy(b, &n8x0_bd_addr, 6); /* u8 bd_addr[6] */ |
|
1166 b += 6; |
|
1167 stb_raw(b ++, 0x02); /* u8 bt_sysclk (38.4) */ |
|
1168 w = (void *) b; |
|
1169 |
|
1170 stw_raw(w ++, OMAP_TAG_WLAN_CX3110X); /* u16 tag */ |
|
1171 stw_raw(w ++, 8); /* u16 len */ |
|
1172 stw_raw(w ++, 0x25); /* u8 chip_type */ |
|
1173 stw_raw(w ++, N8X0_WLAN_PWR_GPIO); /* s16 power_gpio */ |
|
1174 stw_raw(w ++, N8X0_WLAN_IRQ_GPIO); /* s16 irq_gpio */ |
|
1175 stw_raw(w ++, -1); /* s16 spi_cs_gpio */ |
|
1176 |
|
1177 stw_raw(w ++, OMAP_TAG_MMC); /* u16 tag */ |
|
1178 stw_raw(w ++, 16); /* u16 len */ |
|
1179 if (model == 810) { |
|
1180 stw_raw(w ++, 0x23f); /* unsigned flags */ |
|
1181 stw_raw(w ++, -1); /* s16 power_pin */ |
|
1182 stw_raw(w ++, -1); /* s16 switch_pin */ |
|
1183 stw_raw(w ++, -1); /* s16 wp_pin */ |
|
1184 stw_raw(w ++, 0x240); /* unsigned flags */ |
|
1185 stw_raw(w ++, 0xc000); /* s16 power_pin */ |
|
1186 stw_raw(w ++, 0x0248); /* s16 switch_pin */ |
|
1187 stw_raw(w ++, 0xc000); /* s16 wp_pin */ |
|
1188 } else { |
|
1189 stw_raw(w ++, 0xf); /* unsigned flags */ |
|
1190 stw_raw(w ++, -1); /* s16 power_pin */ |
|
1191 stw_raw(w ++, -1); /* s16 switch_pin */ |
|
1192 stw_raw(w ++, -1); /* s16 wp_pin */ |
|
1193 stw_raw(w ++, 0); /* unsigned flags */ |
|
1194 stw_raw(w ++, 0); /* s16 power_pin */ |
|
1195 stw_raw(w ++, 0); /* s16 switch_pin */ |
|
1196 stw_raw(w ++, 0); /* s16 wp_pin */ |
|
1197 } |
|
1198 |
|
1199 stw_raw(w ++, OMAP_TAG_TEA5761); /* u16 tag */ |
|
1200 stw_raw(w ++, 4); /* u16 len */ |
|
1201 stw_raw(w ++, N8X0_TEA5761_CS_GPIO); /* u16 enable_gpio */ |
|
1202 w ++; |
|
1203 |
|
1204 partition = (model == 810) ? n810_part_info : n800_part_info; |
|
1205 for (; partition->name; partition ++) { |
|
1206 stw_raw(w ++, OMAP_TAG_PARTITION); /* u16 tag */ |
|
1207 stw_raw(w ++, 28); /* u16 len */ |
|
1208 strcpy((void *) w, partition->name); /* char name[16] */ |
|
1209 l = (void *) (w + 8); |
|
1210 stl_raw(l ++, partition->size); /* unsigned int size */ |
|
1211 stl_raw(l ++, partition->offset); /* unsigned int offset */ |
|
1212 stl_raw(l ++, partition->mask); /* unsigned int mask_flags */ |
|
1213 w = (void *) l; |
|
1214 } |
|
1215 |
|
1216 stw_raw(w ++, OMAP_TAG_BOOT_REASON); /* u16 tag */ |
|
1217 stw_raw(w ++, 12); /* u16 len */ |
|
1218 #if 0 |
|
1219 strcpy((void *) w, "por"); /* char reason_str[12] */ |
|
1220 strcpy((void *) w, "charger"); /* char reason_str[12] */ |
|
1221 strcpy((void *) w, "32wd_to"); /* char reason_str[12] */ |
|
1222 strcpy((void *) w, "sw_rst"); /* char reason_str[12] */ |
|
1223 strcpy((void *) w, "mbus"); /* char reason_str[12] */ |
|
1224 strcpy((void *) w, "unknown"); /* char reason_str[12] */ |
|
1225 strcpy((void *) w, "swdg_to"); /* char reason_str[12] */ |
|
1226 strcpy((void *) w, "sec_vio"); /* char reason_str[12] */ |
|
1227 strcpy((void *) w, "pwr_key"); /* char reason_str[12] */ |
|
1228 strcpy((void *) w, "rtc_alarm"); /* char reason_str[12] */ |
|
1229 #else |
|
1230 strcpy((void *) w, "pwr_key"); /* char reason_str[12] */ |
|
1231 #endif |
|
1232 w += 6; |
|
1233 |
|
1234 tag = (model == 810) ? "RX-44" : "RX-34"; |
|
1235 stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */ |
|
1236 stw_raw(w ++, 24); /* u16 len */ |
|
1237 strcpy((void *) w, "product"); /* char component[12] */ |
|
1238 w += 6; |
|
1239 strcpy((void *) w, tag); /* char version[12] */ |
|
1240 w += 6; |
|
1241 |
|
1242 stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */ |
|
1243 stw_raw(w ++, 24); /* u16 len */ |
|
1244 strcpy((void *) w, "hw-build"); /* char component[12] */ |
|
1245 w += 6; |
|
1246 strcpy((void *) w, "QEMU " QEMU_VERSION); /* char version[12] */ |
|
1247 w += 6; |
|
1248 |
|
1249 tag = (model == 810) ? "1.1.10-qemu" : "1.1.6-qemu"; |
|
1250 stw_raw(w ++, OMAP_TAG_VERSION_STR); /* u16 tag */ |
|
1251 stw_raw(w ++, 24); /* u16 len */ |
|
1252 strcpy((void *) w, "nolo"); /* char component[12] */ |
|
1253 w += 6; |
|
1254 strcpy((void *) w, tag); /* char version[12] */ |
|
1255 w += 6; |
|
1256 |
|
1257 return (void *) w - p; |
|
1258 } |
|
1259 |
|
1260 static int n800_atag_setup(struct arm_boot_info *info, void *p) |
|
1261 { |
|
1262 return n8x0_atag_setup(p, 800); |
|
1263 } |
|
1264 |
|
1265 static int n810_atag_setup(struct arm_boot_info *info, void *p) |
|
1266 { |
|
1267 return n8x0_atag_setup(p, 810); |
|
1268 } |
|
1269 |
|
1270 static void n8x0_init(ram_addr_t ram_size, const char *boot_device, |
|
1271 DisplayState *ds, const char *kernel_filename, |
|
1272 const char *kernel_cmdline, const char *initrd_filename, |
|
1273 const char *cpu_model, struct arm_boot_info *binfo, int model) |
|
1274 { |
|
1275 struct n800_s *s = (struct n800_s *) qemu_mallocz(sizeof(*s)); |
|
1276 int sdram_size = binfo->ram_size; |
|
1277 int onenandram_size = 0x00010000; |
|
1278 |
|
1279 if (ram_size < sdram_size + onenandram_size + OMAP242X_SRAM_SIZE) { |
|
1280 fprintf(stderr, "This architecture uses %i bytes of memory\n", |
|
1281 sdram_size + onenandram_size + OMAP242X_SRAM_SIZE); |
|
1282 exit(1); |
|
1283 } |
|
1284 |
|
1285 s->cpu = omap2420_mpu_init(sdram_size, NULL, cpu_model); |
|
1286 |
|
1287 /* Setup peripherals |
|
1288 * |
|
1289 * Believed external peripherals layout in the N810: |
|
1290 * (spi bus 1) |
|
1291 * tsc2005 |
|
1292 * lcd_mipid |
|
1293 * (spi bus 2) |
|
1294 * Conexant cx3110x (WLAN) |
|
1295 * optional: pc2400m (WiMAX) |
|
1296 * (i2c bus 0) |
|
1297 * TLV320AIC33 (audio codec) |
|
1298 * TCM825x (camera by Toshiba) |
|
1299 * lp5521 (clever LEDs) |
|
1300 * tsl2563 (light sensor, hwmon, model 7, rev. 0) |
|
1301 * lm8323 (keypad, manf 00, rev 04) |
|
1302 * (i2c bus 1) |
|
1303 * tmp105 (temperature sensor, hwmon) |
|
1304 * menelaus (pm) |
|
1305 * (somewhere on i2c - maybe N800-only) |
|
1306 * tea5761 (FM tuner) |
|
1307 * (serial 0) |
|
1308 * GPS |
|
1309 * (some serial port) |
|
1310 * csr41814 (Bluetooth) |
|
1311 */ |
|
1312 n8x0_gpio_setup(s); |
|
1313 n8x0_nand_setup(s); |
|
1314 n8x0_i2c_setup(s); |
|
1315 if (model == 800) |
|
1316 n800_tsc_kbd_setup(s); |
|
1317 else if (model == 810) { |
|
1318 n810_tsc_setup(s); |
|
1319 n810_kbd_setup(s); |
|
1320 } |
|
1321 n8x0_spi_setup(s); |
|
1322 n8x0_dss_setup(s, ds); |
|
1323 n8x0_cbus_setup(s); |
|
1324 n8x0_uart_setup(s); |
|
1325 if (usb_enabled) |
|
1326 n8x0_usb_setup(s); |
|
1327 |
|
1328 /* Setup initial (reset) machine state */ |
|
1329 |
|
1330 /* Start at the OneNAND bootloader. */ |
|
1331 s->cpu->env->regs[15] = 0; |
|
1332 |
|
1333 if (kernel_filename) { |
|
1334 /* Or at the linux loader. */ |
|
1335 binfo->kernel_filename = kernel_filename; |
|
1336 binfo->kernel_cmdline = kernel_cmdline; |
|
1337 binfo->initrd_filename = initrd_filename; |
|
1338 arm_load_kernel(s->cpu->env, binfo); |
|
1339 |
|
1340 qemu_register_reset(n8x0_boot_init, s); |
|
1341 n8x0_boot_init(s); |
|
1342 } |
|
1343 |
|
1344 if (option_rom[0] && (boot_device[0] == 'n' || !kernel_filename)) { |
|
1345 /* No, wait, better start at the ROM. */ |
|
1346 s->cpu->env->regs[15] = OMAP2_Q2_BASE + 0x400000; |
|
1347 |
|
1348 /* This is intended for loading the `secondary.bin' program from |
|
1349 * Nokia images (the NOLO bootloader). The entry point seems |
|
1350 * to be at OMAP2_Q2_BASE + 0x400000. |
|
1351 * |
|
1352 * The `2nd.bin' files contain some kind of earlier boot code and |
|
1353 * for them the entry point needs to be set to OMAP2_SRAM_BASE. |
|
1354 * |
|
1355 * The code above is for loading the `zImage' file from Nokia |
|
1356 * images. */ |
|
1357 /* FIXME: This is broken if it spans multiple RAM regions. */ |
|
1358 printf("%i bytes of image loaded\n", load_image(option_rom[0], |
|
1359 host_ram_addr(0x400000))); |
|
1360 |
|
1361 n800_setup_nolo_tags(host_ram_addr(sdram_size)); |
|
1362 } |
|
1363 |
|
1364 #if 0 |
|
1365 /* FIXME: We shouldn't really be doing this here. The LCD controller |
|
1366 will set the size once configured, so this just sets an initial |
|
1367 size until the guest activates the display. */ |
|
1368 /*dpy_resize(ds, 800, 480);*/ |
|
1369 DFG: TODO CHECK: FIXED? |
|
1370 #endif |
|
1371 } |
|
1372 |
|
1373 static struct arm_boot_info n800_binfo = { |
|
1374 .loader_start = OMAP2_Q2_BASE, |
|
1375 /* Actually two chips of 0x4000000 bytes each */ |
|
1376 .ram_size = 0x08000000, |
|
1377 .board_id = 0x4f7, |
|
1378 .atag_board = n800_atag_setup, |
|
1379 }; |
|
1380 |
|
1381 static struct arm_boot_info n810_binfo = { |
|
1382 .loader_start = OMAP2_Q2_BASE, |
|
1383 /* Actually two chips of 0x4000000 bytes each */ |
|
1384 .ram_size = 0x08000000, |
|
1385 /* 0x60c and 0x6bf (WiMAX Edition) have been assigned but are not |
|
1386 * used by some older versions of the bootloader and 5555 is used |
|
1387 * instead (including versions that shipped with many devices). */ |
|
1388 .board_id = 0x60c, |
|
1389 .atag_board = n810_atag_setup, |
|
1390 }; |
|
1391 |
|
1392 static void n800_init(ram_addr_t ram_size, int vga_ram_size, |
|
1393 const char *boot_device, DisplayState *ds, |
|
1394 const char *kernel_filename, const char *kernel_cmdline, |
|
1395 const char *initrd_filename, const char *cpu_model) |
|
1396 { |
|
1397 return n8x0_init(ram_size, boot_device, ds, |
|
1398 kernel_filename, kernel_cmdline, initrd_filename, |
|
1399 cpu_model, &n800_binfo, 800); |
|
1400 } |
|
1401 |
|
1402 static void n810_init(ram_addr_t ram_size, int vga_ram_size, |
|
1403 const char *boot_device, DisplayState *ds, |
|
1404 const char *kernel_filename, const char *kernel_cmdline, |
|
1405 const char *initrd_filename, const char *cpu_model) |
|
1406 { |
|
1407 return n8x0_init(ram_size, boot_device, ds, |
|
1408 kernel_filename, kernel_cmdline, initrd_filename, |
|
1409 cpu_model, &n810_binfo, 810); |
|
1410 } |
|
1411 |
|
1412 QEMUMachine n800_machine = { |
|
1413 .name = "n800", |
|
1414 .desc = "Nokia N800 tablet aka. RX-34 (OMAP2420)", |
|
1415 .init = n800_init, |
|
1416 .ram_require = (0x08000000 + 0x00010000 + OMAP242X_SRAM_SIZE) | |
|
1417 RAMSIZE_FIXED, |
|
1418 }; |
|
1419 |
|
1420 QEMUMachine n810_machine = { |
|
1421 .name = "n810", |
|
1422 .desc = "Nokia N810 tablet aka. RX-44 (OMAP2420)", |
|
1423 .init = n810_init, |
|
1424 .ram_require = (0x08000000 + 0x00010000 + OMAP242X_SRAM_SIZE) | |
|
1425 RAMSIZE_FIXED, |
|
1426 }; |