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1 /* |
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2 * Intel XScale PXA255/270 processor support. |
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3 * |
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4 * Copyright (c) 2006 Openedhand Ltd. |
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5 * Written by Andrzej Zaborowski <balrog@zabor.org> |
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6 * |
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7 * This code is licenced under the GNU GPL v2. |
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8 */ |
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9 #ifndef PXA_H |
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10 # define PXA_H "pxa.h" |
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11 |
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12 /* Interrupt numbers */ |
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13 # define PXA2XX_PIC_SSP3 0 |
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14 # define PXA2XX_PIC_USBH2 2 |
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15 # define PXA2XX_PIC_USBH1 3 |
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16 # define PXA2XX_PIC_KEYPAD 4 |
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17 # define PXA2XX_PIC_PWRI2C 6 |
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18 # define PXA25X_PIC_HWUART 7 |
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19 # define PXA27X_PIC_OST_4_11 7 |
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20 # define PXA2XX_PIC_GPIO_0 8 |
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21 # define PXA2XX_PIC_GPIO_1 9 |
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22 # define PXA2XX_PIC_GPIO_X 10 |
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23 # define PXA2XX_PIC_I2S 13 |
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24 # define PXA26X_PIC_ASSP 15 |
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25 # define PXA25X_PIC_NSSP 16 |
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26 # define PXA27X_PIC_SSP2 16 |
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27 # define PXA2XX_PIC_LCD 17 |
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28 # define PXA2XX_PIC_I2C 18 |
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29 # define PXA2XX_PIC_ICP 19 |
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30 # define PXA2XX_PIC_STUART 20 |
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31 # define PXA2XX_PIC_BTUART 21 |
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32 # define PXA2XX_PIC_FFUART 22 |
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33 # define PXA2XX_PIC_MMC 23 |
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34 # define PXA2XX_PIC_SSP 24 |
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35 # define PXA2XX_PIC_DMA 25 |
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36 # define PXA2XX_PIC_OST_0 26 |
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37 # define PXA2XX_PIC_RTC1HZ 30 |
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38 # define PXA2XX_PIC_RTCALARM 31 |
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39 |
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40 /* DMA requests */ |
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41 # define PXA2XX_RX_RQ_I2S 2 |
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42 # define PXA2XX_TX_RQ_I2S 3 |
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43 # define PXA2XX_RX_RQ_BTUART 4 |
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44 # define PXA2XX_TX_RQ_BTUART 5 |
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45 # define PXA2XX_RX_RQ_FFUART 6 |
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46 # define PXA2XX_TX_RQ_FFUART 7 |
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47 # define PXA2XX_RX_RQ_SSP1 13 |
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48 # define PXA2XX_TX_RQ_SSP1 14 |
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49 # define PXA2XX_RX_RQ_SSP2 15 |
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50 # define PXA2XX_TX_RQ_SSP2 16 |
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51 # define PXA2XX_RX_RQ_ICP 17 |
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52 # define PXA2XX_TX_RQ_ICP 18 |
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53 # define PXA2XX_RX_RQ_STUART 19 |
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54 # define PXA2XX_TX_RQ_STUART 20 |
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55 # define PXA2XX_RX_RQ_MMCI 21 |
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56 # define PXA2XX_TX_RQ_MMCI 22 |
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57 # define PXA2XX_USB_RQ(x) ((x) + 24) |
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58 # define PXA2XX_RX_RQ_SSP3 66 |
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59 # define PXA2XX_TX_RQ_SSP3 67 |
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60 |
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61 # define PXA2XX_SDRAM_BASE 0xa0000000 |
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62 # define PXA2XX_INTERNAL_BASE 0x5c000000 |
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63 # define PXA2XX_INTERNAL_SIZE 0x40000 |
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64 |
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65 /* pxa2xx_pic.c */ |
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66 qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env); |
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67 |
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68 /* pxa2xx_timer.c */ |
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69 void pxa25x_timer_init(target_phys_addr_t base, qemu_irq *irqs); |
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70 void pxa27x_timer_init(target_phys_addr_t base, qemu_irq *irqs, qemu_irq irq4); |
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71 |
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72 /* pxa2xx_gpio.c */ |
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73 struct pxa2xx_gpio_info_s; |
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74 struct pxa2xx_gpio_info_s *pxa2xx_gpio_init(target_phys_addr_t base, |
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75 CPUState *env, qemu_irq *pic, int lines); |
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76 qemu_irq *pxa2xx_gpio_in_get(struct pxa2xx_gpio_info_s *s); |
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77 void pxa2xx_gpio_out_set(struct pxa2xx_gpio_info_s *s, |
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78 int line, qemu_irq handler); |
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79 void pxa2xx_gpio_read_notifier(struct pxa2xx_gpio_info_s *s, qemu_irq handler); |
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80 |
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81 /* pxa2xx_dma.c */ |
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82 struct pxa2xx_dma_state_s; |
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83 struct pxa2xx_dma_state_s *pxa255_dma_init(target_phys_addr_t base, |
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84 qemu_irq irq); |
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85 struct pxa2xx_dma_state_s *pxa27x_dma_init(target_phys_addr_t base, |
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86 qemu_irq irq); |
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87 void pxa2xx_dma_request(struct pxa2xx_dma_state_s *s, int req_num, int on); |
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88 |
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89 /* pxa2xx_lcd.c */ |
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90 struct pxa2xx_lcdc_s; |
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91 struct pxa2xx_lcdc_s *pxa2xx_lcdc_init(target_phys_addr_t base, |
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92 qemu_irq irq, DisplayState *ds); |
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93 void pxa2xx_lcd_vsync_notifier(struct pxa2xx_lcdc_s *s, qemu_irq handler); |
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94 void pxa2xx_lcdc_oritentation(void *opaque, int angle); |
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95 |
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96 /* pxa2xx_mmci.c */ |
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97 struct pxa2xx_mmci_s; |
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98 struct pxa2xx_mmci_s *pxa2xx_mmci_init(target_phys_addr_t base, |
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99 BlockDriverState *bd, qemu_irq irq, void *dma); |
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100 void pxa2xx_mmci_handlers(struct pxa2xx_mmci_s *s, qemu_irq readonly, |
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101 qemu_irq coverswitch); |
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102 |
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103 /* pxa2xx_pcmcia.c */ |
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104 struct pxa2xx_pcmcia_s; |
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105 struct pxa2xx_pcmcia_s *pxa2xx_pcmcia_init(target_phys_addr_t base); |
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106 int pxa2xx_pcmcia_attach(void *opaque, struct pcmcia_card_s *card); |
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107 int pxa2xx_pcmcia_dettach(void *opaque); |
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108 void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq); |
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109 |
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110 /* pxa2xx_keypad.c */ |
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111 struct keymap { |
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112 int column; |
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113 int row; |
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114 }; |
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115 struct pxa2xx_keypad_s; |
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116 struct pxa2xx_keypad_s *pxa27x_keypad_init(target_phys_addr_t base, |
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117 qemu_irq irq); |
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118 void pxa27x_register_keypad(struct pxa2xx_keypad_s *kp, struct keymap *map, |
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119 int size); |
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120 |
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121 /* pxa2xx.c */ |
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122 struct pxa2xx_ssp_s; |
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123 void pxa2xx_ssp_attach(struct pxa2xx_ssp_s *port, |
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124 uint32_t (*readfn)(void *opaque), |
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125 void (*writefn)(void *opaque, uint32_t value), void *opaque); |
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126 |
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127 struct pxa2xx_i2c_s; |
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128 struct pxa2xx_i2c_s *pxa2xx_i2c_init(target_phys_addr_t base, |
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129 qemu_irq irq, uint32_t page_size); |
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130 i2c_bus *pxa2xx_i2c_bus(struct pxa2xx_i2c_s *s); |
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131 |
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132 struct pxa2xx_i2s_s; |
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133 struct pxa2xx_fir_s; |
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134 |
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135 struct pxa2xx_state_s { |
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136 CPUState *env; |
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137 qemu_irq *pic; |
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138 qemu_irq reset; |
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139 struct pxa2xx_dma_state_s *dma; |
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140 struct pxa2xx_gpio_info_s *gpio; |
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141 struct pxa2xx_lcdc_s *lcd; |
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142 struct pxa2xx_ssp_s **ssp; |
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143 struct pxa2xx_i2c_s *i2c[2]; |
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144 struct pxa2xx_mmci_s *mmc; |
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145 struct pxa2xx_pcmcia_s *pcmcia[2]; |
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146 struct pxa2xx_i2s_s *i2s; |
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147 struct pxa2xx_fir_s *fir; |
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148 struct pxa2xx_keypad_s *kp; |
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149 |
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150 /* Power management */ |
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151 target_phys_addr_t pm_base; |
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152 uint32_t pm_regs[0x40]; |
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153 |
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154 /* Clock management */ |
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155 target_phys_addr_t cm_base; |
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156 uint32_t cm_regs[4]; |
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157 uint32_t clkcfg; |
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158 |
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159 /* Memory management */ |
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160 target_phys_addr_t mm_base; |
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161 uint32_t mm_regs[0x1a]; |
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162 |
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163 /* Performance monitoring */ |
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164 uint32_t pmnc; |
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165 |
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166 /* Real-Time clock */ |
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167 target_phys_addr_t rtc_base; |
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168 uint32_t rttr; |
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169 uint32_t rtsr; |
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170 uint32_t rtar; |
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171 uint32_t rdar1; |
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172 uint32_t rdar2; |
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173 uint32_t ryar1; |
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174 uint32_t ryar2; |
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175 uint32_t swar1; |
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176 uint32_t swar2; |
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177 uint32_t piar; |
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178 uint32_t last_rcnr; |
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179 uint32_t last_rdcr; |
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180 uint32_t last_rycr; |
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181 uint32_t last_swcr; |
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182 uint32_t last_rtcpicr; |
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183 int64_t last_hz; |
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184 int64_t last_sw; |
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185 int64_t last_pi; |
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186 QEMUTimer *rtc_hz; |
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187 QEMUTimer *rtc_rdal1; |
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188 QEMUTimer *rtc_rdal2; |
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189 QEMUTimer *rtc_swal1; |
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190 QEMUTimer *rtc_swal2; |
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191 QEMUTimer *rtc_pi; |
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192 }; |
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193 |
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194 struct pxa2xx_i2s_s { |
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195 qemu_irq irq; |
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196 struct pxa2xx_dma_state_s *dma; |
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197 void (*data_req)(void *, int, int); |
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198 |
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199 uint32_t control[2]; |
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200 uint32_t status; |
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201 uint32_t mask; |
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202 uint32_t clk; |
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203 |
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204 int enable; |
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205 int rx_len; |
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206 int tx_len; |
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207 void (*codec_out)(void *, uint32_t); |
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208 uint32_t (*codec_in)(void *); |
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209 void *opaque; |
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210 |
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211 int fifo_len; |
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212 uint32_t fifo[16]; |
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213 }; |
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214 |
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215 # define PA_FMT "0x%08lx" |
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216 # define REG_FMT "0x" TARGET_FMT_plx |
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217 |
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218 struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size, DisplayState *ds, |
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219 const char *revision); |
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220 struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size, DisplayState *ds); |
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221 |
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222 /* usb-ohci.c */ |
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223 void usb_ohci_init_pxa(target_phys_addr_t base, int num_ports, int devfn, |
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224 qemu_irq irq); |
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225 |
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226 #endif /* PXA_H */ |