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1 /* |
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2 * Intel XScale PXA255/270 DMA controller. |
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3 * |
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4 * Copyright (c) 2006 Openedhand Ltd. |
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5 * Copyright (c) 2006 Thorsten Zitterell |
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6 * Written by Andrzej Zaborowski <balrog@zabor.org> |
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7 * |
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8 * This code is licenced under the GPL. |
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9 */ |
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10 |
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11 #include "hw.h" |
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12 #include "pxa.h" |
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13 |
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14 struct pxa2xx_dma_channel_s { |
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15 target_phys_addr_t descr; |
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16 target_phys_addr_t src; |
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17 target_phys_addr_t dest; |
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18 uint32_t cmd; |
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19 uint32_t state; |
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20 int request; |
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21 }; |
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22 |
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23 /* Allow the DMA to be used as a PIC. */ |
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24 typedef void (*pxa2xx_dma_handler_t)(void *opaque, int irq, int level); |
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25 |
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26 struct pxa2xx_dma_state_s { |
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27 pxa2xx_dma_handler_t handler; |
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28 qemu_irq irq; |
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29 |
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30 uint32_t stopintr; |
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31 uint32_t eorintr; |
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32 uint32_t rasintr; |
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33 uint32_t startintr; |
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34 uint32_t endintr; |
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35 |
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36 uint32_t align; |
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37 uint32_t pio; |
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38 |
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39 int channels; |
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40 struct pxa2xx_dma_channel_s *chan; |
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41 |
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42 uint8_t *req; |
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43 |
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44 /* Flag to avoid recursive DMA invocations. */ |
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45 int running; |
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46 }; |
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47 |
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48 #define PXA255_DMA_NUM_CHANNELS 16 |
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49 #define PXA27X_DMA_NUM_CHANNELS 32 |
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50 |
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51 #define PXA2XX_DMA_NUM_REQUESTS 75 |
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52 |
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53 #define DCSR0 0x0000 /* DMA Control / Status register for Channel 0 */ |
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54 #define DCSR31 0x007c /* DMA Control / Status register for Channel 31 */ |
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55 #define DALGN 0x00a0 /* DMA Alignment register */ |
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56 #define DPCSR 0x00a4 /* DMA Programmed I/O Control Status register */ |
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57 #define DRQSR0 0x00e0 /* DMA DREQ<0> Status register */ |
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58 #define DRQSR1 0x00e4 /* DMA DREQ<1> Status register */ |
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59 #define DRQSR2 0x00e8 /* DMA DREQ<2> Status register */ |
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60 #define DINT 0x00f0 /* DMA Interrupt register */ |
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61 #define DRCMR0 0x0100 /* Request to Channel Map register 0 */ |
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62 #define DRCMR63 0x01fc /* Request to Channel Map register 63 */ |
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63 #define D_CH0 0x0200 /* Channel 0 Descriptor start */ |
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64 #define DRCMR64 0x1100 /* Request to Channel Map register 64 */ |
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65 #define DRCMR74 0x1128 /* Request to Channel Map register 74 */ |
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66 |
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67 /* Per-channel register */ |
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68 #define DDADR 0x00 |
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69 #define DSADR 0x01 |
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70 #define DTADR 0x02 |
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71 #define DCMD 0x03 |
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72 |
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73 /* Bit-field masks */ |
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74 #define DRCMR_CHLNUM 0x1f |
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75 #define DRCMR_MAPVLD (1 << 7) |
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76 #define DDADR_STOP (1 << 0) |
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77 #define DDADR_BREN (1 << 1) |
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78 #define DCMD_LEN 0x1fff |
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79 #define DCMD_WIDTH(x) (1 << ((((x) >> 14) & 3) - 1)) |
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80 #define DCMD_SIZE(x) (4 << (((x) >> 16) & 3)) |
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81 #define DCMD_FLYBYT (1 << 19) |
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82 #define DCMD_FLYBYS (1 << 20) |
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83 #define DCMD_ENDIRQEN (1 << 21) |
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84 #define DCMD_STARTIRQEN (1 << 22) |
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85 #define DCMD_CMPEN (1 << 25) |
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86 #define DCMD_FLOWTRG (1 << 28) |
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87 #define DCMD_FLOWSRC (1 << 29) |
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88 #define DCMD_INCTRGADDR (1 << 30) |
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89 #define DCMD_INCSRCADDR (1 << 31) |
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90 #define DCSR_BUSERRINTR (1 << 0) |
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91 #define DCSR_STARTINTR (1 << 1) |
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92 #define DCSR_ENDINTR (1 << 2) |
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93 #define DCSR_STOPINTR (1 << 3) |
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94 #define DCSR_RASINTR (1 << 4) |
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95 #define DCSR_REQPEND (1 << 8) |
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96 #define DCSR_EORINT (1 << 9) |
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97 #define DCSR_CMPST (1 << 10) |
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98 #define DCSR_MASKRUN (1 << 22) |
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99 #define DCSR_RASIRQEN (1 << 23) |
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100 #define DCSR_CLRCMPST (1 << 24) |
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101 #define DCSR_SETCMPST (1 << 25) |
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102 #define DCSR_EORSTOPEN (1 << 26) |
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103 #define DCSR_EORJMPEN (1 << 27) |
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104 #define DCSR_EORIRQEN (1 << 28) |
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105 #define DCSR_STOPIRQEN (1 << 29) |
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106 #define DCSR_NODESCFETCH (1 << 30) |
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107 #define DCSR_RUN (1 << 31) |
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108 |
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109 static inline void pxa2xx_dma_update(struct pxa2xx_dma_state_s *s, int ch) |
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110 { |
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111 if (ch >= 0) { |
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112 if ((s->chan[ch].state & DCSR_STOPIRQEN) && |
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113 (s->chan[ch].state & DCSR_STOPINTR)) |
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114 s->stopintr |= 1 << ch; |
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115 else |
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116 s->stopintr &= ~(1 << ch); |
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117 |
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118 if ((s->chan[ch].state & DCSR_EORIRQEN) && |
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119 (s->chan[ch].state & DCSR_EORINT)) |
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120 s->eorintr |= 1 << ch; |
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121 else |
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122 s->eorintr &= ~(1 << ch); |
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123 |
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124 if ((s->chan[ch].state & DCSR_RASIRQEN) && |
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125 (s->chan[ch].state & DCSR_RASINTR)) |
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126 s->rasintr |= 1 << ch; |
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127 else |
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128 s->rasintr &= ~(1 << ch); |
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129 |
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130 if (s->chan[ch].state & DCSR_STARTINTR) |
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131 s->startintr |= 1 << ch; |
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132 else |
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133 s->startintr &= ~(1 << ch); |
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134 |
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135 if (s->chan[ch].state & DCSR_ENDINTR) |
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136 s->endintr |= 1 << ch; |
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137 else |
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138 s->endintr &= ~(1 << ch); |
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139 } |
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140 |
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141 if (s->stopintr | s->eorintr | s->rasintr | s->startintr | s->endintr) |
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142 qemu_irq_raise(s->irq); |
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143 else |
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144 qemu_irq_lower(s->irq); |
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145 } |
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146 |
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147 static inline void pxa2xx_dma_descriptor_fetch( |
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148 struct pxa2xx_dma_state_s *s, int ch) |
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149 { |
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150 uint32_t desc[4]; |
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151 target_phys_addr_t daddr = s->chan[ch].descr & ~0xf; |
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152 if ((s->chan[ch].descr & DDADR_BREN) && (s->chan[ch].state & DCSR_CMPST)) |
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153 daddr += 32; |
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154 |
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155 cpu_physical_memory_read(daddr, (uint8_t *) desc, 16); |
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156 s->chan[ch].descr = desc[DDADR]; |
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157 s->chan[ch].src = desc[DSADR]; |
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158 s->chan[ch].dest = desc[DTADR]; |
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159 s->chan[ch].cmd = desc[DCMD]; |
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160 |
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161 if (s->chan[ch].cmd & DCMD_FLOWSRC) |
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162 s->chan[ch].src &= ~3; |
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163 if (s->chan[ch].cmd & DCMD_FLOWTRG) |
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164 s->chan[ch].dest &= ~3; |
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165 |
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166 if (s->chan[ch].cmd & (DCMD_CMPEN | DCMD_FLYBYS | DCMD_FLYBYT)) |
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167 printf("%s: unsupported mode in channel %i\n", __FUNCTION__, ch); |
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168 |
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169 if (s->chan[ch].cmd & DCMD_STARTIRQEN) |
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170 s->chan[ch].state |= DCSR_STARTINTR; |
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171 } |
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172 |
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173 static void pxa2xx_dma_run(struct pxa2xx_dma_state_s *s) |
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174 { |
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175 int c, srcinc, destinc; |
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176 uint32_t n, size; |
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177 uint32_t width; |
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178 uint32_t length; |
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179 uint8_t buffer[32]; |
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180 struct pxa2xx_dma_channel_s *ch; |
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181 |
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182 if (s->running ++) |
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183 return; |
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184 |
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185 while (s->running) { |
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186 s->running = 1; |
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187 for (c = 0; c < s->channels; c ++) { |
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188 ch = &s->chan[c]; |
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189 |
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190 while ((ch->state & DCSR_RUN) && !(ch->state & DCSR_STOPINTR)) { |
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191 /* Test for pending requests */ |
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192 if ((ch->cmd & (DCMD_FLOWSRC | DCMD_FLOWTRG)) && !ch->request) |
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193 break; |
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194 |
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195 length = ch->cmd & DCMD_LEN; |
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196 size = DCMD_SIZE(ch->cmd); |
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197 width = DCMD_WIDTH(ch->cmd); |
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198 |
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199 srcinc = (ch->cmd & DCMD_INCSRCADDR) ? width : 0; |
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200 destinc = (ch->cmd & DCMD_INCTRGADDR) ? width : 0; |
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201 |
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202 while (length) { |
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203 size = MIN(length, size); |
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204 |
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205 for (n = 0; n < size; n += width) { |
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206 cpu_physical_memory_read(ch->src, buffer + n, width); |
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207 ch->src += srcinc; |
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208 } |
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209 |
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210 for (n = 0; n < size; n += width) { |
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211 cpu_physical_memory_write(ch->dest, buffer + n, width); |
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212 ch->dest += destinc; |
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213 } |
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214 |
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215 length -= size; |
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216 |
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217 if ((ch->cmd & (DCMD_FLOWSRC | DCMD_FLOWTRG)) && |
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218 !ch->request) { |
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219 ch->state |= DCSR_EORINT; |
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220 if (ch->state & DCSR_EORSTOPEN) |
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221 ch->state |= DCSR_STOPINTR; |
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222 if ((ch->state & DCSR_EORJMPEN) && |
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223 !(ch->state & DCSR_NODESCFETCH)) |
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224 pxa2xx_dma_descriptor_fetch(s, c); |
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225 break; |
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226 } |
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227 } |
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228 |
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229 ch->cmd = (ch->cmd & ~DCMD_LEN) | length; |
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230 |
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231 /* Is the transfer complete now? */ |
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232 if (!length) { |
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233 if (ch->cmd & DCMD_ENDIRQEN) |
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234 ch->state |= DCSR_ENDINTR; |
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235 |
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236 if ((ch->state & DCSR_NODESCFETCH) || |
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237 (ch->descr & DDADR_STOP) || |
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238 (ch->state & DCSR_EORSTOPEN)) { |
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239 ch->state |= DCSR_STOPINTR; |
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240 ch->state &= ~DCSR_RUN; |
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241 |
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242 break; |
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243 } |
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244 |
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245 ch->state |= DCSR_STOPINTR; |
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246 break; |
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247 } |
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248 } |
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249 } |
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250 |
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251 s->running --; |
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252 } |
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253 } |
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254 |
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255 static uint32_t pxa2xx_dma_read(void *opaque, target_phys_addr_t offset) |
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256 { |
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257 struct pxa2xx_dma_state_s *s = (struct pxa2xx_dma_state_s *) opaque; |
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258 unsigned int channel; |
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259 |
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260 switch (offset) { |
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261 case DRCMR64 ... DRCMR74: |
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262 offset -= DRCMR64 - DRCMR0 - (64 << 2); |
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263 /* Fall through */ |
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264 case DRCMR0 ... DRCMR63: |
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265 channel = (offset - DRCMR0) >> 2; |
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266 return s->req[channel]; |
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267 |
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268 case DRQSR0: |
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269 case DRQSR1: |
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270 case DRQSR2: |
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271 return 0; |
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272 |
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273 case DCSR0 ... DCSR31: |
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274 channel = offset >> 2; |
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275 if (s->chan[channel].request) |
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276 return s->chan[channel].state | DCSR_REQPEND; |
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277 return s->chan[channel].state; |
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278 |
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279 case DINT: |
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280 return s->stopintr | s->eorintr | s->rasintr | |
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281 s->startintr | s->endintr; |
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282 |
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283 case DALGN: |
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284 return s->align; |
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285 |
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286 case DPCSR: |
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287 return s->pio; |
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288 } |
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289 |
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290 if (offset >= D_CH0 && offset < D_CH0 + (s->channels << 4)) { |
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291 channel = (offset - D_CH0) >> 4; |
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292 switch ((offset & 0x0f) >> 2) { |
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293 case DDADR: |
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294 return s->chan[channel].descr; |
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295 case DSADR: |
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296 return s->chan[channel].src; |
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297 case DTADR: |
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298 return s->chan[channel].dest; |
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299 case DCMD: |
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300 return s->chan[channel].cmd; |
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301 } |
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302 } |
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303 |
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304 cpu_abort(cpu_single_env, |
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305 "%s: Bad offset 0x" TARGET_FMT_plx "\n", __FUNCTION__, offset); |
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306 return 7; |
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307 } |
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308 |
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309 static void pxa2xx_dma_write(void *opaque, |
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310 target_phys_addr_t offset, uint32_t value) |
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311 { |
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312 struct pxa2xx_dma_state_s *s = (struct pxa2xx_dma_state_s *) opaque; |
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313 unsigned int channel; |
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314 |
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315 switch (offset) { |
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316 case DRCMR64 ... DRCMR74: |
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317 offset -= DRCMR64 - DRCMR0 - (64 << 2); |
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318 /* Fall through */ |
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319 case DRCMR0 ... DRCMR63: |
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320 channel = (offset - DRCMR0) >> 2; |
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321 |
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322 if (value & DRCMR_MAPVLD) |
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323 if ((value & DRCMR_CHLNUM) > s->channels) |
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324 cpu_abort(cpu_single_env, "%s: Bad DMA channel %i\n", |
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325 __FUNCTION__, value & DRCMR_CHLNUM); |
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326 |
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327 s->req[channel] = value; |
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328 break; |
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329 |
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330 case DRQSR0: |
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331 case DRQSR1: |
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332 case DRQSR2: |
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333 /* Nothing to do */ |
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334 break; |
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335 |
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336 case DCSR0 ... DCSR31: |
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337 channel = offset >> 2; |
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338 s->chan[channel].state &= 0x0000071f & ~(value & |
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339 (DCSR_EORINT | DCSR_ENDINTR | |
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340 DCSR_STARTINTR | DCSR_BUSERRINTR)); |
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341 s->chan[channel].state |= value & 0xfc800000; |
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342 |
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343 if (s->chan[channel].state & DCSR_STOPIRQEN) |
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344 s->chan[channel].state &= ~DCSR_STOPINTR; |
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345 |
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346 if (value & DCSR_NODESCFETCH) { |
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347 /* No-descriptor-fetch mode */ |
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348 if (value & DCSR_RUN) { |
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349 s->chan[channel].state &= ~DCSR_STOPINTR; |
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350 pxa2xx_dma_run(s); |
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351 } |
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352 } else { |
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353 /* Descriptor-fetch mode */ |
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354 if (value & DCSR_RUN) { |
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355 s->chan[channel].state &= ~DCSR_STOPINTR; |
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356 pxa2xx_dma_descriptor_fetch(s, channel); |
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357 pxa2xx_dma_run(s); |
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358 } |
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359 } |
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360 |
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361 /* Shouldn't matter as our DMA is synchronous. */ |
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362 if (!(value & (DCSR_RUN | DCSR_MASKRUN))) |
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363 s->chan[channel].state |= DCSR_STOPINTR; |
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364 |
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365 if (value & DCSR_CLRCMPST) |
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366 s->chan[channel].state &= ~DCSR_CMPST; |
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367 if (value & DCSR_SETCMPST) |
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368 s->chan[channel].state |= DCSR_CMPST; |
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369 |
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370 pxa2xx_dma_update(s, channel); |
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371 break; |
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372 |
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373 case DALGN: |
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374 s->align = value; |
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375 break; |
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376 |
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377 case DPCSR: |
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378 s->pio = value & 0x80000001; |
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379 break; |
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380 |
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381 default: |
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382 if (offset >= D_CH0 && offset < D_CH0 + (s->channels << 4)) { |
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383 channel = (offset - D_CH0) >> 4; |
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384 switch ((offset & 0x0f) >> 2) { |
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385 case DDADR: |
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386 s->chan[channel].descr = value; |
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387 break; |
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388 case DSADR: |
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389 s->chan[channel].src = value; |
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390 break; |
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391 case DTADR: |
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392 s->chan[channel].dest = value; |
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393 break; |
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394 case DCMD: |
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395 s->chan[channel].cmd = value; |
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396 break; |
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397 default: |
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398 goto fail; |
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399 } |
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400 |
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401 break; |
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402 } |
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403 fail: |
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404 cpu_abort(cpu_single_env, "%s: Bad offset " TARGET_FMT_plx "\n", |
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405 __FUNCTION__, offset); |
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406 } |
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407 } |
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408 |
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409 static uint32_t pxa2xx_dma_readbad(void *opaque, target_phys_addr_t offset) |
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410 { |
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411 cpu_abort(cpu_single_env, "%s: Bad access width\n", __FUNCTION__); |
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412 return 5; |
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413 } |
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414 |
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415 static void pxa2xx_dma_writebad(void *opaque, |
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416 target_phys_addr_t offset, uint32_t value) |
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417 { |
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418 cpu_abort(cpu_single_env, "%s: Bad access width\n", __FUNCTION__); |
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419 } |
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420 |
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421 static CPUReadMemoryFunc *pxa2xx_dma_readfn[] = { |
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422 pxa2xx_dma_readbad, |
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423 pxa2xx_dma_readbad, |
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424 pxa2xx_dma_read |
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425 }; |
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426 |
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427 static CPUWriteMemoryFunc *pxa2xx_dma_writefn[] = { |
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428 pxa2xx_dma_writebad, |
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429 pxa2xx_dma_writebad, |
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430 pxa2xx_dma_write |
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431 }; |
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432 |
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433 static void pxa2xx_dma_save(QEMUFile *f, void *opaque) |
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434 { |
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435 struct pxa2xx_dma_state_s *s = (struct pxa2xx_dma_state_s *) opaque; |
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436 int i; |
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437 |
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438 qemu_put_be32(f, s->channels); |
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439 |
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440 qemu_put_be32s(f, &s->stopintr); |
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441 qemu_put_be32s(f, &s->eorintr); |
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442 qemu_put_be32s(f, &s->rasintr); |
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443 qemu_put_be32s(f, &s->startintr); |
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444 qemu_put_be32s(f, &s->endintr); |
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445 qemu_put_be32s(f, &s->align); |
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446 qemu_put_be32s(f, &s->pio); |
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447 |
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448 qemu_put_buffer(f, s->req, PXA2XX_DMA_NUM_REQUESTS); |
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449 for (i = 0; i < s->channels; i ++) { |
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450 qemu_put_betl(f, s->chan[i].descr); |
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451 qemu_put_betl(f, s->chan[i].src); |
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452 qemu_put_betl(f, s->chan[i].dest); |
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453 qemu_put_be32s(f, &s->chan[i].cmd); |
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454 qemu_put_be32s(f, &s->chan[i].state); |
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455 qemu_put_be32(f, s->chan[i].request); |
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456 }; |
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457 } |
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458 |
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459 static int pxa2xx_dma_load(QEMUFile *f, void *opaque, int version_id) |
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460 { |
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461 struct pxa2xx_dma_state_s *s = (struct pxa2xx_dma_state_s *) opaque; |
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462 int i; |
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463 |
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464 if (qemu_get_be32(f) != s->channels) |
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465 return -EINVAL; |
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466 |
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467 qemu_get_be32s(f, &s->stopintr); |
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468 qemu_get_be32s(f, &s->eorintr); |
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469 qemu_get_be32s(f, &s->rasintr); |
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470 qemu_get_be32s(f, &s->startintr); |
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471 qemu_get_be32s(f, &s->endintr); |
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472 qemu_get_be32s(f, &s->align); |
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473 qemu_get_be32s(f, &s->pio); |
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474 |
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475 qemu_get_buffer(f, s->req, PXA2XX_DMA_NUM_REQUESTS); |
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476 for (i = 0; i < s->channels; i ++) { |
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477 s->chan[i].descr = qemu_get_betl(f); |
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478 s->chan[i].src = qemu_get_betl(f); |
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479 s->chan[i].dest = qemu_get_betl(f); |
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480 qemu_get_be32s(f, &s->chan[i].cmd); |
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481 qemu_get_be32s(f, &s->chan[i].state); |
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482 s->chan[i].request = qemu_get_be32(f); |
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483 }; |
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484 |
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485 return 0; |
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486 } |
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487 |
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488 static struct pxa2xx_dma_state_s *pxa2xx_dma_init(target_phys_addr_t base, |
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489 qemu_irq irq, int channels) |
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490 { |
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491 int i, iomemtype; |
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492 struct pxa2xx_dma_state_s *s; |
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493 s = (struct pxa2xx_dma_state_s *) |
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494 qemu_mallocz(sizeof(struct pxa2xx_dma_state_s)); |
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495 |
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496 s->channels = channels; |
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497 s->chan = qemu_mallocz(sizeof(struct pxa2xx_dma_channel_s) * s->channels); |
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498 s->irq = irq; |
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499 s->handler = (pxa2xx_dma_handler_t) pxa2xx_dma_request; |
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500 s->req = qemu_mallocz(sizeof(uint8_t) * PXA2XX_DMA_NUM_REQUESTS); |
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501 |
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502 memset(s->chan, 0, sizeof(struct pxa2xx_dma_channel_s) * s->channels); |
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503 for (i = 0; i < s->channels; i ++) |
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504 s->chan[i].state = DCSR_STOPINTR; |
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505 |
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506 memset(s->req, 0, sizeof(uint8_t) * PXA2XX_DMA_NUM_REQUESTS); |
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507 |
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508 iomemtype = cpu_register_io_memory(0, pxa2xx_dma_readfn, |
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509 pxa2xx_dma_writefn, s); |
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510 cpu_register_physical_memory(base, 0x00010000, iomemtype); |
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511 |
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512 register_savevm("pxa2xx_dma", 0, 0, pxa2xx_dma_save, pxa2xx_dma_load, s); |
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513 |
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514 return s; |
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515 } |
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516 |
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517 struct pxa2xx_dma_state_s *pxa27x_dma_init(target_phys_addr_t base, |
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518 qemu_irq irq) |
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519 { |
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520 return pxa2xx_dma_init(base, irq, PXA27X_DMA_NUM_CHANNELS); |
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521 } |
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522 |
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523 struct pxa2xx_dma_state_s *pxa255_dma_init(target_phys_addr_t base, |
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524 qemu_irq irq) |
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525 { |
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526 return pxa2xx_dma_init(base, irq, PXA255_DMA_NUM_CHANNELS); |
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527 } |
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528 |
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529 void pxa2xx_dma_request(struct pxa2xx_dma_state_s *s, int req_num, int on) |
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530 { |
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531 int ch; |
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532 if (req_num < 0 || req_num >= PXA2XX_DMA_NUM_REQUESTS) |
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533 cpu_abort(cpu_single_env, |
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534 "%s: Bad DMA request %i\n", __FUNCTION__, req_num); |
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535 |
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536 if (!(s->req[req_num] & DRCMR_MAPVLD)) |
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537 return; |
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538 ch = s->req[req_num] & DRCMR_CHLNUM; |
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539 |
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540 if (!s->chan[ch].request && on) |
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541 s->chan[ch].state |= DCSR_RASINTR; |
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542 else |
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543 s->chan[ch].state &= ~DCSR_RASINTR; |
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544 if (s->chan[ch].request && !on) |
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545 s->chan[ch].state |= DCSR_EORINT; |
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546 |
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547 s->chan[ch].request = on; |
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548 if (on) { |
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549 pxa2xx_dma_run(s); |
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550 pxa2xx_dma_update(s, ch); |
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551 } |
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552 } |