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1 /* |
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2 * QEMU TCX Frame buffer |
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3 * |
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4 * Copyright (c) 2003-2005 Fabrice Bellard |
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5 * |
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6 * Permission is hereby granted, free of charge, to any person obtaining a copy |
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7 * of this software and associated documentation files (the "Software"), to deal |
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8 * in the Software without restriction, including without limitation the rights |
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9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
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10 * copies of the Software, and to permit persons to whom the Software is |
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11 * furnished to do so, subject to the following conditions: |
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12 * |
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13 * The above copyright notice and this permission notice shall be included in |
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14 * all copies or substantial portions of the Software. |
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15 * |
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16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
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22 * THE SOFTWARE. |
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23 */ |
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24 #include "hw.h" |
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25 #include "sun4m.h" |
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26 #include "console.h" |
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27 #include "pixel_ops.h" |
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28 |
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29 #define MAXX 1024 |
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30 #define MAXY 768 |
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31 #define TCX_DAC_NREGS 16 |
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32 #define TCX_THC_NREGS_8 0x081c |
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33 #define TCX_THC_NREGS_24 0x1000 |
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34 #define TCX_TEC_NREGS 0x1000 |
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35 |
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36 typedef struct TCXState { |
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37 target_phys_addr_t addr; |
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38 DisplayState *ds; |
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39 QEMUConsole *console; |
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40 uint8_t *vram; |
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41 uint32_t *vram24, *cplane; |
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42 ram_addr_t vram_offset, vram24_offset, cplane_offset; |
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43 uint16_t width, height, depth; |
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44 uint8_t r[256], g[256], b[256]; |
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45 uint32_t palette[256]; |
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46 uint8_t dac_index, dac_state; |
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47 } TCXState; |
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48 |
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49 static void tcx_screen_dump(void *opaque, const char *filename); |
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50 static void tcx24_screen_dump(void *opaque, const char *filename); |
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51 static void tcx_invalidate_display(void *opaque); |
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52 static void tcx24_invalidate_display(void *opaque); |
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53 |
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54 static void update_palette_entries(TCXState *s, int start, int end) |
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55 { |
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56 int i; |
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57 for(i = start; i < end; i++) { |
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58 switch(ds_get_bits_per_pixel(s->ds)) { |
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59 default: |
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60 case 8: |
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61 s->palette[i] = rgb_to_pixel8(s->r[i], s->g[i], s->b[i]); |
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62 break; |
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63 case 15: |
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64 if (s->ds->bgr) |
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65 s->palette[i] = rgb_to_pixel15bgr(s->r[i], s->g[i], s->b[i]); |
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66 else |
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67 s->palette[i] = rgb_to_pixel15(s->r[i], s->g[i], s->b[i]); |
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68 break; |
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69 case 16: |
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70 if (s->ds->bgr) |
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71 s->palette[i] = rgb_to_pixel16bgr(s->r[i], s->g[i], s->b[i]); |
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72 else |
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73 s->palette[i] = rgb_to_pixel16(s->r[i], s->g[i], s->b[i]); |
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74 break; |
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75 case 32: |
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76 if (s->ds->bgr) |
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77 s->palette[i] = rgb_to_pixel32bgr(s->r[i], s->g[i], s->b[i]); |
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78 else |
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79 s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]); |
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80 break; |
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81 } |
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82 } |
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83 if (s->depth == 24) |
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84 tcx24_invalidate_display(s); |
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85 else |
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86 tcx_invalidate_display(s); |
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87 } |
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88 |
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89 static void tcx_draw_line32(TCXState *s1, uint8_t *d, |
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90 const uint8_t *s, int width) |
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91 { |
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92 int x; |
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93 uint8_t val; |
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94 uint32_t *p = (uint32_t *)d; |
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95 |
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96 for(x = 0; x < width; x++) { |
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97 val = *s++; |
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98 *p++ = s1->palette[val]; |
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99 } |
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100 } |
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101 |
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102 static void tcx_draw_line16(TCXState *s1, uint8_t *d, |
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103 const uint8_t *s, int width) |
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104 { |
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105 int x; |
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106 uint8_t val; |
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107 uint16_t *p = (uint16_t *)d; |
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108 |
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109 for(x = 0; x < width; x++) { |
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110 val = *s++; |
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111 *p++ = s1->palette[val]; |
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112 } |
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113 } |
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114 |
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115 static void tcx_draw_line8(TCXState *s1, uint8_t *d, |
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116 const uint8_t *s, int width) |
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117 { |
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118 int x; |
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119 uint8_t val; |
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120 |
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121 for(x = 0; x < width; x++) { |
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122 val = *s++; |
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123 *d++ = s1->palette[val]; |
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124 } |
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125 } |
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126 |
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127 /* |
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128 XXX Could be much more optimal: |
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129 * detect if line/page/whole screen is in 24 bit mode |
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130 * if destination is also BGR, use memcpy |
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131 */ |
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132 static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d, |
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133 const uint8_t *s, int width, |
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134 const uint32_t *cplane, |
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135 const uint32_t *s24) |
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136 { |
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137 int x, bgr, r, g, b; |
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138 uint8_t val, *p8; |
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139 uint32_t *p = (uint32_t *)d; |
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140 uint32_t dval; |
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141 |
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142 bgr = s1->ds->bgr; |
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143 for(x = 0; x < width; x++, s++, s24++) { |
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144 if ((be32_to_cpu(*cplane++) & 0xff000000) == 0x03000000) { |
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145 // 24-bit direct, BGR order |
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146 p8 = (uint8_t *)s24; |
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147 p8++; |
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148 b = *p8++; |
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149 g = *p8++; |
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150 r = *p8++; |
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151 if (bgr) |
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152 dval = rgb_to_pixel32bgr(r, g, b); |
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153 else |
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154 dval = rgb_to_pixel32(r, g, b); |
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155 } else { |
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156 val = *s; |
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157 dval = s1->palette[val]; |
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158 } |
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159 *p++ = dval; |
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160 } |
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161 } |
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162 |
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163 static inline int check_dirty(ram_addr_t page, ram_addr_t page24, |
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164 ram_addr_t cpage) |
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165 { |
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166 int ret; |
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167 unsigned int off; |
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168 |
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169 ret = cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG); |
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170 for (off = 0; off < TARGET_PAGE_SIZE * 4; off += TARGET_PAGE_SIZE) { |
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171 ret |= cpu_physical_memory_get_dirty(page24 + off, VGA_DIRTY_FLAG); |
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172 ret |= cpu_physical_memory_get_dirty(cpage + off, VGA_DIRTY_FLAG); |
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173 } |
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174 return ret; |
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175 } |
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176 |
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177 static inline void reset_dirty(TCXState *ts, ram_addr_t page_min, |
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178 ram_addr_t page_max, ram_addr_t page24, |
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179 ram_addr_t cpage) |
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180 { |
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181 cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE, |
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182 VGA_DIRTY_FLAG); |
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183 page_min -= ts->vram_offset; |
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184 page_max -= ts->vram_offset; |
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185 cpu_physical_memory_reset_dirty(page24 + page_min * 4, |
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186 page24 + page_max * 4 + TARGET_PAGE_SIZE, |
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187 VGA_DIRTY_FLAG); |
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188 cpu_physical_memory_reset_dirty(cpage + page_min * 4, |
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189 cpage + page_max * 4 + TARGET_PAGE_SIZE, |
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190 VGA_DIRTY_FLAG); |
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191 } |
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192 |
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193 /* Fixed line length 1024 allows us to do nice tricks not possible on |
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194 VGA... */ |
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195 static void tcx_update_display(void *opaque) |
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196 { |
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197 TCXState *ts = opaque; |
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198 ram_addr_t page, page_min, page_max; |
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199 int y, y_start, dd, ds; |
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200 uint8_t *d, *s; |
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201 void (*f)(TCXState *s1, uint8_t *dst, const uint8_t *src, int width); |
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202 |
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203 if (ds_get_bits_per_pixel(ts->ds) == 0) |
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204 return; |
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205 page = ts->vram_offset; |
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206 y_start = -1; |
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207 page_min = 0xffffffff; |
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208 page_max = 0; |
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209 d = ds_get_data(ts->ds); |
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210 s = ts->vram; |
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211 dd = ds_get_linesize(ts->ds); |
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212 ds = 1024; |
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213 |
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214 switch (ds_get_bits_per_pixel(ts->ds)) { |
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215 case 32: |
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216 f = tcx_draw_line32; |
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217 break; |
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218 case 15: |
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219 case 16: |
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220 f = tcx_draw_line16; |
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221 break; |
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222 default: |
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223 case 8: |
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224 f = tcx_draw_line8; |
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225 break; |
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226 case 0: |
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227 return; |
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228 } |
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229 |
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230 for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) { |
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231 if (cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG)) { |
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232 if (y_start < 0) |
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233 y_start = y; |
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234 if (page < page_min) |
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235 page_min = page; |
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236 if (page > page_max) |
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237 page_max = page; |
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238 f(ts, d, s, ts->width); |
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239 d += dd; |
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240 s += ds; |
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241 f(ts, d, s, ts->width); |
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242 d += dd; |
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243 s += ds; |
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244 f(ts, d, s, ts->width); |
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245 d += dd; |
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246 s += ds; |
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247 f(ts, d, s, ts->width); |
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248 d += dd; |
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249 s += ds; |
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250 } else { |
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251 if (y_start >= 0) { |
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252 /* flush to display */ |
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253 dpy_update(ts->ds, 0, y_start, |
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254 ts->width, y - y_start); |
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255 y_start = -1; |
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256 } |
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257 d += dd * 4; |
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258 s += ds * 4; |
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259 } |
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260 } |
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261 if (y_start >= 0) { |
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262 /* flush to display */ |
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263 dpy_update(ts->ds, 0, y_start, |
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264 ts->width, y - y_start); |
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265 } |
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266 /* reset modified pages */ |
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267 if (page_min <= page_max) { |
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268 cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE, |
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269 VGA_DIRTY_FLAG); |
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270 } |
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271 } |
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272 |
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273 static void tcx24_update_display(void *opaque) |
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274 { |
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275 TCXState *ts = opaque; |
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276 ram_addr_t page, page_min, page_max, cpage, page24; |
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277 int y, y_start, dd, ds; |
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278 uint8_t *d, *s; |
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279 uint32_t *cptr, *s24; |
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280 |
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281 if (ds_get_bits_per_pixel(ts->ds) != 32) |
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282 return; |
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283 page = ts->vram_offset; |
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284 page24 = ts->vram24_offset; |
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285 cpage = ts->cplane_offset; |
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286 y_start = -1; |
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287 page_min = 0xffffffff; |
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288 page_max = 0; |
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289 d = ds_get_data(ts->ds); |
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290 s = ts->vram; |
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291 s24 = ts->vram24; |
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292 cptr = ts->cplane; |
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293 dd = ds_get_linesize(ts->ds); |
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294 ds = 1024; |
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295 |
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296 for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE, |
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297 page24 += TARGET_PAGE_SIZE, cpage += TARGET_PAGE_SIZE) { |
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298 if (check_dirty(page, page24, cpage)) { |
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299 if (y_start < 0) |
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300 y_start = y; |
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301 if (page < page_min) |
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302 page_min = page; |
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303 if (page > page_max) |
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304 page_max = page; |
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305 tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); |
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306 d += dd; |
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307 s += ds; |
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308 cptr += ds; |
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309 s24 += ds; |
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310 tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); |
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311 d += dd; |
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312 s += ds; |
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313 cptr += ds; |
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314 s24 += ds; |
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315 tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); |
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316 d += dd; |
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317 s += ds; |
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318 cptr += ds; |
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319 s24 += ds; |
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320 tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); |
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321 d += dd; |
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322 s += ds; |
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323 cptr += ds; |
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324 s24 += ds; |
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325 } else { |
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326 if (y_start >= 0) { |
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327 /* flush to display */ |
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328 dpy_update(ts->ds, 0, y_start, |
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329 ts->width, y - y_start); |
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330 y_start = -1; |
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331 } |
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332 d += dd * 4; |
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333 s += ds * 4; |
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334 cptr += ds * 4; |
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335 s24 += ds * 4; |
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336 } |
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337 } |
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338 if (y_start >= 0) { |
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339 /* flush to display */ |
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340 dpy_update(ts->ds, 0, y_start, |
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341 ts->width, y - y_start); |
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342 } |
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343 /* reset modified pages */ |
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344 if (page_min <= page_max) { |
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345 reset_dirty(ts, page_min, page_max, page24, cpage); |
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346 } |
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347 } |
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348 |
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349 static void tcx_invalidate_display(void *opaque) |
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350 { |
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351 TCXState *s = opaque; |
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352 int i; |
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353 |
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354 for (i = 0; i < MAXX*MAXY; i += TARGET_PAGE_SIZE) { |
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355 cpu_physical_memory_set_dirty(s->vram_offset + i); |
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356 } |
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357 } |
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358 |
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359 static void tcx24_invalidate_display(void *opaque) |
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360 { |
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361 TCXState *s = opaque; |
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362 int i; |
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363 |
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364 tcx_invalidate_display(s); |
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365 for (i = 0; i < MAXX*MAXY * 4; i += TARGET_PAGE_SIZE) { |
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366 cpu_physical_memory_set_dirty(s->vram24_offset + i); |
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367 cpu_physical_memory_set_dirty(s->cplane_offset + i); |
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368 } |
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369 } |
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370 |
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371 static void tcx_save(QEMUFile *f, void *opaque) |
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372 { |
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373 TCXState *s = opaque; |
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374 |
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375 qemu_put_be16s(f, &s->height); |
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376 qemu_put_be16s(f, &s->width); |
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377 qemu_put_be16s(f, &s->depth); |
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378 qemu_put_buffer(f, s->r, 256); |
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379 qemu_put_buffer(f, s->g, 256); |
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380 qemu_put_buffer(f, s->b, 256); |
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381 qemu_put_8s(f, &s->dac_index); |
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382 qemu_put_8s(f, &s->dac_state); |
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383 } |
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384 |
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385 static int tcx_load(QEMUFile *f, void *opaque, int version_id) |
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386 { |
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387 TCXState *s = opaque; |
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388 uint32_t dummy; |
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389 |
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390 if (version_id != 3 && version_id != 4) |
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391 return -EINVAL; |
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392 |
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393 if (version_id == 3) { |
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394 qemu_get_be32s(f, &dummy); |
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395 qemu_get_be32s(f, &dummy); |
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396 qemu_get_be32s(f, &dummy); |
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397 } |
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398 qemu_get_be16s(f, &s->height); |
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399 qemu_get_be16s(f, &s->width); |
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400 qemu_get_be16s(f, &s->depth); |
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401 qemu_get_buffer(f, s->r, 256); |
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402 qemu_get_buffer(f, s->g, 256); |
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403 qemu_get_buffer(f, s->b, 256); |
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404 qemu_get_8s(f, &s->dac_index); |
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405 qemu_get_8s(f, &s->dac_state); |
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406 update_palette_entries(s, 0, 256); |
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407 if (s->depth == 24) |
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408 tcx24_invalidate_display(s); |
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409 else |
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410 tcx_invalidate_display(s); |
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411 |
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412 return 0; |
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413 } |
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414 |
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415 static void tcx_reset(void *opaque) |
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416 { |
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417 TCXState *s = opaque; |
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418 |
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419 /* Initialize palette */ |
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420 memset(s->r, 0, 256); |
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421 memset(s->g, 0, 256); |
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422 memset(s->b, 0, 256); |
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423 s->r[255] = s->g[255] = s->b[255] = 255; |
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424 update_palette_entries(s, 0, 256); |
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425 memset(s->vram, 0, MAXX*MAXY); |
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426 cpu_physical_memory_reset_dirty(s->vram_offset, s->vram_offset + |
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427 MAXX * MAXY * (1 + 4 + 4), VGA_DIRTY_FLAG); |
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428 s->dac_index = 0; |
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429 s->dac_state = 0; |
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430 } |
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431 |
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432 static uint32_t tcx_dac_readl(void *opaque, target_phys_addr_t addr) |
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433 { |
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434 return 0; |
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435 } |
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436 |
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437 static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
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438 { |
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439 TCXState *s = opaque; |
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440 |
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441 switch (addr) { |
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442 case 0: |
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443 s->dac_index = val >> 24; |
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444 s->dac_state = 0; |
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445 break; |
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446 case 4: |
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447 switch (s->dac_state) { |
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448 case 0: |
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449 s->r[s->dac_index] = val >> 24; |
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450 update_palette_entries(s, s->dac_index, s->dac_index + 1); |
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451 s->dac_state++; |
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452 break; |
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453 case 1: |
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454 s->g[s->dac_index] = val >> 24; |
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455 update_palette_entries(s, s->dac_index, s->dac_index + 1); |
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456 s->dac_state++; |
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457 break; |
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458 case 2: |
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459 s->b[s->dac_index] = val >> 24; |
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460 update_palette_entries(s, s->dac_index, s->dac_index + 1); |
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461 s->dac_index = (s->dac_index + 1) & 255; // Index autoincrement |
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462 default: |
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463 s->dac_state = 0; |
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464 break; |
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465 } |
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466 break; |
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467 default: |
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468 break; |
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469 } |
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470 return; |
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471 } |
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472 |
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473 static CPUReadMemoryFunc *tcx_dac_read[3] = { |
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474 NULL, |
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475 NULL, |
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476 tcx_dac_readl, |
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477 }; |
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478 |
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479 static CPUWriteMemoryFunc *tcx_dac_write[3] = { |
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480 NULL, |
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481 NULL, |
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482 tcx_dac_writel, |
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483 }; |
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484 |
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485 static uint32_t tcx_dummy_readl(void *opaque, target_phys_addr_t addr) |
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486 { |
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487 return 0; |
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488 } |
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489 |
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490 static void tcx_dummy_writel(void *opaque, target_phys_addr_t addr, |
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491 uint32_t val) |
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492 { |
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493 } |
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494 |
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495 static CPUReadMemoryFunc *tcx_dummy_read[3] = { |
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496 NULL, |
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497 NULL, |
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498 tcx_dummy_readl, |
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499 }; |
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500 |
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501 static CPUWriteMemoryFunc *tcx_dummy_write[3] = { |
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502 NULL, |
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503 NULL, |
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504 tcx_dummy_writel, |
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505 }; |
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506 |
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507 void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base, |
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508 unsigned long vram_offset, int vram_size, int width, int height, |
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509 int depth) |
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510 { |
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511 TCXState *s; |
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512 int io_memory, dummy_memory; |
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513 int size; |
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514 |
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515 s = qemu_mallocz(sizeof(TCXState)); |
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516 if (!s) |
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517 return; |
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518 s->ds = ds; |
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519 s->addr = addr; |
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520 s->vram_offset = vram_offset; |
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521 s->width = width; |
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522 s->height = height; |
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523 s->depth = depth; |
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524 |
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525 // 8-bit plane |
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526 s->vram = vram_base; |
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527 size = vram_size; |
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528 cpu_register_physical_memory(addr + 0x00800000ULL, size, vram_offset); |
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529 vram_offset += size; |
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530 vram_base += size; |
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531 |
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532 io_memory = cpu_register_io_memory(0, tcx_dac_read, tcx_dac_write, s); |
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533 cpu_register_physical_memory(addr + 0x00200000ULL, TCX_DAC_NREGS, |
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534 io_memory); |
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535 |
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536 dummy_memory = cpu_register_io_memory(0, tcx_dummy_read, tcx_dummy_write, |
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537 s); |
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538 cpu_register_physical_memory(addr + 0x00700000ULL, TCX_TEC_NREGS, |
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539 dummy_memory); |
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540 if (depth == 24) { |
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541 // 24-bit plane |
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542 size = vram_size * 4; |
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543 s->vram24 = (uint32_t *)vram_base; |
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544 s->vram24_offset = vram_offset; |
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545 cpu_register_physical_memory(addr + 0x02000000ULL, size, vram_offset); |
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546 vram_offset += size; |
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547 vram_base += size; |
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548 |
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549 // Control plane |
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550 size = vram_size * 4; |
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551 s->cplane = (uint32_t *)vram_base; |
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552 s->cplane_offset = vram_offset; |
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553 cpu_register_physical_memory(addr + 0x0a000000ULL, size, vram_offset); |
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554 s->console = graphic_console_init(s->ds, tcx24_update_display, |
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555 tcx24_invalidate_display, |
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556 tcx24_screen_dump, NULL, s); |
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557 } else { |
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558 cpu_register_physical_memory(addr + 0x00300000ULL, TCX_THC_NREGS_8, |
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559 dummy_memory); |
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560 s->console = graphic_console_init(s->ds, tcx_update_display, |
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561 tcx_invalidate_display, |
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562 tcx_screen_dump, NULL, s); |
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563 } |
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564 // NetBSD writes here even with 8-bit display |
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565 cpu_register_physical_memory(addr + 0x00301000ULL, TCX_THC_NREGS_24, |
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566 dummy_memory); |
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567 |
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568 register_savevm("tcx", addr, 4, tcx_save, tcx_load, s); |
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569 qemu_register_reset(tcx_reset, s); |
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570 tcx_reset(s); |
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571 qemu_console_resize(s->console, width, height); |
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572 } |
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573 |
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574 static void tcx_screen_dump(void *opaque, const char *filename) |
|
575 { |
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576 TCXState *s = opaque; |
|
577 FILE *f; |
|
578 uint8_t *d, *d1, v; |
|
579 int y, x; |
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580 |
|
581 f = fopen(filename, "wb"); |
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582 if (!f) |
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583 return; |
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584 fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255); |
|
585 d1 = s->vram; |
|
586 for(y = 0; y < s->height; y++) { |
|
587 d = d1; |
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588 for(x = 0; x < s->width; x++) { |
|
589 v = *d; |
|
590 fputc(s->r[v], f); |
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591 fputc(s->g[v], f); |
|
592 fputc(s->b[v], f); |
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593 d++; |
|
594 } |
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595 d1 += MAXX; |
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596 } |
|
597 fclose(f); |
|
598 return; |
|
599 } |
|
600 |
|
601 static void tcx24_screen_dump(void *opaque, const char *filename) |
|
602 { |
|
603 TCXState *s = opaque; |
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604 FILE *f; |
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605 uint8_t *d, *d1, v; |
|
606 uint32_t *s24, *cptr, dval; |
|
607 int y, x; |
|
608 |
|
609 f = fopen(filename, "wb"); |
|
610 if (!f) |
|
611 return; |
|
612 fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255); |
|
613 d1 = s->vram; |
|
614 s24 = s->vram24; |
|
615 cptr = s->cplane; |
|
616 for(y = 0; y < s->height; y++) { |
|
617 d = d1; |
|
618 for(x = 0; x < s->width; x++, d++, s24++) { |
|
619 if ((*cptr++ & 0xff000000) == 0x03000000) { // 24-bit direct |
|
620 dval = *s24 & 0x00ffffff; |
|
621 fputc((dval >> 16) & 0xff, f); |
|
622 fputc((dval >> 8) & 0xff, f); |
|
623 fputc(dval & 0xff, f); |
|
624 } else { |
|
625 v = *d; |
|
626 fputc(s->r[v], f); |
|
627 fputc(s->g[v], f); |
|
628 fputc(s->b[v], f); |
|
629 } |
|
630 } |
|
631 d1 += MAXX; |
|
632 } |
|
633 fclose(f); |
|
634 return; |
|
635 } |