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1 import qemu |
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2 |
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3 class syborg_serial(qemu.devclass): |
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4 REG_ID = 0 |
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5 REG_DATA = 1 |
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6 REG_FIFO_COUNT = 2 |
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7 REG_INT_ENABLE = 3 |
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8 REG_DMA_TX_ADDR = 4 |
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9 REG_DMA_TX_COUNT = 5 # triggers dma |
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10 REG_DMA_RX_ADDR = 6 |
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11 REG_DMA_RX_COUNT = 7 # triggers dma |
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12 |
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13 def update_irq(self): |
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14 level = 2 # TX DMA complete |
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15 if len(self.fifo) > 0: |
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16 level |= 1 # FIFO not empty |
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17 if self.dma_rx_count == 0: |
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18 level |= 4 # RX DMA complete |
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19 self.set_irq_level(0, (level & self.int_enable) != 0) |
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20 |
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21 def can_receive(self): |
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22 return self.fifo_size - len(self.fifo) |
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23 |
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24 def receive(self, buf): |
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25 for x in buf: |
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26 ch = ord(x) |
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27 if self.dma_rx_count > 0: |
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28 self.dma_writeb(self.dma_rx_addr, ch) |
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29 self.dma_rx_addr += 1 |
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30 self.dma_rx_count -= 1 |
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31 else: |
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32 self.fifo.append(ch) |
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33 self.update_irq() |
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34 |
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35 def do_dma_tx(self, count): |
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36 # TODO: Optimize block transmits. |
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37 while count > 0: |
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38 ch = self.dma_readb(self.dma_tx_addr) |
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39 self.chardev.write(ch) |
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40 self.dma_tx_addr += 1 |
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41 count -= 1 |
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42 self.update_irq() |
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43 |
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44 def dma_rx_start(self, count): |
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45 while (count > 0) and (len(self.fifo) > 0): |
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46 ch = self.fifo.pop(0) |
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47 self.dma_writeb(self.dma_rx_addr, ch) |
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48 self.dma_rx_addr += 1 |
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49 count -= 1 |
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50 self.dma_rx_count = count |
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51 self.update_irq() |
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52 |
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53 def create(self): |
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54 self.fifo_size = self.properties["fifo-size"] |
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55 self.chardev = self.properties["chardev"] |
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56 self.fifo=[] |
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57 self.int_enable = 0 |
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58 self.chardev.set_handlers(self.can_receive, self.receive) |
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59 self.dma_tx_addr = 0 |
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60 self.dma_rx_addr = 0 |
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61 self.dma_rx_count = 0 |
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62 |
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63 def read_reg(self, offset): |
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64 offset >>= 2 |
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65 if offset == self.REG_ID: |
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66 return 0xc51d0001 |
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67 elif offset == self.REG_DATA: |
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68 if len(self.fifo) == 0: |
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69 return 0xffffffff |
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70 val = self.fifo.pop(0) |
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71 self.update_irq(); |
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72 return val |
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73 elif offset == self.REG_FIFO_COUNT: |
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74 return len(self.fifo) |
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75 elif offset == self.REG_INT_ENABLE: |
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76 return self.int_enable |
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77 elif offset == self.REG_DMA_TX_ADDR: |
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78 return self.dma_tx_addr |
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79 elif offset == self.REG_DMA_TX_COUNT: |
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80 return 0 |
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81 elif offset == self.REG_DMA_RX_ADDR: |
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82 return self.dma_rx_addr |
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83 elif offset == self.REG_DMA_RX_COUNT: |
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84 return self.dma_rx_count |
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85 return 0 |
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86 |
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87 def write_reg(self, offset, value): |
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88 offset >>= 2 |
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89 if offset == self.REG_DATA: |
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90 self.chardev.write(value) |
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91 elif offset == self.REG_INT_ENABLE: |
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92 self.int_enable = value & 7 |
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93 self.update_irq() |
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94 elif offset == self.REG_DMA_TX_ADDR: |
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95 self.dma_tx_addr = value |
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96 elif offset == self.REG_DMA_TX_COUNT: |
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97 self.do_dma_tx(value) |
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98 elif offset == self.REG_DMA_RX_ADDR: |
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99 self.dma_rx_addr = value |
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100 elif offset == self.REG_DMA_RX_COUNT: |
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101 self.dma_rx_start(value) |
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102 |
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103 def save(self, f): |
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104 f.put_u32(self.fifo_size) |
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105 f.put_u32(self.int_enable) |
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106 f.put_u32(self.dma_tx_addr) |
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107 f.put_u32(self.dma_rx_addr) |
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108 f.put_u32(self.dma_rx_count) |
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109 f.put_u32(len(self.fifo)) |
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110 for x in self.fifo: |
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111 f.put_u32(x) |
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112 |
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113 def load(self, f): |
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114 if self.fifo_size != f.get_u32(): |
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115 raise ValueError, "fifo size mismatch" |
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116 self.int_enable = f.get_u32() |
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117 self.dma_tx_addr = f.get_u32() |
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118 self.dma_rx_addr = f.get_u32() |
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119 self.dma_rx_count = f.get_u32() |
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120 n = f.get_u32() |
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121 self.fifo = [] |
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122 while n > 0: |
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123 self.fifo.append(f.get_u32()) |
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124 n -= 1; |
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125 |
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126 # Device class properties |
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127 regions = [qemu.ioregion(0x1000, readl=read_reg, writel=write_reg)] |
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128 irqs = 1 |
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129 name = "syborg,serial" |
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130 properties = {"fifo-size":16, "chardev":None} |
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131 |
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132 qemu.register_device(syborg_serial) |