1 /* ppc-dis.c -- Disassemble PowerPC instructions

     2    Copyright 1994 Free Software Foundation, Inc.

     3    Written by Ian Lance Taylor, Cygnus Support

     4 

     5 This file is part of GDB, GAS, and the GNU binutils.

     6 

     7 GDB, GAS, and the GNU binutils are free software; you can redistribute

     8 them and/or modify them under the terms of the GNU General Public

     9 License as published by the Free Software Foundation; either version

    10 2, or (at your option) any later version.

    11 

    12 GDB, GAS, and the GNU binutils are distributed in the hope that they

    13 will be useful, but WITHOUT ANY WARRANTY; without even the implied

    14 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See

    15 the GNU General Public License for more details.

    16 

    17 You should have received a copy of the GNU General Public License

    18 along with this file; see the file COPYING.  If not, write to the Free

    19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */

    20 #include "dis-asm.h"

    21 

    22 /* ppc.h -- Header file for PowerPC opcode table

    23    Copyright 1994 Free Software Foundation, Inc.

    24    Written by Ian Lance Taylor, Cygnus Support

    25 

    26 This file is part of GDB, GAS, and the GNU binutils.

    27 

    28 GDB, GAS, and the GNU binutils are free software; you can redistribute

    29 them and/or modify them under the terms of the GNU General Public

    30 License as published by the Free Software Foundation; either version

    31 1, or (at your option) any later version.

    32 

    33 GDB, GAS, and the GNU binutils are distributed in the hope that they

    34 will be useful, but WITHOUT ANY WARRANTY; without even the implied

    35 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See

    36 the GNU General Public License for more details.

    37 

    38 You should have received a copy of the GNU General Public License

    39 along with this file; see the file COPYING.  If not, write to the Free

    40 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */

    41 

    42 /* The opcode table is an array of struct powerpc_opcode.  */

    43 

    44 struct powerpc_opcode

    45 {

    46   /* The opcode name.  */

    47   const char *name;

    48 

    49   /* The opcode itself.  Those bits which will be filled in with

    50      operands are zeroes.  */

    51   uint32_t opcode;

    52 

    53   /* The opcode mask.  This is used by the disassembler.  This is a

    54      mask containing ones indicating those bits which must match the

    55      opcode field, and zeroes indicating those bits which need not

    56      match (and are presumably filled in by operands).  */

    57   uint32_t mask;

    58 

    59   /* One bit flags for the opcode.  These are used to indicate which

    60      specific processors support the instructions.  The defined values

    61      are listed below.  */

    62   uint32_t flags;

    63 

    64   /* An array of operand codes.  Each code is an index into the

    65      operand table.  They appear in the order which the operands must

    66      appear in assembly code, and are terminated by a zero.  */

    67   unsigned char operands[8];

    68 };

    69 

    70 /* The table itself is sorted by major opcode number, and is otherwise

    71    in the order in which the disassembler should consider

    72    instructions.  */

    73 extern const struct powerpc_opcode powerpc_opcodes[];

    74 extern const int powerpc_num_opcodes;

    75 

    76 /* Values defined for the flags field of a struct powerpc_opcode.  */

    77 

    78 /* Opcode is defined for the PowerPC architecture.  */

    79 #define PPC_OPCODE_PPC (01)

    80 

    81 /* Opcode is defined for the POWER (RS/6000) architecture.  */

    82 #define PPC_OPCODE_POWER (02)

    83 

    84 /* Opcode is defined for the POWER2 (Rios 2) architecture.  */

    85 #define PPC_OPCODE_POWER2 (04)

    86 

    87 /* Opcode is only defined on 32 bit architectures.  */

    88 #define PPC_OPCODE_32 (010)

    89 

    90 /* Opcode is only defined on 64 bit architectures.  */

    91 #define PPC_OPCODE_64 (020)

    92 

    93 /* Opcode is supported by the Motorola PowerPC 601 processor.  The 601

    94    is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,

    95    but it also supports many additional POWER instructions.  */

    96 #define PPC_OPCODE_601 (040)

    97 

    98 /* A macro to extract the major opcode from an instruction.  */

    99 #define PPC_OP(i) (((i) >> 26) & 0x3f)

   100 

   101 /* The operands table is an array of struct powerpc_operand.  */

   102 

   103 struct powerpc_operand

   104 {

   105   /* The number of bits in the operand.  */

   106   int bits;

   107 

   108   /* How far the operand is left shifted in the instruction.  */

   109   int shift;

   110 

   111   /* Insertion function.  This is used by the assembler.  To insert an

   112      operand value into an instruction, check this field.

   113 

   114      If it is NULL, execute

   115          i |= (op & ((1 << o->bits) - 1)) << o->shift;

   116      (i is the instruction which we are filling in, o is a pointer to

   117      this structure, and op is the opcode value; this assumes twos

   118      complement arithmetic).

   119 

   120      If this field is not NULL, then simply call it with the

   121      instruction and the operand value.  It will return the new value

   122      of the instruction.  If the ERRMSG argument is not NULL, then if

   123      the operand value is illegal, *ERRMSG will be set to a warning

   124      string (the operand will be inserted in any case).  If the

   125      operand value is legal, *ERRMSG will be unchanged (most operands

   126      can accept any value).  */

   127   unsigned long (*insert)(uint32_t instruction, int32_t op,

   128 				   const char **errmsg);

   129 

   130   /* Extraction function.  This is used by the disassembler.  To

   131      extract this operand type from an instruction, check this field.

   132 

   133      If it is NULL, compute

   134          op = ((i) >> o->shift) & ((1 << o->bits) - 1);

   135 	 if ((o->flags & PPC_OPERAND_SIGNED) != 0

   136 	     && (op & (1 << (o->bits - 1))) != 0)

   137 	   op -= 1 << o->bits;

   138      (i is the instruction, o is a pointer to this structure, and op

   139      is the result; this assumes twos complement arithmetic).

   140 

   141      If this field is not NULL, then simply call it with the

   142      instruction value.  It will return the value of the operand.  If

   143      the INVALID argument is not NULL, *INVALID will be set to

   144      non-zero if this operand type can not actually be extracted from

   145      this operand (i.e., the instruction does not match).  If the

   146      operand is valid, *INVALID will not be changed.  */

   147   long (*extract) (uint32_t instruction, int *invalid);

   148 

   149   /* One bit syntax flags.  */

   150   uint32_t flags;

   151 };

   152 

   153 /* Elements in the table are retrieved by indexing with values from

   154    the operands field of the powerpc_opcodes table.  */

   155 

   156 extern const struct powerpc_operand powerpc_operands[];

   157 

   158 /* Values defined for the flags field of a struct powerpc_operand.  */

   159 

   160 /* This operand takes signed values.  */

   161 #define PPC_OPERAND_SIGNED (01)

   162 

   163 /* This operand takes signed values, but also accepts a full positive

   164    range of values when running in 32 bit mode.  That is, if bits is

   165    16, it takes any value from -0x8000 to 0xffff.  In 64 bit mode,

   166    this flag is ignored.  */

   167 #define PPC_OPERAND_SIGNOPT (02)

   168 

   169 /* This operand does not actually exist in the assembler input.  This

   170    is used to support extended mnemonics such as mr, for which two

   171    operands fields are identical.  The assembler should call the

   172    insert function with any op value.  The disassembler should call

   173    the extract function, ignore the return value, and check the value

   174    placed in the valid argument.  */

   175 #define PPC_OPERAND_FAKE (04)

   176 

   177 /* The next operand should be wrapped in parentheses rather than

   178    separated from this one by a comma.  This is used for the load and

   179    store instructions which want their operands to look like

   180        reg,displacement(reg)

   181    */

   182 #define PPC_OPERAND_PARENS (010)

   183 

   184 /* This operand may use the symbolic names for the CR fields, which

   185    are

   186        lt  0	gt  1	eq  2	so  3	un  3

   187        cr0 0	cr1 1	cr2 2	cr3 3

   188        cr4 4	cr5 5	cr6 6	cr7 7

   189    These may be combined arithmetically, as in cr2*4+gt.  These are

   190    only supported on the PowerPC, not the POWER.  */

   191 #define PPC_OPERAND_CR (020)

   192 

   193 /* This operand names a register.  The disassembler uses this to print

   194    register names with a leading 'r'.  */

   195 #define PPC_OPERAND_GPR (040)

   196 

   197 /* This operand names a floating point register.  The disassembler

   198    prints these with a leading 'f'.  */

   199 #define PPC_OPERAND_FPR (0100)

   200 

   201 /* This operand is a relative branch displacement.  The disassembler

   202    prints these symbolically if possible.  */

   203 #define PPC_OPERAND_RELATIVE (0200)

   204 

   205 /* This operand is an absolute branch address.  The disassembler

   206    prints these symbolically if possible.  */

   207 #define PPC_OPERAND_ABSOLUTE (0400)

   208 

   209 /* This operand is optional, and is zero if omitted.  This is used for

   210    the optional BF and L fields in the comparison instructions.  The

   211    assembler must count the number of operands remaining on the line,

   212    and the number of operands remaining for the opcode, and decide

   213    whether this operand is present or not.  The disassembler should

   214    print this operand out only if it is not zero.  */

   215 #define PPC_OPERAND_OPTIONAL (01000)

   216 

   217 /* This flag is only used with PPC_OPERAND_OPTIONAL.  If this operand

   218    is omitted, then for the next operand use this operand value plus

   219    1, ignoring the next operand field for the opcode.  This wretched

   220    hack is needed because the Power rotate instructions can take

   221    either 4 or 5 operands.  The disassembler should print this operand

   222    out regardless of the PPC_OPERAND_OPTIONAL field.  */

   223 #define PPC_OPERAND_NEXT (02000)

   224 

   225 /* This operand should be regarded as a negative number for the

   226    purposes of overflow checking (i.e., the normal most negative

   227    number is disallowed and one more than the normal most positive

   228    number is allowed).  This flag will only be set for a signed

   229    operand.  */

   230 #define PPC_OPERAND_NEGATIVE (04000)

   231 

   232 /* The POWER and PowerPC assemblers use a few macros.  We keep them

   233    with the operands table for simplicity.  The macro table is an

   234    array of struct powerpc_macro.  */

   235 

   236 struct powerpc_macro

   237 {

   238   /* The macro name.  */

   239   const char *name;

   240 

   241   /* The number of operands the macro takes.  */

   242   unsigned int operands;

   243 

   244   /* One bit flags for the opcode.  These are used to indicate which

   245      specific processors support the instructions.  The values are the

   246      same as those for the struct powerpc_opcode flags field.  */

   247   uint32_t flags;

   248 

   249   /* A format string to turn the macro into a normal instruction.

   250      Each %N in the string is replaced with operand number N (zero

   251      based).  */

   252   const char *format;

   253 };

   254 

   255 extern const struct powerpc_macro powerpc_macros[];

   256 extern const int powerpc_num_macros;

   257 

   258 /* ppc-opc.c -- PowerPC opcode list

   259    Copyright 1994 Free Software Foundation, Inc.

   260    Written by Ian Lance Taylor, Cygnus Support

   261 

   262 This file is part of GDB, GAS, and the GNU binutils.

   263 

   264 GDB, GAS, and the GNU binutils are free software; you can redistribute

   265 them and/or modify them under the terms of the GNU General Public

   266 License as published by the Free Software Foundation; either version

   267 2, or (at your option) any later version.

   268 

   269 GDB, GAS, and the GNU binutils are distributed in the hope that they

   270 will be useful, but WITHOUT ANY WARRANTY; without even the implied

   271 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See

   272 the GNU General Public License for more details.

   273 

   274 You should have received a copy of the GNU General Public License

   275 along with this file; see the file COPYING.  If not, write to the Free

   276 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */

   277 

   278 /* This file holds the PowerPC opcode table.  The opcode table

   279    includes almost all of the extended instruction mnemonics.  This

   280    permits the disassembler to use them, and simplifies the assembler

   281    logic, at the cost of increasing the table size.  The table is

   282    strictly constant data, so the compiler should be able to put it in

   283    the .text section.

   284 

   285    This file also holds the operand table.  All knowledge about

   286    inserting operands into instructions and vice-versa is kept in this

   287    file.  */

   288 

   289 /* Local insertion and extraction functions.  */

   290 

   291 static unsigned long insert_bat (uint32_t, int32_t, const char **);

   292 static long extract_bat(uint32_t, int *);

   293 static unsigned long insert_bba(uint32_t, int32_t, const char **);

   294 static long extract_bba(uint32_t, int *);

   295 static unsigned long insert_bd(uint32_t, int32_t, const char **);

   296 static long extract_bd(uint32_t, int *);

   297 static unsigned long insert_bdm(uint32_t, int32_t, const char **);

   298 static long extract_bdm(uint32_t, int *);

   299 static unsigned long insert_bdp(uint32_t, int32_t, const char **);

   300 static long extract_bdp(uint32_t, int *);

   301 static unsigned long insert_bo(uint32_t, int32_t, const char **);

   302 static long extract_bo(uint32_t, int *);

   303 static unsigned long insert_boe(uint32_t, int32_t, const char **);

   304 static long extract_boe(uint32_t, int *);

   305 static unsigned long insert_ds(uint32_t, int32_t, const char **);

   306 static long extract_ds(uint32_t, int *);

   307 static unsigned long insert_li(uint32_t, int32_t, const char **);

   308 static long extract_li(uint32_t, int *);

   309 static unsigned long insert_mbe(uint32_t, int32_t, const char **);

   310 static long extract_mbe(uint32_t, int *);

   311 static unsigned long insert_mb6(uint32_t, int32_t, const char **);

   312 static long extract_mb6(uint32_t, int *);

   313 static unsigned long insert_nb(uint32_t, int32_t, const char **);

   314 static long extract_nb(uint32_t, int *);

   315 static unsigned long insert_nsi(uint32_t, int32_t, const char **);

   316 static long extract_nsi(uint32_t, int *);

   317 static unsigned long insert_ral(uint32_t, int32_t, const char **);

   318 static unsigned long insert_ram(uint32_t, int32_t, const char **);

   319 static unsigned long insert_ras(uint32_t, int32_t, const char **);

   320 static unsigned long insert_rbs(uint32_t, int32_t, const char **);

   321 static long extract_rbs(uint32_t, int *);

   322 static unsigned long insert_sh6(uint32_t, int32_t, const char **);

   323 static long extract_sh6(uint32_t, int *);

   324 static unsigned long insert_spr(uint32_t, int32_t, const char **);

   325 static long extract_spr(uint32_t, int *);

   326 static unsigned long insert_tbr(uint32_t, int32_t, const char **);

   327 static long extract_tbr(uint32_t, int *);

   328 

   329 /* The operands table.

   330 

   331    The fields are bits, shift, signed, insert, extract, flags.  */

   332 

   333 const struct powerpc_operand powerpc_operands[] =

   334 {

   335   /* The zero index is used to indicate the end of the list of

   336      operands.  */

   337 #define UNUSED (0)

   338   { 0, 0, 0, 0, 0 },

   339 

   340   /* The BA field in an XL form instruction.  */

   341 #define BA (1)

   342 #define BA_MASK (0x1f << 16)

   343   { 5, 16, 0, 0, PPC_OPERAND_CR },

   344 

   345   /* The BA field in an XL form instruction when it must be the same

   346      as the BT field in the same instruction.  */

   347 #define BAT (2)

   348   { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },

   349 

   350   /* The BB field in an XL form instruction.  */

   351 #define BB (3)

   352 #define BB_MASK (0x1f << 11)

   353   { 5, 11, 0, 0, PPC_OPERAND_CR },

   354 

   355   /* The BB field in an XL form instruction when it must be the same

   356      as the BA field in the same instruction.  */

   357 #define BBA (4)

   358   { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },

   359 

   360   /* The BD field in a B form instruction.  The lower two bits are

   361      forced to zero.  */

   362 #define BD (5)

   363   { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },

   364 

   365   /* The BD field in a B form instruction when absolute addressing is

   366      used.  */

   367 #define BDA (6)

   368   { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },

   369 

   370   /* The BD field in a B form instruction when the - modifier is used.

   371      This sets the y bit of the BO field appropriately.  */

   372 #define BDM (7)

   373   { 16, 0, insert_bdm, extract_bdm,

   374       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },

   375 

   376   /* The BD field in a B form instruction when the - modifier is used

   377      and absolute address is used.  */

   378 #define BDMA (8)

   379   { 16, 0, insert_bdm, extract_bdm,

   380       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },

   381 

   382   /* The BD field in a B form instruction when the + modifier is used.

   383      This sets the y bit of the BO field appropriately.  */

   384 #define BDP (9)

   385   { 16, 0, insert_bdp, extract_bdp,

   386       PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },

   387 

   388   /* The BD field in a B form instruction when the + modifier is used

   389      and absolute addressing is used.  */

   390 #define BDPA (10)

   391   { 16, 0, insert_bdp, extract_bdp,

   392       PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },

   393 

   394   /* The BF field in an X or XL form instruction.  */

   395 #define BF (11)

   396   { 3, 23, 0, 0, PPC_OPERAND_CR },

   397 

   398   /* An optional BF field.  This is used for comparison instructions,

   399      in which an omitted BF field is taken as zero.  */

   400 #define OBF (12)

   401   { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },

   402 

   403   /* The BFA field in an X or XL form instruction.  */

   404 #define BFA (13)

   405   { 3, 18, 0, 0, PPC_OPERAND_CR },

   406 

   407   /* The BI field in a B form or XL form instruction.  */

   408 #define BI (14)

   409 #define BI_MASK (0x1f << 16)

   410   { 5, 16, 0, 0, PPC_OPERAND_CR },

   411 

   412   /* The BO field in a B form instruction.  Certain values are

   413      illegal.  */

   414 #define BO (15)

   415 #define BO_MASK (0x1f << 21)

   416   { 5, 21, insert_bo, extract_bo, 0 },

   417 

   418   /* The BO field in a B form instruction when the + or - modifier is

   419      used.  This is like the BO field, but it must be even.  */

   420 #define BOE (16)

   421   { 5, 21, insert_boe, extract_boe, 0 },

   422 

   423   /* The BT field in an X or XL form instruction.  */

   424 #define BT (17)

   425   { 5, 21, 0, 0, PPC_OPERAND_CR },

   426 

   427   /* The condition register number portion of the BI field in a B form

   428      or XL form instruction.  This is used for the extended

   429      conditional branch mnemonics, which set the lower two bits of the

   430      BI field.  This field is optional.  */

   431 #define CR (18)

   432   { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },

   433 

   434   /* The D field in a D form instruction.  This is a displacement off

   435      a register, and implies that the next operand is a register in

   436      parentheses.  */

   437 #define D (19)

   438   { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },

   439 

   440   /* The DS field in a DS form instruction.  This is like D, but the

   441      lower two bits are forced to zero.  */

   442 #define DS (20)

   443   { 16, 0, insert_ds, extract_ds, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },

   444 

   445   /* The FL1 field in a POWER SC form instruction.  */

   446 #define FL1 (21)

   447   { 4, 12, 0, 0, 0 },

   448 

   449   /* The FL2 field in a POWER SC form instruction.  */

   450 #define FL2 (22)

   451   { 3, 2, 0, 0, 0 },

   452 

   453   /* The FLM field in an XFL form instruction.  */

   454 #define FLM (23)

   455   { 8, 17, 0, 0, 0 },

   456 

   457   /* The FRA field in an X or A form instruction.  */

   458 #define FRA (24)

   459 #define FRA_MASK (0x1f << 16)

   460   { 5, 16, 0, 0, PPC_OPERAND_FPR },

   461 

   462   /* The FRB field in an X or A form instruction.  */

   463 #define FRB (25)

   464 #define FRB_MASK (0x1f << 11)

   465   { 5, 11, 0, 0, PPC_OPERAND_FPR },

   466 

   467   /* The FRC field in an A form instruction.  */

   468 #define FRC (26)

   469 #define FRC_MASK (0x1f << 6)

   470   { 5, 6, 0, 0, PPC_OPERAND_FPR },

   471 

   472   /* The FRS field in an X form instruction or the FRT field in a D, X

   473      or A form instruction.  */

   474 #define FRS (27)

   475 #define FRT (FRS)

   476   { 5, 21, 0, 0, PPC_OPERAND_FPR },

   477 

   478   /* The FXM field in an XFX instruction.  */

   479 #define FXM (28)

   480 #define FXM_MASK (0xff << 12)

   481   { 8, 12, 0, 0, 0 },

   482 

   483   /* The L field in a D or X form instruction.  */

   484 #define L (29)

   485   { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },

   486 

   487   /* The LEV field in a POWER SC form instruction.  */

   488 #define LEV (30)

   489   { 7, 5, 0, 0, 0 },

   490 

   491   /* The LI field in an I form instruction.  The lower two bits are

   492      forced to zero.  */

   493 #define LI (31)

   494   { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },

   495 

   496   /* The LI field in an I form instruction when used as an absolute

   497      address.  */

   498 #define LIA (32)

   499   { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },

   500 

   501   /* The MB field in an M form instruction.  */

   502 #define MB (33)

   503 #define MB_MASK (0x1f << 6)

   504   { 5, 6, 0, 0, 0 },

   505 

   506   /* The ME field in an M form instruction.  */

   507 #define ME (34)

   508 #define ME_MASK (0x1f << 1)

   509   { 5, 1, 0, 0, 0 },

   510 

   511   /* The MB and ME fields in an M form instruction expressed a single

   512      operand which is a bitmask indicating which bits to select.  This

   513      is a two operand form using PPC_OPERAND_NEXT.  See the

   514      description in opcode/ppc.h for what this means.  */

   515 #define MBE (35)

   516   { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },

   517   { 32, 0, insert_mbe, extract_mbe, 0 },

   518 

   519   /* The MB or ME field in an MD or MDS form instruction.  The high

   520      bit is wrapped to the low end.  */

   521 #define MB6 (37)

   522 #define ME6 (MB6)

   523 #define MB6_MASK (0x3f << 5)

   524   { 6, 5, insert_mb6, extract_mb6, 0 },

   525 

   526   /* The NB field in an X form instruction.  The value 32 is stored as

   527      0.  */

   528 #define NB (38)

   529   { 6, 11, insert_nb, extract_nb, 0 },

   530 

   531   /* The NSI field in a D form instruction.  This is the same as the

   532      SI field, only negated.  */

   533 #define NSI (39)

   534   { 16, 0, insert_nsi, extract_nsi,

   535       PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },

   536 

   537   /* The RA field in an D, DS, X, XO, M, or MDS form instruction.  */

   538 #define RA (40)

   539 #define RA_MASK (0x1f << 16)

   540   { 5, 16, 0, 0, PPC_OPERAND_GPR },

   541 

   542   /* The RA field in a D or X form instruction which is an updating

   543      load, which means that the RA field may not be zero and may not

   544      equal the RT field.  */

   545 #define RAL (41)

   546   { 5, 16, insert_ral, 0, PPC_OPERAND_GPR },

   547 

   548   /* The RA field in an lmw instruction, which has special value

   549      restrictions.  */

   550 #define RAM (42)

   551   { 5, 16, insert_ram, 0, PPC_OPERAND_GPR },

   552 

   553   /* The RA field in a D or X form instruction which is an updating

   554      store or an updating floating point load, which means that the RA

   555      field may not be zero.  */

   556 #define RAS (43)

   557   { 5, 16, insert_ras, 0, PPC_OPERAND_GPR },

   558 

   559   /* The RB field in an X, XO, M, or MDS form instruction.  */

   560 #define RB (44)

   561 #define RB_MASK (0x1f << 11)

   562   { 5, 11, 0, 0, PPC_OPERAND_GPR },

   563 

   564   /* The RB field in an X form instruction when it must be the same as

   565      the RS field in the instruction.  This is used for extended

   566      mnemonics like mr.  */

   567 #define RBS (45)

   568   { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },

   569 

   570   /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form

   571      instruction or the RT field in a D, DS, X, XFX or XO form

   572      instruction.  */

   573 #define RS (46)

   574 #define RT (RS)

   575 #define RT_MASK (0x1f << 21)

   576   { 5, 21, 0, 0, PPC_OPERAND_GPR },

   577 

   578   /* The SH field in an X or M form instruction.  */

   579 #define SH (47)

   580 #define SH_MASK (0x1f << 11)

   581   { 5, 11, 0, 0, 0 },

   582 

   583   /* The SH field in an MD form instruction.  This is split.  */

   584 #define SH6 (48)

   585 #define SH6_MASK ((0x1f << 11) | (1 << 1))

   586   { 6, 1, insert_sh6, extract_sh6, 0 },

   587 

   588   /* The SI field in a D form instruction.  */

   589 #define SI (49)

   590   { 16, 0, 0, 0, PPC_OPERAND_SIGNED },

   591 

   592   /* The SI field in a D form instruction when we accept a wide range

   593      of positive values.  */

   594 #define SISIGNOPT (50)

   595   { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },

   596 

   597   /* The SPR field in an XFX form instruction.  This is flipped--the

   598      lower 5 bits are stored in the upper 5 and vice- versa.  */

   599 #define SPR (51)

   600 #define SPR_MASK (0x3ff << 11)

   601   { 10, 11, insert_spr, extract_spr, 0 },

   602 

   603   /* The BAT index number in an XFX form m[ft]ibat[lu] instruction.  */

   604 #define SPRBAT (52)

   605 #define SPRBAT_MASK (0x3 << 17)

   606   { 2, 17, 0, 0, 0 },

   607 

   608   /* The SPRG register number in an XFX form m[ft]sprg instruction.  */

   609 #define SPRG (53)

   610 #define SPRG_MASK (0x3 << 16)

   611   { 2, 16, 0, 0, 0 },

   612 

   613   /* The SR field in an X form instruction.  */

   614 #define SR (54)

   615   { 4, 16, 0, 0, 0 },

   616 

   617   /* The SV field in a POWER SC form instruction.  */

   618 #define SV (55)

   619   { 14, 2, 0, 0, 0 },

   620 

   621   /* The TBR field in an XFX form instruction.  This is like the SPR

   622      field, but it is optional.  */

   623 #define TBR (56)

   624   { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },

   625 

   626   /* The TO field in a D or X form instruction.  */

   627 #define TO (57)

   628 #define TO_MASK (0x1f << 21)

   629   { 5, 21, 0, 0, 0 },

   630 

   631   /* The U field in an X form instruction.  */

   632 #define U (58)

   633   { 4, 12, 0, 0, 0 },

   634 

   635   /* The UI field in a D form instruction.  */

   636 #define UI (59)

   637   { 16, 0, 0, 0, 0 },

   638 };

   639 

   640 /* The functions used to insert and extract complicated operands.  */

   641 

   642 /* The BA field in an XL form instruction when it must be the same as

   643    the BT field in the same instruction.  This operand is marked FAKE.

   644    The insertion function just copies the BT field into the BA field,

   645    and the extraction function just checks that the fields are the

   646    same.  */

   647 

   648 /*ARGSUSED*/

   649 static unsigned long

   650 insert_bat (insn, value, errmsg)

   651      uint32_t insn;

   652      int32_t value;

   653      const char **errmsg;

   654 {

   655   return insn | (((insn >> 21) & 0x1f) << 16);

   656 }

   657 

   658 static long

   659 extract_bat (insn, invalid)

   660      uint32_t insn;

   661      int *invalid;

   662 {

   663   if (invalid != (int *) NULL

   664       && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))

   665     *invalid = 1;

   666   return 0;

   667 }

   668 

   669 /* The BB field in an XL form instruction when it must be the same as

   670    the BA field in the same instruction.  This operand is marked FAKE.

   671    The insertion function just copies the BA field into the BB field,

   672    and the extraction function just checks that the fields are the

   673    same.  */

   674 

   675 /*ARGSUSED*/

   676 static unsigned long

   677 insert_bba (insn, value, errmsg)

   678      uint32_t insn;

   679      int32_t value;

   680      const char **errmsg;

   681 {

   682   return insn | (((insn >> 16) & 0x1f) << 11);

   683 }

   684 

   685 static long

   686 extract_bba (insn, invalid)

   687      uint32_t insn;

   688      int *invalid;

   689 {

   690   if (invalid != (int *) NULL

   691       && ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))

   692     *invalid = 1;

   693   return 0;

   694 }

   695 

   696 /* The BD field in a B form instruction.  The lower two bits are

   697    forced to zero.  */

   698 

   699 /*ARGSUSED*/

   700 static unsigned long

   701 insert_bd (insn, value, errmsg)

   702      uint32_t insn;

   703      int32_t value;

   704      const char **errmsg;

   705 {

   706   return insn | (value & 0xfffc);

   707 }

   708 

   709 /*ARGSUSED*/

   710 static long

   711 extract_bd (insn, invalid)

   712      uint32_t insn;

   713      int *invalid;

   714 {

   715   if ((insn & 0x8000) != 0)

   716     return (insn & 0xfffc) - 0x10000;

   717   else

   718     return insn & 0xfffc;

   719 }

   720 

   721 /* The BD field in a B form instruction when the - modifier is used.

   722    This modifier means that the branch is not expected to be taken.

   723    We must set the y bit of the BO field to 1 if the offset is

   724    negative.  When extracting, we require that the y bit be 1 and that

   725    the offset be positive, since if the y bit is 0 we just want to

   726    print the normal form of the instruction.  */

   727 

   728 /*ARGSUSED*/

   729 static unsigned long

   730 insert_bdm (insn, value, errmsg)

   731      uint32_t insn;

   732      int32_t value;

   733      const char **errmsg;

   734 {

   735   if ((value & 0x8000) != 0)

   736     insn |= 1 << 21;

   737   return insn | (value & 0xfffc);

   738 }

   739 

   740 static long

   741 extract_bdm (insn, invalid)

   742      uint32_t insn;

   743      int *invalid;

   744 {

   745   if (invalid != (int *) NULL

   746       && ((insn & (1 << 21)) == 0

   747 	  || (insn & (1 << 15)) == 0))

   748     *invalid = 1;

   749   if ((insn & 0x8000) != 0)

   750     return (insn & 0xfffc) - 0x10000;

   751   else

   752     return insn & 0xfffc;

   753 }

   754 

   755 /* The BD field in a B form instruction when the + modifier is used.

   756    This is like BDM, above, except that the branch is expected to be

   757    taken.  */

   758 

   759 /*ARGSUSED*/

   760 static unsigned long

   761 insert_bdp (insn, value, errmsg)

   762      uint32_t insn;

   763      int32_t value;

   764      const char **errmsg;

   765 {

   766   if ((value & 0x8000) == 0)

   767     insn |= 1 << 21;

   768   return insn | (value & 0xfffc);

   769 }

   770 

   771 static long

   772 extract_bdp (insn, invalid)

   773      uint32_t insn;

   774      int *invalid;

   775 {

   776   if (invalid != (int *) NULL

   777       && ((insn & (1 << 21)) == 0

   778 	  || (insn & (1 << 15)) != 0))

   779     *invalid = 1;

   780   if ((insn & 0x8000) != 0)

   781     return (insn & 0xfffc) - 0x10000;

   782   else

   783     return insn & 0xfffc;

   784 }

   785 

   786 /* Check for legal values of a BO field.  */

   787 

   788 static int

   789 valid_bo (int32_t value)

   790 {

   791   /* Certain encodings have bits that are required to be zero.  These

   792      are (z must be zero, y may be anything):

   793          001zy

   794 	 011zy

   795 	 1z00y

   796 	 1z01y

   797 	 1z1zz

   798      */

   799   switch (value & 0x14)

   800     {

   801     default:

   802     case 0:

   803       return 1;

   804     case 0x4:

   805       return (value & 0x2) == 0;

   806     case 0x10:

   807       return (value & 0x8) == 0;

   808     case 0x14:

   809       return value == 0x14;

   810     }

   811 }

   812 

   813 /* The BO field in a B form instruction.  Warn about attempts to set

   814    the field to an illegal value.  */

   815 

   816 static unsigned long

   817 insert_bo (insn, value, errmsg)

   818      uint32_t insn;

   819      int32_t value;

   820      const char **errmsg;

   821 {

   822   if (errmsg != (const char **) NULL

   823       && ! valid_bo (value))

   824     *errmsg = "invalid conditional option";

   825   return insn | ((value & 0x1f) << 21);

   826 }

   827 

   828 static long

   829 extract_bo (insn, invalid)

   830      uint32_t insn;

   831      int *invalid;

   832 {

   833   int32_t value;

   834 

   835   value = (insn >> 21) & 0x1f;

   836   if (invalid != (int *) NULL

   837       && ! valid_bo (value))

   838     *invalid = 1;

   839   return value;

   840 }

   841 

   842 /* The BO field in a B form instruction when the + or - modifier is

   843    used.  This is like the BO field, but it must be even.  When

   844    extracting it, we force it to be even.  */

   845 

   846 static unsigned long

   847 insert_boe (insn, value, errmsg)

   848      uint32_t insn;

   849      int32_t value;

   850      const char **errmsg;

   851 {

   852   if (errmsg != (const char **) NULL)

   853     {

   854       if (! valid_bo (value))

   855 	*errmsg = "invalid conditional option";

   856       else if ((value & 1) != 0)

   857 	*errmsg = "attempt to set y bit when using + or - modifier";

   858     }

   859   return insn | ((value & 0x1f) << 21);

   860 }

   861 

   862 static long

   863 extract_boe (insn, invalid)

   864      uint32_t insn;

   865      int *invalid;

   866 {

   867   int32_t value;

   868 

   869   value = (insn >> 21) & 0x1f;

   870   if (invalid != (int *) NULL

   871       && ! valid_bo (value))

   872     *invalid = 1;

   873   return value & 0x1e;

   874 }

   875 

   876 /* The DS field in a DS form instruction.  This is like D, but the

   877    lower two bits are forced to zero.  */

   878 

   879 /*ARGSUSED*/

   880 static unsigned long

   881 insert_ds (insn, value, errmsg)

   882      uint32_t insn;

   883      int32_t value;

   884      const char **errmsg;

   885 {

   886   return insn | (value & 0xfffc);

   887 }

   888 

   889 /*ARGSUSED*/

   890 static long

   891 extract_ds (insn, invalid)

   892      uint32_t insn;

   893      int *invalid;

   894 {

   895   if ((insn & 0x8000) != 0)

   896     return (insn & 0xfffc) - 0x10000;

   897   else

   898     return insn & 0xfffc;

   899 }

   900 

   901 /* The LI field in an I form instruction.  The lower two bits are

   902    forced to zero.  */

   903 

   904 /*ARGSUSED*/

   905 static unsigned long

   906 insert_li (insn, value, errmsg)

   907      uint32_t insn;

   908      int32_t value;

   909      const char **errmsg;

   910 {

   911   return insn | (value & 0x3fffffc);

   912 }

   913 

   914 /*ARGSUSED*/

   915 static long

   916 extract_li (insn, invalid)

   917      uint32_t insn;

   918      int *invalid;

   919 {

   920   if ((insn & 0x2000000) != 0)

   921     return (insn & 0x3fffffc) - 0x4000000;

   922   else

   923     return insn & 0x3fffffc;

   924 }

   925 

   926 /* The MB and ME fields in an M form instruction expressed as a single

   927    operand which is itself a bitmask.  The extraction function always

   928    marks it as invalid, since we never want to recognize an

   929    instruction which uses a field of this type.  */

   930 

   931 static unsigned long

   932 insert_mbe (insn, value, errmsg)

   933      uint32_t insn;

   934      int32_t value;

   935      const char **errmsg;

   936 {

   937   uint32_t uval;

   938   int mb, me;

   939 

   940   uval = value;

   941 

   942   if (uval == 0)

   943     {

   944       if (errmsg != (const char **) NULL)

   945 	*errmsg = "illegal bitmask";

   946       return insn;

   947     }

   948 

   949   me = 31;

   950   while ((uval & 1) == 0)

   951     {

   952       uval >>= 1;

   953       --me;

   954     }

   955 

   956   mb = me;

   957   uval >>= 1;

   958   while ((uval & 1) != 0)

   959     {

   960       uval >>= 1;

   961       --mb;

   962     }

   963 

   964   if (uval != 0)

   965     {

   966       if (errmsg != (const char **) NULL)

   967 	*errmsg = "illegal bitmask";

   968     }

   969 

   970   return insn | (mb << 6) | (me << 1);

   971 }

   972 

   973 static long

   974 extract_mbe (insn, invalid)

   975      uint32_t insn;

   976      int *invalid;

   977 {

   978   long ret;

   979   int mb, me;

   980   int i;

   981 

   982   if (invalid != (int *) NULL)

   983     *invalid = 1;

   984 

   985   ret = 0;

   986   mb = (insn >> 6) & 0x1f;

   987   me = (insn >> 1) & 0x1f;

   988   for (i = mb; i < me; i++)

   989     ret |= 1 << (31 - i);

   990   return ret;

   991 }

   992 

   993 /* The MB or ME field in an MD or MDS form instruction.  The high bit

   994    is wrapped to the low end.  */

   995 

   996 /*ARGSUSED*/

   997 static unsigned long

   998 insert_mb6 (insn, value, errmsg)

   999      uint32_t insn;

  1000      int32_t value;

  1001      const char **errmsg;

  1002 {

  1003   return insn | ((value & 0x1f) << 6) | (value & 0x20);

  1004 }

  1005 

  1006 /*ARGSUSED*/

  1007 static long

  1008 extract_mb6 (insn, invalid)

  1009      uint32_t insn;

  1010      int *invalid;

  1011 {

  1012   return ((insn >> 6) & 0x1f) | (insn & 0x20);

  1013 }

  1014 

  1015 /* The NB field in an X form instruction.  The value 32 is stored as

  1016    0.  */

  1017 

  1018 static unsigned long

  1019 insert_nb (insn, value, errmsg)

  1020      uint32_t insn;

  1021      int32_t value;

  1022      const char **errmsg;

  1023 {

  1024   if (value < 0 || value > 32)

  1025     *errmsg = "value out of range";

  1026   if (value == 32)

  1027     value = 0;

  1028   return insn | ((value & 0x1f) << 11);

  1029 }

  1030 

  1031 /*ARGSUSED*/

  1032 static long

  1033 extract_nb (insn, invalid)

  1034      uint32_t insn;

  1035      int *invalid;

  1036 {

  1037   long ret;

  1038 

  1039   ret = (insn >> 11) & 0x1f;

  1040   if (ret == 0)

  1041     ret = 32;

  1042   return ret;

  1043 }

  1044 

  1045 /* The NSI field in a D form instruction.  This is the same as the SI

  1046    field, only negated.  The extraction function always marks it as

  1047    invalid, since we never want to recognize an instruction which uses

  1048    a field of this type.  */

  1049 

  1050 /*ARGSUSED*/

  1051 static unsigned long

  1052 insert_nsi (insn, value, errmsg)

  1053      uint32_t insn;

  1054      int32_t value;

  1055      const char **errmsg;

  1056 {

  1057   return insn | ((- value) & 0xffff);

  1058 }

  1059 

  1060 static long

  1061 extract_nsi (insn, invalid)

  1062      uint32_t insn;

  1063      int *invalid;

  1064 {

  1065   if (invalid != (int *) NULL)

  1066     *invalid = 1;

  1067   if ((insn & 0x8000) != 0)

  1068     return - ((insn & 0xffff) - 0x10000);

  1069   else

  1070     return - (insn & 0xffff);

  1071 }

  1072 

  1073 /* The RA field in a D or X form instruction which is an updating

  1074    load, which means that the RA field may not be zero and may not

  1075    equal the RT field.  */

  1076 

  1077 static unsigned long

  1078 insert_ral (insn, value, errmsg)

  1079      uint32_t insn;

  1080      int32_t value;

  1081      const char **errmsg;

  1082 {

  1083   if (value == 0

  1084       || value == ((insn >> 21) & 0x1f))

  1085     *errmsg = "invalid register operand when updating";

  1086   return insn | ((value & 0x1f) << 16);

  1087 }

  1088 

  1089 /* The RA field in an lmw instruction, which has special value

  1090    restrictions.  */

  1091 

  1092 static unsigned long

  1093 insert_ram (insn, value, errmsg)

  1094      uint32_t insn;

  1095      int32_t value;

  1096      const char **errmsg;

  1097 {

  1098   if (value >= ((insn >> 21) & 0x1f))

  1099     *errmsg = "index register in load range";

  1100   return insn | ((value & 0x1f) << 16);

  1101 }

  1102 

  1103 /* The RA field in a D or X form instruction which is an updating

  1104    store or an updating floating point load, which means that the RA

  1105    field may not be zero.  */

  1106 

  1107 static unsigned long

  1108 insert_ras (insn, value, errmsg)

  1109      uint32_t insn;

  1110      int32_t value;

  1111      const char **errmsg;

  1112 {

  1113   if (value == 0)

  1114     *errmsg = "invalid register operand when updating";

  1115   return insn | ((value & 0x1f) << 16);

  1116 }

  1117 

  1118 /* The RB field in an X form instruction when it must be the same as

  1119    the RS field in the instruction.  This is used for extended

  1120    mnemonics like mr.  This operand is marked FAKE.  The insertion

  1121    function just copies the BT field into the BA field, and the

  1122    extraction function just checks that the fields are the same.  */

  1123 

  1124 /*ARGSUSED*/

  1125 static unsigned long

  1126 insert_rbs (insn, value, errmsg)

  1127      uint32_t insn;

  1128      int32_t value;

  1129      const char **errmsg;

  1130 {

  1131   return insn | (((insn >> 21) & 0x1f) << 11);

  1132 }

  1133 

  1134 static long

  1135 extract_rbs (insn, invalid)