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1 /* |
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2 * ARM virtual CPU header |
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3 * |
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4 * Copyright (c) 2003 Fabrice Bellard |
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5 * |
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6 * This library is free software; you can redistribute it and/or |
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7 * modify it under the terms of the GNU Lesser General Public |
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8 * License as published by the Free Software Foundation; either |
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9 * version 2 of the License, or (at your option) any later version. |
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10 * |
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11 * This library is distributed in the hope that it will be useful, |
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12 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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14 * Lesser General Public License for more details. |
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15 * |
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16 * You should have received a copy of the GNU Lesser General Public |
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17 * License along with this library; if not, write to the Free Software |
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18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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19 */ |
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20 #ifndef CPU_ARM_H |
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21 #define CPU_ARM_H |
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22 |
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23 #define TARGET_LONG_BITS 32 |
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24 |
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25 #define ELF_MACHINE EM_ARM |
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26 |
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27 #include "cpu-defs.h" |
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28 |
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29 #include "softfloat.h" |
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30 |
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31 #define TARGET_HAS_ICE 1 |
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32 |
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33 #define EXCP_UDEF 1 /* undefined instruction */ |
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34 #define EXCP_SWI 2 /* software interrupt */ |
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35 #define EXCP_PREFETCH_ABORT 3 |
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36 #define EXCP_DATA_ABORT 4 |
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37 #define EXCP_IRQ 5 |
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38 #define EXCP_FIQ 6 |
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39 #define EXCP_BKPT 7 |
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40 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ |
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41 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ |
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42 |
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43 #define ARMV7M_EXCP_RESET 1 |
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44 #define ARMV7M_EXCP_NMI 2 |
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45 #define ARMV7M_EXCP_HARD 3 |
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46 #define ARMV7M_EXCP_MEM 4 |
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47 #define ARMV7M_EXCP_BUS 5 |
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48 #define ARMV7M_EXCP_USAGE 6 |
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49 #define ARMV7M_EXCP_SVC 11 |
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50 #define ARMV7M_EXCP_DEBUG 12 |
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51 #define ARMV7M_EXCP_PENDSV 14 |
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52 #define ARMV7M_EXCP_SYSTICK 15 |
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53 |
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54 typedef void ARMWriteCPFunc(void *opaque, int cp_info, |
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55 int srcreg, int operand, uint32_t value); |
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56 typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info, |
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57 int dstreg, int operand); |
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58 |
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59 struct arm_boot_info; |
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60 |
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61 #define NB_MMU_MODES 2 |
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62 |
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63 /* We currently assume float and double are IEEE single and double |
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64 precision respectively. |
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65 Doing runtime conversions is tricky because VFP registers may contain |
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66 integer values (eg. as the result of a FTOSI instruction). |
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67 s<2n> maps to the least significant half of d<n> |
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68 s<2n+1> maps to the most significant half of d<n> |
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69 */ |
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70 |
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71 typedef struct CPUARMState { |
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72 /* Regs for current mode. */ |
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73 uint32_t regs[16]; |
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74 /* Frequently accessed CPSR bits are stored separately for efficiently. |
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75 This contains all the other bits. Use cpsr_{read,write} to access |
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76 the whole CPSR. */ |
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77 uint32_t uncached_cpsr; |
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78 uint32_t spsr; |
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79 |
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80 /* Banked registers. */ |
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81 uint32_t banked_spsr[6]; |
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82 uint32_t banked_r13[6]; |
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83 uint32_t banked_r14[6]; |
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84 |
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85 /* These hold r8-r12. */ |
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86 uint32_t usr_regs[5]; |
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87 uint32_t fiq_regs[5]; |
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88 |
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89 /* cpsr flag cache for faster execution */ |
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90 uint32_t CF; /* 0 or 1 */ |
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91 uint32_t VF; /* V is the bit 31. All other bits are undefined */ |
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92 uint32_t NF; /* N is bit 31. All other bits are undefined. */ |
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93 uint32_t ZF; /* Z set if zero. */ |
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94 uint32_t QF; /* 0 or 1 */ |
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95 uint32_t GE; /* cpsr[19:16] */ |
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96 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ |
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97 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ |
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98 |
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99 /* System control coprocessor (cp15) */ |
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100 struct { |
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101 uint32_t c0_cpuid; |
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102 uint32_t c0_cachetype; |
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103 uint32_t c0_ccsid[16]; /* Cache size. */ |
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104 uint32_t c0_clid; /* Cache level. */ |
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105 uint32_t c0_cssel; /* Cache size selection. */ |
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106 uint32_t c0_c1[8]; /* Feature registers. */ |
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107 uint32_t c0_c2[8]; /* Instruction set registers. */ |
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108 uint32_t c1_sys; /* System control register. */ |
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109 uint32_t c1_coproc; /* Coprocessor access register. */ |
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110 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ |
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111 uint32_t c2_base0; /* MMU translation table base 0. */ |
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112 uint32_t c2_base1; /* MMU translation table base 1. */ |
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113 uint32_t c2_control; /* MMU translation table base control. */ |
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114 uint32_t c2_mask; /* MMU translation table base selection mask. */ |
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115 uint32_t c2_base_mask; /* MMU translation table base 0 mask. */ |
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116 uint32_t c2_data; /* MPU data cachable bits. */ |
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117 uint32_t c2_insn; /* MPU instruction cachable bits. */ |
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118 uint32_t c3; /* MMU domain access control register |
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119 MPU write buffer control. */ |
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120 uint32_t c5_insn; /* Fault status registers. */ |
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121 uint32_t c5_data; |
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122 uint32_t c6_region[8]; /* MPU base/size registers. */ |
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123 uint32_t c6_insn; /* Fault address registers. */ |
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124 uint32_t c6_data; |
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125 uint32_t c9_insn; /* Cache lockdown registers. */ |
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126 uint32_t c9_data; |
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127 uint32_t c12_vbar; /* Vector base address. */ |
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128 uint32_t c13_fcse; /* FCSE PID. */ |
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129 uint32_t c13_context; /* Context ID. */ |
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130 uint32_t c13_tls1; /* User RW Thread register. */ |
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131 uint32_t c13_tls2; /* User RO Thread register. */ |
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132 uint32_t c13_tls3; /* Privileged Thread register. */ |
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133 uint32_t c15_cpar; /* XScale Coprocessor Access Register */ |
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134 uint32_t c15_ticonfig; /* TI925T configuration byte. */ |
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135 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ |
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136 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ |
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137 uint32_t c15_threadid; /* TI debugger thread-ID. */ |
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138 } cp15; |
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139 |
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140 struct { |
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141 uint32_t other_sp; |
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142 uint32_t vecbase; |
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143 uint32_t basepri; |
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144 uint32_t control; |
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145 int current_sp; |
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146 int exception; |
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147 int pending_exception; |
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148 void *nvic; |
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149 } v7m; |
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150 |
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151 /* Coprocessor IO used by peripherals */ |
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152 struct { |
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153 ARMReadCPFunc *cp_read; |
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154 ARMWriteCPFunc *cp_write; |
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155 void *opaque; |
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156 } cp[15]; |
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157 |
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158 /* Thumb-2 EE state. */ |
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159 uint32_t teecr; |
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160 uint32_t teehbr; |
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161 |
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162 /* Internal CPU feature flags. */ |
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163 uint32_t features; |
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164 |
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165 /* Callback for vectored interrupt controller. */ |
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166 int (*get_irq_vector)(struct CPUARMState *); |
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167 void *irq_opaque; |
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168 |
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169 /* VFP coprocessor state. */ |
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170 struct { |
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171 float64 regs[32]; |
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172 |
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173 uint32_t xregs[16]; |
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174 /* We store these fpcsr fields separately for convenience. */ |
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175 int vec_len; |
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176 int vec_stride; |
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177 |
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178 /* scratch space when Tn are not sufficient. */ |
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179 uint32_t scratch[8]; |
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180 |
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181 float_status fp_status; |
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182 } vfp; |
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183 #if defined(CONFIG_USER_ONLY) |
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184 struct mmon_state *mmon_entry; |
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185 #else |
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186 uint32_t mmon_addr; |
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187 #endif |
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188 |
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189 /* iwMMXt coprocessor state. */ |
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190 struct { |
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191 uint64_t regs[16]; |
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192 uint64_t val; |
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193 |
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194 uint32_t cregs[16]; |
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195 } iwmmxt; |
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196 |
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197 /* For mixed endian mode. */ |
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198 int bswap_code; |
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199 |
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200 #if defined(CONFIG_USER_ONLY) |
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201 /* For usermode syscall translation. */ |
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202 int eabi; |
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203 #endif |
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204 |
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205 CPU_COMMON |
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206 |
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207 /* These fields after the common ones so they are preserved on reset. */ |
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208 struct arm_boot_info *boot_info; |
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209 } CPUARMState; |
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210 |
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211 CPUARMState *cpu_arm_init(const char *cpu_model, void *dev); |
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212 void arm_cpu_reset_dev(CPUARMState *env); |
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213 void arm_translate_init(void); |
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214 int cpu_arm_exec(CPUARMState *s); |
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215 void cpu_arm_close(CPUARMState *s); |
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216 void do_interrupt(CPUARMState *); |
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217 void switch_mode(CPUARMState *, int); |
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218 uint32_t do_arm_semihosting(CPUARMState *env); |
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219 |
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220 /* you can call this signal handler from your SIGBUS and SIGSEGV |
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221 signal handlers to inform the virtual CPU of exceptions. non zero |
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222 is returned if the signal was handled by the virtual CPU. */ |
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223 int cpu_arm_signal_handler(int host_signum, void *pinfo, |
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224 void *puc); |
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225 |
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226 void cpu_lock(void); |
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227 void cpu_unlock(void); |
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228 static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls) |
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229 { |
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230 env->cp15.c13_tls2 = newtls; |
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231 } |
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232 |
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233 #define CPSR_M (0x1f) |
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234 #define CPSR_T (1 << 5) |
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235 #define CPSR_F (1 << 6) |
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236 #define CPSR_I (1 << 7) |
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237 #define CPSR_A (1 << 8) |
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238 #define CPSR_E (1 << 9) |
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239 #define CPSR_IT_2_7 (0xfc00) |
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240 #define CPSR_GE (0xf << 16) |
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241 #define CPSR_RESERVED (0xf << 20) |
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242 #define CPSR_J (1 << 24) |
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243 #define CPSR_IT_0_1 (3 << 25) |
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244 #define CPSR_Q (1 << 27) |
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245 #define CPSR_V (1 << 28) |
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246 #define CPSR_C (1 << 29) |
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247 #define CPSR_Z (1 << 30) |
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248 #define CPSR_N (1 << 31) |
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249 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) |
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250 |
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251 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) |
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252 #define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV) |
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253 /* Bits writable in user mode. */ |
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254 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE) |
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255 /* Execution state bits. MRS read as zero, MSR writes ignored. */ |
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256 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J) |
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257 |
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258 /* Return the current CPSR value. */ |
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259 uint32_t cpsr_read(CPUARMState *env); |
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260 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear. */ |
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261 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask); |
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262 |
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263 /* Return the current xPSR value. */ |
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264 static inline uint32_t xpsr_read(CPUARMState *env) |
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265 { |
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266 int ZF; |
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267 ZF = (env->ZF == 0); |
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268 return (env->NF & 0x80000000) | (ZF << 30) |
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269 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) |
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270 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) |
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271 | ((env->condexec_bits & 0xfc) << 8) |
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272 | env->v7m.exception; |
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273 } |
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274 |
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275 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */ |
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276 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) |
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277 { |
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278 if (mask & CPSR_NZCV) { |
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279 env->ZF = (~val) & CPSR_Z; |
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280 env->NF = val; |
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281 env->CF = (val >> 29) & 1; |
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282 env->VF = (val << 3) & 0x80000000; |
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283 } |
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284 if (mask & CPSR_Q) |
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285 env->QF = ((val & CPSR_Q) != 0); |
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286 if (mask & (1 << 24)) |
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287 env->thumb = ((val & (1 << 24)) != 0); |
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288 if (mask & CPSR_IT_0_1) { |
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289 env->condexec_bits &= ~3; |
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290 env->condexec_bits |= (val >> 25) & 3; |
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291 } |
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292 if (mask & CPSR_IT_2_7) { |
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293 env->condexec_bits &= 3; |
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294 env->condexec_bits |= (val >> 8) & 0xfc; |
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295 } |
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296 if (mask & 0x1ff) { |
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297 env->v7m.exception = val & 0x1ff; |
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298 } |
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299 } |
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300 |
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301 enum arm_cpu_mode { |
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302 ARM_CPU_MODE_USR = 0x10, |
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303 ARM_CPU_MODE_FIQ = 0x11, |
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304 ARM_CPU_MODE_IRQ = 0x12, |
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305 ARM_CPU_MODE_SVC = 0x13, |
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306 ARM_CPU_MODE_ABT = 0x17, |
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307 ARM_CPU_MODE_UND = 0x1b, |
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308 ARM_CPU_MODE_SYS = 0x1f |
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309 }; |
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310 |
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311 /* VFP system registers. */ |
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312 #define ARM_VFP_FPSID 0 |
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313 #define ARM_VFP_FPSCR 1 |
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314 #define ARM_VFP_MVFR1 6 |
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315 #define ARM_VFP_MVFR0 7 |
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316 #define ARM_VFP_FPEXC 8 |
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317 #define ARM_VFP_FPINST 9 |
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318 #define ARM_VFP_FPINST2 10 |
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319 |
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320 /* iwMMXt coprocessor control registers. */ |
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321 #define ARM_IWMMXT_wCID 0 |
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322 #define ARM_IWMMXT_wCon 1 |
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323 #define ARM_IWMMXT_wCSSF 2 |
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324 #define ARM_IWMMXT_wCASF 3 |
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325 #define ARM_IWMMXT_wCGR0 8 |
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326 #define ARM_IWMMXT_wCGR1 9 |
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327 #define ARM_IWMMXT_wCGR2 10 |
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328 #define ARM_IWMMXT_wCGR3 11 |
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329 |
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330 enum arm_features { |
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331 ARM_FEATURE_VFP, |
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332 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ |
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333 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ |
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334 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ |
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335 ARM_FEATURE_V6, |
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336 ARM_FEATURE_V6K, |
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337 ARM_FEATURE_V7, |
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338 ARM_FEATURE_THUMB2, |
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339 ARM_FEATURE_MPU, /* Only has Memory Protection Unit, not full MMU. */ |
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340 ARM_FEATURE_VFP3, |
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341 ARM_FEATURE_NEON, |
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342 ARM_FEATURE_DIV, |
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343 ARM_FEATURE_M, /* Microcontroller profile. */ |
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344 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ |
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345 ARM_FEATURE_THUMB2EE, |
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346 ARM_FEATURE_FP16 |
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347 }; |
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348 |
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349 static inline int arm_feature(CPUARMState *env, int feature) |
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350 { |
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351 return (env->features & (1u << feature)) != 0; |
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352 } |
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353 |
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354 void arm_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); |
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355 |
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356 /* Interface between CPU and Interrupt controller. */ |
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357 void armv7m_nvic_set_pending(void *opaque, int irq); |
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358 int armv7m_nvic_acknowledge_irq(void *opaque); |
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359 void armv7m_nvic_complete_irq(void *opaque, int irq); |
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360 |
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361 void cpu_arm_set_cp_io(CPUARMState *env, int cpnum, |
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362 ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write, |
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363 void *opaque); |
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364 |
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365 /* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3. |
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366 Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are |
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367 conventional cores (ie. Application or Realtime profile). */ |
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368 |
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369 #define IS_M(env) arm_feature(env, ARM_FEATURE_M) |
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370 #define ARM_CPUID(env) (env->cp15.c0_cpuid) |
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371 |
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372 #define ARM_CPUID_ARM1026 0x4106a262 |
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373 #define ARM_CPUID_ARM926 0x41069265 |
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374 #define ARM_CPUID_ARM946 0x41059461 |
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375 #define ARM_CPUID_TI915T 0x54029152 |
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376 #define ARM_CPUID_TI925T 0x54029252 |
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377 #define ARM_CPUID_PXA250 0x69052100 |
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378 #define ARM_CPUID_PXA255 0x69052d00 |
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379 #define ARM_CPUID_PXA260 0x69052903 |
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380 #define ARM_CPUID_PXA261 0x69052d05 |
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381 #define ARM_CPUID_PXA262 0x69052d06 |
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382 #define ARM_CPUID_PXA270 0x69054110 |
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383 #define ARM_CPUID_PXA270_A0 0x69054110 |
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384 #define ARM_CPUID_PXA270_A1 0x69054111 |
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385 #define ARM_CPUID_PXA270_B0 0x69054112 |
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386 #define ARM_CPUID_PXA270_B1 0x69054113 |
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387 #define ARM_CPUID_PXA270_C0 0x69054114 |
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388 #define ARM_CPUID_PXA270_C5 0x69054117 |
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389 #define ARM_CPUID_ARM1136 0x4117b363 |
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390 #define ARM_CPUID_ARM1136_R2 0x4107b362 |
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391 #define ARM_CPUID_ARM11MPCORE 0x410fb022 |
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392 #define ARM_CPUID_CORTEXA8 0x410fc080 |
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393 #define ARM_CPUID_CORTEXM3 0x410fc231 |
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394 #define ARM_CPUID_ANY 0xffffffff |
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395 |
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396 #if defined(CONFIG_USER_ONLY) |
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397 #define TARGET_PAGE_BITS 12 |
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398 #else |
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399 /* The ARM MMU allows 1k pages. */ |
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400 /* ??? Linux doesn't actually use these, and they're deprecated in recent |
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401 architecture revisions. Maybe a configure option to disable them. */ |
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402 #define TARGET_PAGE_BITS 10 |
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403 #endif |
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404 |
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405 #define CPUState CPUARMState |
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406 #define cpu_init(env) cpu_arm_init(env, NULL) |
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407 #define cpu_exec cpu_arm_exec |
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408 #define cpu_gen_code cpu_arm_gen_code |
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409 #define cpu_signal_handler cpu_arm_signal_handler |
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410 #define cpu_list arm_cpu_list |
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411 |
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412 #define CPU_SAVE_VERSION 1 |
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413 |
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414 /* MMU modes definitions */ |
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415 #define MMU_MODE0_SUFFIX _kernel |
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416 #define MMU_MODE1_SUFFIX _user |
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417 #define MMU_USER_IDX 1 |
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418 static inline int cpu_mmu_index (CPUState *env) |
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419 { |
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420 return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0; |
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421 } |
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422 |
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423 #if defined(CONFIG_USER_ONLY) |
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424 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) |
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425 { |
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426 if (newsp) |
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427 env->regs[13] = newsp; |
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428 env->regs[0] = 0; |
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429 } |
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430 #endif |
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431 |
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432 #include "cpu-all.h" |
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433 #include "exec-all.h" |
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434 |
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435 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) |
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436 { |
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437 env->regs[15] = tb->pc; |
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438 } |
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439 |
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440 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, |
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441 target_ulong *cs_base, int *flags) |
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442 { |
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443 *pc = env->regs[15]; |
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444 *cs_base = 0; |
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445 *flags = env->thumb | (env->vfp.vec_len << 1) |
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446 | (env->vfp.vec_stride << 4) | (env->condexec_bits << 8); |
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447 if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) |
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448 *flags |= (1 << 6); |
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449 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) |
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450 *flags |= (1 << 7); |
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451 } |
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452 |
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453 #endif |