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1 /* |
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2 * CRIS mmu emulation. |
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3 * |
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4 * Copyright (c) 2007 AXIS Communications AB |
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5 * Written by Edgar E. Iglesias. |
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6 * |
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7 * This library is free software; you can redistribute it and/or |
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8 * modify it under the terms of the GNU Lesser General Public |
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9 * License as published by the Free Software Foundation; either |
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10 * version 2 of the License, or (at your option) any later version. |
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11 * |
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12 * This library is distributed in the hope that it will be useful, |
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13 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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15 * Lesser General Public License for more details. |
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16 * |
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17 * You should have received a copy of the GNU Lesser General Public |
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18 * License along with this library; if not, write to the Free Software |
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19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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20 */ |
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21 |
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22 #ifndef CONFIG_USER_ONLY |
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23 |
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24 #include <stdio.h> |
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25 #include <string.h> |
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26 #include <stdlib.h> |
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27 |
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28 #include "config.h" |
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29 #include "cpu.h" |
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30 #include "mmu.h" |
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31 #include "exec-all.h" |
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32 |
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33 #ifdef DEBUG |
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34 #define D(x) x |
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35 #else |
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36 #define D(x) |
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37 #endif |
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38 |
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39 void cris_mmu_init(CPUState *env) |
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40 { |
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41 env->mmu_rand_lfsr = 0xcccc; |
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42 } |
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43 |
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44 #define SR_POLYNOM 0x8805 |
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45 static inline unsigned int compute_polynom(unsigned int sr) |
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46 { |
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47 unsigned int i; |
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48 unsigned int f; |
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49 |
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50 f = 0; |
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51 for (i = 0; i < 16; i++) |
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52 f += ((SR_POLYNOM >> i) & 1) & ((sr >> i) & 1); |
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53 |
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54 return f; |
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55 } |
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56 |
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57 static inline int cris_mmu_enabled(uint32_t rw_gc_cfg) |
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58 { |
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59 return (rw_gc_cfg & 12) != 0; |
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60 } |
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61 |
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62 static inline int cris_mmu_segmented_addr(int seg, uint32_t rw_mm_cfg) |
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63 { |
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64 return (1 << seg) & rw_mm_cfg; |
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65 } |
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66 |
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67 static uint32_t cris_mmu_translate_seg(CPUState *env, int seg) |
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68 { |
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69 uint32_t base; |
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70 int i; |
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71 |
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72 if (seg < 8) |
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73 base = env->sregs[SFR_RW_MM_KBASE_LO]; |
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74 else |
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75 base = env->sregs[SFR_RW_MM_KBASE_HI]; |
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76 |
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77 i = seg & 7; |
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78 base >>= i * 4; |
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79 base &= 15; |
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80 |
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81 base <<= 28; |
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82 return base; |
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83 } |
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84 /* Used by the tlb decoder. */ |
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85 #define EXTRACT_FIELD(src, start, end) \ |
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86 (((src) >> start) & ((1 << (end - start + 1)) - 1)) |
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87 |
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88 static inline void set_field(uint32_t *dst, unsigned int val, |
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89 unsigned int offset, unsigned int width) |
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90 { |
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91 uint32_t mask; |
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92 |
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93 mask = (1 << width) - 1; |
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94 mask <<= offset; |
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95 val <<= offset; |
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96 |
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97 val &= mask; |
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98 *dst &= ~(mask); |
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99 *dst |= val; |
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100 } |
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101 |
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102 #ifdef DEBUG |
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103 static void dump_tlb(CPUState *env, int mmu) |
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104 { |
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105 int set; |
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106 int idx; |
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107 uint32_t hi, lo, tlb_vpn, tlb_pfn; |
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108 |
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109 for (set = 0; set < 4; set++) { |
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110 for (idx = 0; idx < 16; idx++) { |
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111 lo = env->tlbsets[mmu][set][idx].lo; |
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112 hi = env->tlbsets[mmu][set][idx].hi; |
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113 tlb_vpn = EXTRACT_FIELD(hi, 13, 31); |
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114 tlb_pfn = EXTRACT_FIELD(lo, 13, 31); |
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115 |
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116 printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n", |
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117 set, idx, hi, lo, tlb_vpn, tlb_pfn); |
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118 } |
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119 } |
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120 } |
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121 #endif |
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122 |
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123 /* rw 0 = read, 1 = write, 2 = exec. */ |
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124 static int cris_mmu_translate_page(struct cris_mmu_result_t *res, |
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125 CPUState *env, uint32_t vaddr, |
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126 int rw, int usermode) |
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127 { |
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128 unsigned int vpage; |
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129 unsigned int idx; |
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130 uint32_t pid, lo, hi; |
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131 uint32_t tlb_vpn, tlb_pfn = 0; |
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132 int tlb_pid, tlb_g, tlb_v, tlb_k, tlb_w, tlb_x; |
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133 int cfg_v, cfg_k, cfg_w, cfg_x; |
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134 int set, match = 0; |
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135 uint32_t r_cause; |
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136 uint32_t r_cfg; |
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137 int rwcause; |
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138 int mmu = 1; /* Data mmu is default. */ |
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139 int vect_base; |
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140 |
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141 r_cause = env->sregs[SFR_R_MM_CAUSE]; |
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142 r_cfg = env->sregs[SFR_RW_MM_CFG]; |
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143 pid = env->pregs[PR_PID] & 0xff; |
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144 |
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145 switch (rw) { |
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146 case 2: rwcause = CRIS_MMU_ERR_EXEC; mmu = 0; break; |
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147 case 1: rwcause = CRIS_MMU_ERR_WRITE; break; |
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148 default: |
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149 case 0: rwcause = CRIS_MMU_ERR_READ; break; |
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150 } |
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151 |
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152 /* I exception vectors 4 - 7, D 8 - 11. */ |
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153 vect_base = (mmu + 1) * 4; |
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154 |
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155 vpage = vaddr >> 13; |
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156 |
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157 /* We know the index which to check on each set. |
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158 Scan both I and D. */ |
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159 #if 0 |
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160 for (set = 0; set < 4; set++) { |
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161 for (idx = 0; idx < 16; idx++) { |
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162 lo = env->tlbsets[mmu][set][idx].lo; |
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163 hi = env->tlbsets[mmu][set][idx].hi; |
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164 tlb_vpn = EXTRACT_FIELD(hi, 13, 31); |
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165 tlb_pfn = EXTRACT_FIELD(lo, 13, 31); |
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166 |
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167 printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n", |
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168 set, idx, hi, lo, tlb_vpn, tlb_pfn); |
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169 } |
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170 } |
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171 #endif |
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172 |
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173 idx = vpage & 15; |
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174 for (set = 0; set < 4; set++) |
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175 { |
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176 lo = env->tlbsets[mmu][set][idx].lo; |
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177 hi = env->tlbsets[mmu][set][idx].hi; |
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178 |
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179 tlb_vpn = hi >> 13; |
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180 tlb_pid = EXTRACT_FIELD(hi, 0, 7); |
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181 tlb_g = EXTRACT_FIELD(lo, 4, 4); |
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182 |
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183 D(fprintf(logfile, |
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184 "TLB[%d][%d][%d] v=%x vpage=%x lo=%x hi=%x\n", |
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185 mmu, set, idx, tlb_vpn, vpage, lo, hi)); |
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186 if ((tlb_g || (tlb_pid == pid)) |
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187 && tlb_vpn == vpage) { |
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188 match = 1; |
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189 break; |
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190 } |
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191 } |
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192 |
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193 res->bf_vec = vect_base; |
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194 if (match) { |
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195 cfg_w = EXTRACT_FIELD(r_cfg, 19, 19); |
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196 cfg_k = EXTRACT_FIELD(r_cfg, 18, 18); |
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197 cfg_x = EXTRACT_FIELD(r_cfg, 17, 17); |
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198 cfg_v = EXTRACT_FIELD(r_cfg, 16, 16); |
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199 |
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200 tlb_pfn = EXTRACT_FIELD(lo, 13, 31); |
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201 tlb_v = EXTRACT_FIELD(lo, 3, 3); |
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202 tlb_k = EXTRACT_FIELD(lo, 2, 2); |
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203 tlb_w = EXTRACT_FIELD(lo, 1, 1); |
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204 tlb_x = EXTRACT_FIELD(lo, 0, 0); |
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205 |
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206 /* |
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207 set_exception_vector(0x04, i_mmu_refill); |
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208 set_exception_vector(0x05, i_mmu_invalid); |
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209 set_exception_vector(0x06, i_mmu_access); |
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210 set_exception_vector(0x07, i_mmu_execute); |
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211 set_exception_vector(0x08, d_mmu_refill); |
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212 set_exception_vector(0x09, d_mmu_invalid); |
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213 set_exception_vector(0x0a, d_mmu_access); |
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214 set_exception_vector(0x0b, d_mmu_write); |
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215 */ |
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216 if (cfg_k && tlb_k && usermode) { |
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217 D(printf ("tlb: kernel protected %x lo=%x pc=%x\n", |
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218 vaddr, lo, env->pc)); |
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219 match = 0; |
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220 res->bf_vec = vect_base + 2; |
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221 } else if (rw == 1 && cfg_w && !tlb_w) { |
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222 D(printf ("tlb: write protected %x lo=%x pc=%x\n", |
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223 vaddr, lo, env->pc)); |
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224 match = 0; |
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225 /* write accesses never go through the I mmu. */ |
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226 res->bf_vec = vect_base + 3; |
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227 } else if (rw == 2 && cfg_x && !tlb_x) { |
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228 D(printf ("tlb: exec protected %x lo=%x pc=%x\n", |
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229 vaddr, lo, env->pc)); |
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230 match = 0; |
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231 res->bf_vec = vect_base + 3; |
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232 } else if (cfg_v && !tlb_v) { |
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233 D(printf ("tlb: invalid %x\n", vaddr)); |
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234 match = 0; |
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235 res->bf_vec = vect_base + 1; |
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236 } |
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237 |
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238 res->prot = 0; |
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239 if (match) { |
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240 res->prot |= PAGE_READ; |
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241 if (tlb_w) |
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242 res->prot |= PAGE_WRITE; |
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243 if (tlb_x) |
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244 res->prot |= PAGE_EXEC; |
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245 } |
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246 else |
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247 D(dump_tlb(env, mmu)); |
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248 } else { |
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249 /* If refill, provide a randomized set. */ |
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250 set = env->mmu_rand_lfsr & 3; |
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251 } |
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252 |
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253 if (!match) { |
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254 unsigned int f; |
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255 |
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256 /* Update lfsr at every fault. */ |
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257 f = compute_polynom(env->mmu_rand_lfsr); |
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258 env->mmu_rand_lfsr >>= 1; |
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259 env->mmu_rand_lfsr |= (f << 15); |
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260 env->mmu_rand_lfsr &= 0xffff; |
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261 |
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262 /* Compute index. */ |
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263 idx = vpage & 15; |
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264 |
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265 /* Update RW_MM_TLB_SEL. */ |
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266 env->sregs[SFR_RW_MM_TLB_SEL] = 0; |
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267 set_field(&env->sregs[SFR_RW_MM_TLB_SEL], idx, 0, 4); |
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268 set_field(&env->sregs[SFR_RW_MM_TLB_SEL], set, 4, 2); |
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269 |
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270 /* Update RW_MM_CAUSE. */ |
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271 set_field(&r_cause, rwcause, 8, 2); |
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272 set_field(&r_cause, vpage, 13, 19); |
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273 set_field(&r_cause, pid, 0, 8); |
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274 env->sregs[SFR_R_MM_CAUSE] = r_cause; |
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275 D(printf("refill vaddr=%x pc=%x\n", vaddr, env->pc)); |
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276 } |
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277 |
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278 D(printf ("%s rw=%d mtch=%d pc=%x va=%x vpn=%x tlbvpn=%x pfn=%x pid=%x" |
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279 " %x cause=%x sel=%x sp=%x %x %x\n", |
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280 __func__, rw, match, env->pc, |
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281 vaddr, vpage, |
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282 tlb_vpn, tlb_pfn, tlb_pid, |
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283 pid, |
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284 r_cause, |
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285 env->sregs[SFR_RW_MM_TLB_SEL], |
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286 env->regs[R_SP], env->pregs[PR_USP], env->ksp)); |
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287 |
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288 res->pfn = tlb_pfn; |
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289 return !match; |
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290 } |
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291 |
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292 void cris_mmu_flush_pid(CPUState *env, uint32_t pid) |
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293 { |
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294 target_ulong vaddr; |
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295 unsigned int idx; |
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296 uint32_t lo, hi; |
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297 uint32_t tlb_vpn; |
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298 int tlb_pid, tlb_g, tlb_v, tlb_k; |
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299 unsigned int set; |
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300 unsigned int mmu; |
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301 |
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302 pid &= 0xff; |
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303 for (mmu = 0; mmu < 2; mmu++) { |
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304 for (set = 0; set < 4; set++) |
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305 { |
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306 for (idx = 0; idx < 16; idx++) { |
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307 lo = env->tlbsets[mmu][set][idx].lo; |
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308 hi = env->tlbsets[mmu][set][idx].hi; |
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309 |
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310 tlb_vpn = EXTRACT_FIELD(hi, 13, 31); |
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311 tlb_pid = EXTRACT_FIELD(hi, 0, 7); |
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312 tlb_g = EXTRACT_FIELD(lo, 4, 4); |
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313 tlb_v = EXTRACT_FIELD(lo, 3, 3); |
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314 tlb_k = EXTRACT_FIELD(lo, 2, 2); |
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315 |
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316 /* Kernel protected areas need to be flushed |
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317 as well. */ |
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318 if (tlb_v && !tlb_g && (tlb_pid == pid || tlb_k)) { |
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319 vaddr = tlb_vpn << TARGET_PAGE_BITS; |
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320 D(fprintf(logfile, |
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321 "flush pid=%x vaddr=%x\n", |
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322 pid, vaddr)); |
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323 tlb_flush_page(env, vaddr); |
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324 } |
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325 } |
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326 } |
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327 } |
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328 } |
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329 |
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330 int cris_mmu_translate(struct cris_mmu_result_t *res, |
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331 CPUState *env, uint32_t vaddr, |
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332 int rw, int mmu_idx) |
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333 { |
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334 uint32_t phy = vaddr; |
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335 int seg; |
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336 int miss = 0; |
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337 int is_user = mmu_idx == MMU_USER_IDX; |
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338 uint32_t old_srs; |
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339 |
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340 old_srs= env->pregs[PR_SRS]; |
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341 |
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342 /* rw == 2 means exec, map the access to the insn mmu. */ |
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343 env->pregs[PR_SRS] = rw == 2 ? 1 : 2; |
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344 |
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345 if (!cris_mmu_enabled(env->sregs[SFR_RW_GC_CFG])) { |
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346 res->phy = vaddr; |
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347 res->prot = PAGE_BITS; |
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348 goto done; |
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349 } |
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350 |
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351 seg = vaddr >> 28; |
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352 if (cris_mmu_segmented_addr(seg, env->sregs[SFR_RW_MM_CFG])) |
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353 { |
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354 uint32_t base; |
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355 |
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356 miss = 0; |
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357 base = cris_mmu_translate_seg(env, seg); |
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358 phy = base | (0x0fffffff & vaddr); |
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359 res->phy = phy; |
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360 res->prot = PAGE_BITS; |
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361 } |
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362 else |
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363 { |
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364 miss = cris_mmu_translate_page(res, env, vaddr, rw, is_user); |
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365 phy = (res->pfn << 13); |
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366 res->phy = phy; |
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367 } |
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368 done: |
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369 env->pregs[PR_SRS] = old_srs; |
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370 return miss; |
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371 } |
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372 #endif |