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1 /* cris.h -- Header file for CRIS opcode and register tables. |
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2 Copyright (C) 2000, 2001, 2004 Free Software Foundation, Inc. |
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3 Contributed by Axis Communications AB, Lund, Sweden. |
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4 Originally written for GAS 1.38.1 by Mikael Asker. |
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5 Updated, BFDized and GNUified by Hans-Peter Nilsson. |
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6 |
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7 This file is part of GAS, GDB and the GNU binutils. |
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8 |
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9 GAS, GDB, and GNU binutils is free software; you can redistribute it |
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10 and/or modify it under the terms of the GNU General Public License as |
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11 published by the Free Software Foundation; either version 2, or (at your |
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12 option) any later version. |
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13 |
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14 GAS, GDB, and GNU binutils are distributed in the hope that they will be |
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15 useful, but WITHOUT ANY WARRANTY; without even the implied warranty of |
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16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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17 GNU General Public License for more details. |
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18 |
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19 You should have received a copy of the GNU General Public License |
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20 along with this program; if not, write to the Free Software |
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21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ |
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22 |
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23 #ifndef __CRIS_H_INCLUDED_ |
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24 #define __CRIS_H_INCLUDED_ |
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25 |
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26 #if !defined(__STDC__) && !defined(const) |
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27 #define const |
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28 #endif |
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29 |
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30 |
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31 /* Registers. */ |
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32 #define MAX_REG (15) |
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33 #define REG_SP (14) |
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34 #define REG_PC (15) |
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35 |
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36 /* CPU version control of disassembly and assembly of instructions. |
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37 May affect how the instruction is assembled, at least the size of |
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38 immediate operands. */ |
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39 enum cris_insn_version_usage |
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40 { |
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41 /* Any version. */ |
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42 cris_ver_version_all=0, |
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43 |
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44 /* Indeterminate (intended for disassembly only, or obsolete). */ |
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45 cris_ver_warning, |
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46 |
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47 /* Only for v0..3 (Etrax 1..4). */ |
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48 cris_ver_v0_3, |
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49 |
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50 /* Only for v3 or higher (ETRAX 4 and beyond). */ |
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51 cris_ver_v3p, |
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52 |
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53 /* Only for v8 (Etrax 100). */ |
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54 cris_ver_v8, |
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55 |
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56 /* Only for v8 or higher (ETRAX 100, ETRAX 100 LX). */ |
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57 cris_ver_v8p, |
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58 |
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59 /* Only for v0..10. FIXME: Not sure what to do with this. */ |
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60 cris_ver_sim_v0_10, |
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61 |
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62 /* Only for v0..10. */ |
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63 cris_ver_v0_10, |
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64 |
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65 /* Only for v3..10. (ETRAX 4, ETRAX 100 and ETRAX 100 LX). */ |
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66 cris_ver_v3_10, |
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67 |
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68 /* Only for v8..10 (ETRAX 100 and ETRAX 100 LX). */ |
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69 cris_ver_v8_10, |
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70 |
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71 /* Only for v10 (ETRAX 100 LX) and same series. */ |
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72 cris_ver_v10, |
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73 |
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74 /* Only for v10 (ETRAX 100 LX) and same series. */ |
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75 cris_ver_v10p, |
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76 |
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77 /* Only for v32 or higher (codename GUINNESS). |
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78 Of course some or all these of may change to cris_ver_v32p if/when |
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79 there's a new revision. */ |
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80 cris_ver_v32p |
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81 }; |
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82 |
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83 |
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84 /* Special registers. */ |
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85 struct cris_spec_reg |
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86 { |
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87 const char *const name; |
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88 unsigned int number; |
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89 |
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90 /* The size of the register. */ |
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91 unsigned int reg_size; |
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92 |
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93 /* What CPU version the special register of that name is implemented |
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94 in. If cris_ver_warning, emit an unimplemented-warning. */ |
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95 enum cris_insn_version_usage applicable_version; |
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96 |
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97 /* There might be a specific warning for using a special register |
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98 here. */ |
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99 const char *const warning; |
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100 }; |
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101 extern const struct cris_spec_reg cris_spec_regs[]; |
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102 |
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103 |
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104 /* Support registers (kind of special too, but not named as such). */ |
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105 struct cris_support_reg |
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106 { |
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107 const char *const name; |
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108 unsigned int number; |
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109 }; |
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110 extern const struct cris_support_reg cris_support_regs[]; |
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111 |
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112 struct cris_cond15 |
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113 { |
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114 /* The name of the condition. */ |
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115 const char *const name; |
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116 |
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117 /* What CPU version this condition name applies to. */ |
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118 enum cris_insn_version_usage applicable_version; |
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119 }; |
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120 extern const struct cris_cond15 cris_conds15[]; |
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121 |
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122 /* Opcode-dependent constants. */ |
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123 #define AUTOINCR_BIT (0x04) |
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124 |
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125 /* Prefixes. */ |
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126 #define BDAP_QUICK_OPCODE (0x0100) |
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127 #define BDAP_QUICK_Z_BITS (0x0e00) |
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128 |
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129 #define BIAP_OPCODE (0x0540) |
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130 #define BIAP_Z_BITS (0x0a80) |
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131 |
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132 #define DIP_OPCODE (0x0970) |
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133 #define DIP_Z_BITS (0xf280) |
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134 |
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135 #define BDAP_INDIR_LOW (0x40) |
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136 #define BDAP_INDIR_LOW_Z (0x80) |
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137 #define BDAP_INDIR_HIGH (0x09) |
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138 #define BDAP_INDIR_HIGH_Z (0x02) |
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139 |
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140 #define BDAP_INDIR_OPCODE (BDAP_INDIR_HIGH * 0x0100 + BDAP_INDIR_LOW) |
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141 #define BDAP_INDIR_Z_BITS (BDAP_INDIR_HIGH_Z * 0x100 + BDAP_INDIR_LOW_Z) |
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142 #define BDAP_PC_LOW (BDAP_INDIR_LOW + REG_PC) |
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143 #define BDAP_INCR_HIGH (BDAP_INDIR_HIGH + AUTOINCR_BIT) |
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144 |
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145 /* No prefix must have this code for its "match" bits in the |
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146 opcode-table. "BCC .+2" will do nicely. */ |
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147 #define NO_CRIS_PREFIX 0 |
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148 |
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149 /* Definitions for condition codes. */ |
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150 #define CC_CC 0x0 |
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151 #define CC_HS 0x0 |
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152 #define CC_CS 0x1 |
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153 #define CC_LO 0x1 |
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154 #define CC_NE 0x2 |
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155 #define CC_EQ 0x3 |
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156 #define CC_VC 0x4 |
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157 #define CC_VS 0x5 |
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158 #define CC_PL 0x6 |
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159 #define CC_MI 0x7 |
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160 #define CC_LS 0x8 |
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161 #define CC_HI 0x9 |
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162 #define CC_GE 0xA |
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163 #define CC_LT 0xB |
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164 #define CC_GT 0xC |
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165 #define CC_LE 0xD |
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166 #define CC_A 0xE |
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167 #define CC_EXT 0xF |
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168 |
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169 /* A table of strings "cc", "cs"... indexed with condition code |
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170 values as above. */ |
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171 extern const char *const cris_cc_strings[]; |
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172 |
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173 /* Bcc quick. */ |
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174 #define BRANCH_QUICK_LOW (0) |
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175 #define BRANCH_QUICK_HIGH (0) |
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176 #define BRANCH_QUICK_OPCODE (BRANCH_QUICK_HIGH * 0x0100 + BRANCH_QUICK_LOW) |
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177 #define BRANCH_QUICK_Z_BITS (0x0F00) |
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178 |
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179 /* BA quick. */ |
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180 #define BA_QUICK_HIGH (BRANCH_QUICK_HIGH + CC_A * 0x10) |
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181 #define BA_QUICK_OPCODE (BA_QUICK_HIGH * 0x100 + BRANCH_QUICK_LOW) |
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182 |
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183 /* Bcc [PC+]. */ |
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184 #define BRANCH_PC_LOW (0xFF) |
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185 #define BRANCH_INCR_HIGH (0x0D) |
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186 #define BA_PC_INCR_OPCODE \ |
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187 ((BRANCH_INCR_HIGH + CC_A * 0x10) * 0x0100 + BRANCH_PC_LOW) |
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188 |
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189 /* Jump. */ |
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190 /* Note that old versions generated special register 8 (in high bits) |
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191 and not-that-old versions recognized it as a jump-instruction. |
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192 That opcode now belongs to JUMPU. */ |
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193 #define JUMP_INDIR_OPCODE (0x0930) |
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194 #define JUMP_INDIR_Z_BITS (0xf2c0) |
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195 #define JUMP_PC_INCR_OPCODE \ |
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196 (JUMP_INDIR_OPCODE + AUTOINCR_BIT * 0x0100 + REG_PC) |
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197 |
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198 #define MOVE_M_TO_PREG_OPCODE 0x0a30 |
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199 #define MOVE_M_TO_PREG_ZBITS 0x01c0 |
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200 |
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201 /* BDAP.D N,PC. */ |
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202 #define MOVE_PC_INCR_OPCODE_PREFIX \ |
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203 (((BDAP_INCR_HIGH | (REG_PC << 4)) << 8) | BDAP_PC_LOW | (2 << 4)) |
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204 #define MOVE_PC_INCR_OPCODE_SUFFIX \ |
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205 (MOVE_M_TO_PREG_OPCODE | REG_PC | (AUTOINCR_BIT << 8)) |
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206 |
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207 #define JUMP_PC_INCR_OPCODE_V32 (0x0DBF) |
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208 |
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209 /* BA DWORD (V32). */ |
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210 #define BA_DWORD_OPCODE (0x0EBF) |
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211 |
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212 /* Nop. */ |
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213 #define NOP_OPCODE (0x050F) |
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214 #define NOP_Z_BITS (0xFFFF ^ NOP_OPCODE) |
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215 |
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216 #define NOP_OPCODE_V32 (0x05B0) |
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217 #define NOP_Z_BITS_V32 (0xFFFF ^ NOP_OPCODE_V32) |
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218 |
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219 /* For the compatibility mode, let's use "MOVE R0,P0". Doesn't affect |
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220 registers or flags. Unfortunately shuts off interrupts for one cycle |
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221 for < v32, but there doesn't seem to be any alternative without that |
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222 effect. */ |
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223 #define NOP_OPCODE_COMMON (0x630) |
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224 #define NOP_OPCODE_ZBITS_COMMON (0xffff & ~NOP_OPCODE_COMMON) |
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225 |
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226 /* LAPC.D */ |
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227 #define LAPC_DWORD_OPCODE (0x0D7F) |
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228 #define LAPC_DWORD_Z_BITS (0x0fff & ~LAPC_DWORD_OPCODE) |
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229 |
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230 /* Structure of an opcode table entry. */ |
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231 enum cris_imm_oprnd_size_type |
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232 { |
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233 /* No size is applicable. */ |
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234 SIZE_NONE, |
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235 |
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236 /* Always 32 bits. */ |
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237 SIZE_FIX_32, |
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238 |
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239 /* Indicated by size of special register. */ |
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240 SIZE_SPEC_REG, |
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241 |
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242 /* Indicated by size field, signed. */ |
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243 SIZE_FIELD_SIGNED, |
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244 |
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245 /* Indicated by size field, unsigned. */ |
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246 SIZE_FIELD_UNSIGNED, |
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247 |
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248 /* Indicated by size field, no sign implied. */ |
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249 SIZE_FIELD |
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250 }; |
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251 |
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252 /* For GDB. FIXME: Is this the best way to handle opcode |
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253 interpretation? */ |
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254 enum cris_op_type |
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255 { |
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256 cris_not_implemented_op = 0, |
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257 cris_abs_op, |
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258 cris_addi_op, |
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259 cris_asr_op, |
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260 cris_asrq_op, |
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261 cris_ax_ei_setf_op, |
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262 cris_bdap_prefix, |
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263 cris_biap_prefix, |
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264 cris_break_op, |
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265 cris_btst_nop_op, |
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266 cris_clearf_di_op, |
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267 cris_dip_prefix, |
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268 cris_dstep_logshift_mstep_neg_not_op, |
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269 cris_eight_bit_offset_branch_op, |
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270 cris_move_mem_to_reg_movem_op, |
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271 cris_move_reg_to_mem_movem_op, |
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272 cris_move_to_preg_op, |
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273 cris_muls_op, |
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274 cris_mulu_op, |
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275 cris_none_reg_mode_add_sub_cmp_and_or_move_op, |
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276 cris_none_reg_mode_clear_test_op, |
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277 cris_none_reg_mode_jump_op, |
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278 cris_none_reg_mode_move_from_preg_op, |
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279 cris_quick_mode_add_sub_op, |
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280 cris_quick_mode_and_cmp_move_or_op, |
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281 cris_quick_mode_bdap_prefix, |
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282 cris_reg_mode_add_sub_cmp_and_or_move_op, |
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283 cris_reg_mode_clear_op, |
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284 cris_reg_mode_jump_op, |
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285 cris_reg_mode_move_from_preg_op, |
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286 cris_reg_mode_test_op, |
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287 cris_scc_op, |
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288 cris_sixteen_bit_offset_branch_op, |
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289 cris_three_operand_add_sub_cmp_and_or_op, |
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290 cris_three_operand_bound_op, |
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291 cris_two_operand_bound_op, |
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292 cris_xor_op |
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293 }; |
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294 |
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295 struct cris_opcode |
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296 { |
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297 /* The name of the insn. */ |
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298 const char *name; |
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299 |
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300 /* Bits that must be 1 for a match. */ |
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301 unsigned int match; |
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302 |
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303 /* Bits that must be 0 for a match. */ |
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304 unsigned int lose; |
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305 |
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306 /* See the table in "opcodes/cris-opc.c". */ |
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307 const char *args; |
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308 |
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309 /* Nonzero if this is a delayed branch instruction. */ |
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310 char delayed; |
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311 |
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312 /* Size of immediate operands. */ |
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313 enum cris_imm_oprnd_size_type imm_oprnd_size; |
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314 |
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315 /* Indicates which version this insn was first implemented in. */ |
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316 enum cris_insn_version_usage applicable_version; |
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317 |
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318 /* What kind of operation this is. */ |
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319 enum cris_op_type op; |
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320 }; |
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321 extern const struct cris_opcode cris_opcodes[]; |
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322 |
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323 |
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324 /* These macros are for the target-specific flags in disassemble_info |
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325 used at disassembly. */ |
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326 |
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327 /* This insn accesses memory. This flag is more trustworthy than |
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328 checking insn_type for "dis_dref" which does not work for |
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329 e.g. "JSR [foo]". */ |
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330 #define CRIS_DIS_FLAG_MEMREF (1 << 0) |
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331 |
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332 /* The "target" field holds a register number. */ |
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333 #define CRIS_DIS_FLAG_MEM_TARGET_IS_REG (1 << 1) |
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334 |
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335 /* The "target2" field holds a register number; add it to "target". */ |
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336 #define CRIS_DIS_FLAG_MEM_TARGET2_IS_REG (1 << 2) |
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337 |
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338 /* Yet another add-on: the register in "target2" must be multiplied |
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339 by 2 before adding to "target". */ |
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340 #define CRIS_DIS_FLAG_MEM_TARGET2_MULT2 (1 << 3) |
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341 |
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342 /* Yet another add-on: the register in "target2" must be multiplied |
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343 by 4 (mutually exclusive with .._MULT2). */ |
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344 #define CRIS_DIS_FLAG_MEM_TARGET2_MULT4 (1 << 4) |
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345 |
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346 /* The register in "target2" is an indirect memory reference (of the |
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347 register there), add to "target". Assumed size is dword (mutually |
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348 exclusive with .._MULT[24]). */ |
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349 #define CRIS_DIS_FLAG_MEM_TARGET2_MEM (1 << 5) |
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350 |
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351 /* Add-on to CRIS_DIS_FLAG_MEM_TARGET2_MEM; the memory access is "byte"; |
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352 sign-extended before adding to "target". */ |
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353 #define CRIS_DIS_FLAG_MEM_TARGET2_MEM_BYTE (1 << 6) |
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354 |
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355 /* Add-on to CRIS_DIS_FLAG_MEM_TARGET2_MEM; the memory access is "word"; |
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356 sign-extended before adding to "target". */ |
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357 #define CRIS_DIS_FLAG_MEM_TARGET2_MEM_WORD (1 << 7) |
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358 |
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359 #endif /* __CRIS_H_INCLUDED_ */ |
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360 |
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361 /* |
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362 * Local variables: |
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363 * eval: (c-set-style "gnu") |
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364 * indent-tabs-mode: t |
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365 * End: |
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366 */ |