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1 #include "hw/hw.h" |
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2 #include "hw/boards.h" |
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3 |
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4 #include "exec-all.h" |
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5 |
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6 void register_machines(void) |
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7 { |
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8 qemu_register_machine(&mips_malta_machine); |
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9 qemu_register_machine(&mips_magnum_machine); |
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10 qemu_register_machine(&mips_pica61_machine); |
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11 qemu_register_machine(&mips_mipssim_machine); |
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12 qemu_register_machine(&mips_machine); |
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13 } |
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14 |
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15 static void save_tc(QEMUFile *f, TCState *tc) |
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16 { |
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17 int i; |
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18 |
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19 /* Save active TC */ |
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20 for(i = 0; i < 32; i++) |
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21 qemu_put_betls(f, &tc->gpr[i]); |
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22 qemu_put_betls(f, &tc->PC); |
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23 for(i = 0; i < MIPS_DSP_ACC; i++) |
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24 qemu_put_betls(f, &tc->HI[i]); |
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25 for(i = 0; i < MIPS_DSP_ACC; i++) |
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26 qemu_put_betls(f, &tc->LO[i]); |
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27 for(i = 0; i < MIPS_DSP_ACC; i++) |
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28 qemu_put_betls(f, &tc->ACX[i]); |
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29 qemu_put_betls(f, &tc->DSPControl); |
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30 qemu_put_sbe32s(f, &tc->CP0_TCStatus); |
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31 qemu_put_sbe32s(f, &tc->CP0_TCBind); |
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32 qemu_put_betls(f, &tc->CP0_TCHalt); |
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33 qemu_put_betls(f, &tc->CP0_TCContext); |
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34 qemu_put_betls(f, &tc->CP0_TCSchedule); |
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35 qemu_put_betls(f, &tc->CP0_TCScheFBack); |
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36 qemu_put_sbe32s(f, &tc->CP0_Debug_tcstatus); |
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37 } |
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38 |
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39 static void save_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu) |
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40 { |
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41 int i; |
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42 |
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43 for(i = 0; i < 32; i++) |
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44 qemu_put_be64s(f, &fpu->fpr[i].d); |
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45 qemu_put_s8s(f, &fpu->fp_status.float_detect_tininess); |
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46 qemu_put_s8s(f, &fpu->fp_status.float_rounding_mode); |
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47 qemu_put_s8s(f, &fpu->fp_status.float_exception_flags); |
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48 qemu_put_be32s(f, &fpu->fcr0); |
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49 qemu_put_be32s(f, &fpu->fcr31); |
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50 } |
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51 |
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52 void cpu_save(QEMUFile *f, void *opaque) |
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53 { |
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54 CPUState *env = opaque; |
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55 int i; |
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56 |
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57 /* Save active TC */ |
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58 save_tc(f, &env->active_tc); |
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59 |
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60 /* Save active FPU */ |
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61 save_fpu(f, &env->active_fpu); |
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62 |
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63 /* Save MVP */ |
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64 qemu_put_sbe32s(f, &env->mvp->CP0_MVPControl); |
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65 qemu_put_sbe32s(f, &env->mvp->CP0_MVPConf0); |
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66 qemu_put_sbe32s(f, &env->mvp->CP0_MVPConf1); |
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67 |
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68 /* Save TLB */ |
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69 qemu_put_be32s(f, &env->tlb->nb_tlb); |
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70 qemu_put_be32s(f, &env->tlb->tlb_in_use); |
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71 for(i = 0; i < MIPS_TLB_MAX; i++) { |
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72 uint16_t flags = ((env->tlb->mmu.r4k.tlb[i].G << 10) | |
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73 (env->tlb->mmu.r4k.tlb[i].C0 << 7) | |
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74 (env->tlb->mmu.r4k.tlb[i].C1 << 4) | |
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75 (env->tlb->mmu.r4k.tlb[i].V0 << 3) | |
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76 (env->tlb->mmu.r4k.tlb[i].V1 << 2) | |
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77 (env->tlb->mmu.r4k.tlb[i].D0 << 1) | |
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78 (env->tlb->mmu.r4k.tlb[i].D1 << 0)); |
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79 |
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80 qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].VPN); |
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81 qemu_put_be32s(f, &env->tlb->mmu.r4k.tlb[i].PageMask); |
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82 qemu_put_8s(f, &env->tlb->mmu.r4k.tlb[i].ASID); |
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83 qemu_put_be16s(f, &flags); |
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84 qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[0]); |
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85 qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[1]); |
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86 } |
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87 |
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88 /* Save CPU metastate */ |
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89 qemu_put_be32s(f, &env->current_tc); |
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90 qemu_put_be32s(f, &env->current_fpu); |
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91 qemu_put_sbe32s(f, &env->error_code); |
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92 qemu_put_be32s(f, &env->hflags); |
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93 qemu_put_betls(f, &env->btarget); |
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94 qemu_put_sbe32s(f, &env->bcond); |
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95 |
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96 /* Save remaining CP1 registers */ |
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97 qemu_put_sbe32s(f, &env->CP0_Index); |
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98 qemu_put_sbe32s(f, &env->CP0_Random); |
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99 qemu_put_sbe32s(f, &env->CP0_VPEControl); |
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100 qemu_put_sbe32s(f, &env->CP0_VPEConf0); |
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101 qemu_put_sbe32s(f, &env->CP0_VPEConf1); |
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102 qemu_put_betls(f, &env->CP0_YQMask); |
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103 qemu_put_betls(f, &env->CP0_VPESchedule); |
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104 qemu_put_betls(f, &env->CP0_VPEScheFBack); |
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105 qemu_put_sbe32s(f, &env->CP0_VPEOpt); |
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106 qemu_put_betls(f, &env->CP0_EntryLo0); |
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107 qemu_put_betls(f, &env->CP0_EntryLo1); |
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108 qemu_put_betls(f, &env->CP0_Context); |
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109 qemu_put_sbe32s(f, &env->CP0_PageMask); |
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110 qemu_put_sbe32s(f, &env->CP0_PageGrain); |
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111 qemu_put_sbe32s(f, &env->CP0_Wired); |
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112 qemu_put_sbe32s(f, &env->CP0_SRSConf0); |
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113 qemu_put_sbe32s(f, &env->CP0_SRSConf1); |
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114 qemu_put_sbe32s(f, &env->CP0_SRSConf2); |
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115 qemu_put_sbe32s(f, &env->CP0_SRSConf3); |
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116 qemu_put_sbe32s(f, &env->CP0_SRSConf4); |
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117 qemu_put_sbe32s(f, &env->CP0_HWREna); |
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118 qemu_put_betls(f, &env->CP0_BadVAddr); |
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119 qemu_put_sbe32s(f, &env->CP0_Count); |
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120 qemu_put_betls(f, &env->CP0_EntryHi); |
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121 qemu_put_sbe32s(f, &env->CP0_Compare); |
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122 qemu_put_sbe32s(f, &env->CP0_Status); |
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123 qemu_put_sbe32s(f, &env->CP0_IntCtl); |
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124 qemu_put_sbe32s(f, &env->CP0_SRSCtl); |
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125 qemu_put_sbe32s(f, &env->CP0_SRSMap); |
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126 qemu_put_sbe32s(f, &env->CP0_Cause); |
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127 qemu_put_betls(f, &env->CP0_EPC); |
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128 qemu_put_sbe32s(f, &env->CP0_PRid); |
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129 qemu_put_sbe32s(f, &env->CP0_EBase); |
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130 qemu_put_sbe32s(f, &env->CP0_Config0); |
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131 qemu_put_sbe32s(f, &env->CP0_Config1); |
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132 qemu_put_sbe32s(f, &env->CP0_Config2); |
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133 qemu_put_sbe32s(f, &env->CP0_Config3); |
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134 qemu_put_sbe32s(f, &env->CP0_Config6); |
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135 qemu_put_sbe32s(f, &env->CP0_Config7); |
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136 qemu_put_betls(f, &env->CP0_LLAddr); |
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137 for(i = 0; i < 8; i++) |
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138 qemu_put_betls(f, &env->CP0_WatchLo[i]); |
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139 for(i = 0; i < 8; i++) |
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140 qemu_put_sbe32s(f, &env->CP0_WatchHi[i]); |
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141 qemu_put_betls(f, &env->CP0_XContext); |
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142 qemu_put_sbe32s(f, &env->CP0_Framemask); |
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143 qemu_put_sbe32s(f, &env->CP0_Debug); |
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144 qemu_put_betls(f, &env->CP0_DEPC); |
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145 qemu_put_sbe32s(f, &env->CP0_Performance0); |
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146 qemu_put_sbe32s(f, &env->CP0_TagLo); |
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147 qemu_put_sbe32s(f, &env->CP0_DataLo); |
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148 qemu_put_sbe32s(f, &env->CP0_TagHi); |
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149 qemu_put_sbe32s(f, &env->CP0_DataHi); |
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150 qemu_put_betls(f, &env->CP0_ErrorEPC); |
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151 qemu_put_sbe32s(f, &env->CP0_DESAVE); |
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152 |
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153 /* Save inactive TC state */ |
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154 for (i = 0; i < MIPS_SHADOW_SET_MAX; i++) |
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155 save_tc(f, &env->tcs[i]); |
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156 for (i = 0; i < MIPS_FPU_MAX; i++) |
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157 save_fpu(f, &env->fpus[i]); |
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158 } |
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159 |
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160 static void load_tc(QEMUFile *f, TCState *tc) |
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161 { |
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162 int i; |
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163 |
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164 /* Save active TC */ |
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165 for(i = 0; i < 32; i++) |
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166 qemu_get_betls(f, &tc->gpr[i]); |
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167 qemu_get_betls(f, &tc->PC); |
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168 for(i = 0; i < MIPS_DSP_ACC; i++) |
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169 qemu_get_betls(f, &tc->HI[i]); |
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170 for(i = 0; i < MIPS_DSP_ACC; i++) |
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171 qemu_get_betls(f, &tc->LO[i]); |
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172 for(i = 0; i < MIPS_DSP_ACC; i++) |
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173 qemu_get_betls(f, &tc->ACX[i]); |
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174 qemu_get_betls(f, &tc->DSPControl); |
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175 qemu_get_sbe32s(f, &tc->CP0_TCStatus); |
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176 qemu_get_sbe32s(f, &tc->CP0_TCBind); |
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177 qemu_get_betls(f, &tc->CP0_TCHalt); |
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178 qemu_get_betls(f, &tc->CP0_TCContext); |
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179 qemu_get_betls(f, &tc->CP0_TCSchedule); |
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180 qemu_get_betls(f, &tc->CP0_TCScheFBack); |
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181 qemu_get_sbe32s(f, &tc->CP0_Debug_tcstatus); |
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182 } |
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183 |
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184 static void load_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu) |
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185 { |
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186 int i; |
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187 |
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188 for(i = 0; i < 32; i++) |
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189 qemu_get_be64s(f, &fpu->fpr[i].d); |
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190 qemu_get_s8s(f, &fpu->fp_status.float_detect_tininess); |
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191 qemu_get_s8s(f, &fpu->fp_status.float_rounding_mode); |
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192 qemu_get_s8s(f, &fpu->fp_status.float_exception_flags); |
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193 qemu_get_be32s(f, &fpu->fcr0); |
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194 qemu_get_be32s(f, &fpu->fcr31); |
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195 } |
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196 |
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197 int cpu_load(QEMUFile *f, void *opaque, int version_id) |
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198 { |
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199 CPUState *env = opaque; |
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200 int i; |
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201 |
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202 if (version_id != 3) |
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203 return -EINVAL; |
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204 |
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205 /* Load active TC */ |
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206 load_tc(f, &env->active_tc); |
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207 |
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208 /* Load active FPU */ |
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209 load_fpu(f, &env->active_fpu); |
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210 |
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211 /* Load MVP */ |
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212 qemu_get_sbe32s(f, &env->mvp->CP0_MVPControl); |
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213 qemu_get_sbe32s(f, &env->mvp->CP0_MVPConf0); |
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214 qemu_get_sbe32s(f, &env->mvp->CP0_MVPConf1); |
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215 |
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216 /* Load TLB */ |
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217 qemu_get_be32s(f, &env->tlb->nb_tlb); |
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218 qemu_get_be32s(f, &env->tlb->tlb_in_use); |
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219 for(i = 0; i < MIPS_TLB_MAX; i++) { |
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220 uint16_t flags; |
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221 |
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222 qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].VPN); |
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223 qemu_get_be32s(f, &env->tlb->mmu.r4k.tlb[i].PageMask); |
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224 qemu_get_8s(f, &env->tlb->mmu.r4k.tlb[i].ASID); |
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225 qemu_get_be16s(f, &flags); |
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226 env->tlb->mmu.r4k.tlb[i].G = (flags >> 10) & 1; |
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227 env->tlb->mmu.r4k.tlb[i].C0 = (flags >> 7) & 3; |
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228 env->tlb->mmu.r4k.tlb[i].C1 = (flags >> 4) & 3; |
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229 env->tlb->mmu.r4k.tlb[i].V0 = (flags >> 3) & 1; |
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230 env->tlb->mmu.r4k.tlb[i].V1 = (flags >> 2) & 1; |
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231 env->tlb->mmu.r4k.tlb[i].D0 = (flags >> 1) & 1; |
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232 env->tlb->mmu.r4k.tlb[i].D1 = (flags >> 0) & 1; |
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233 qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[0]); |
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234 qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[1]); |
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235 } |
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236 |
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237 /* Load CPU metastate */ |
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238 qemu_get_be32s(f, &env->current_tc); |
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239 qemu_get_be32s(f, &env->current_fpu); |
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240 qemu_get_sbe32s(f, &env->error_code); |
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241 qemu_get_be32s(f, &env->hflags); |
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242 qemu_get_betls(f, &env->btarget); |
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243 qemu_get_sbe32s(f, &env->bcond); |
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244 |
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245 /* Load remaining CP1 registers */ |
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246 qemu_get_sbe32s(f, &env->CP0_Index); |
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247 qemu_get_sbe32s(f, &env->CP0_Random); |
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248 qemu_get_sbe32s(f, &env->CP0_VPEControl); |
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249 qemu_get_sbe32s(f, &env->CP0_VPEConf0); |
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250 qemu_get_sbe32s(f, &env->CP0_VPEConf1); |
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251 qemu_get_betls(f, &env->CP0_YQMask); |
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252 qemu_get_betls(f, &env->CP0_VPESchedule); |
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253 qemu_get_betls(f, &env->CP0_VPEScheFBack); |
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254 qemu_get_sbe32s(f, &env->CP0_VPEOpt); |
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255 qemu_get_betls(f, &env->CP0_EntryLo0); |
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256 qemu_get_betls(f, &env->CP0_EntryLo1); |
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257 qemu_get_betls(f, &env->CP0_Context); |
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258 qemu_get_sbe32s(f, &env->CP0_PageMask); |
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259 qemu_get_sbe32s(f, &env->CP0_PageGrain); |
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260 qemu_get_sbe32s(f, &env->CP0_Wired); |
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261 qemu_get_sbe32s(f, &env->CP0_SRSConf0); |
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262 qemu_get_sbe32s(f, &env->CP0_SRSConf1); |
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263 qemu_get_sbe32s(f, &env->CP0_SRSConf2); |
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264 qemu_get_sbe32s(f, &env->CP0_SRSConf3); |
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265 qemu_get_sbe32s(f, &env->CP0_SRSConf4); |
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266 qemu_get_sbe32s(f, &env->CP0_HWREna); |
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267 qemu_get_betls(f, &env->CP0_BadVAddr); |
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268 qemu_get_sbe32s(f, &env->CP0_Count); |
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269 qemu_get_betls(f, &env->CP0_EntryHi); |
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270 qemu_get_sbe32s(f, &env->CP0_Compare); |
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271 qemu_get_sbe32s(f, &env->CP0_Status); |
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272 qemu_get_sbe32s(f, &env->CP0_IntCtl); |
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273 qemu_get_sbe32s(f, &env->CP0_SRSCtl); |
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274 qemu_get_sbe32s(f, &env->CP0_SRSMap); |
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275 qemu_get_sbe32s(f, &env->CP0_Cause); |
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276 qemu_get_betls(f, &env->CP0_EPC); |
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277 qemu_get_sbe32s(f, &env->CP0_PRid); |
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278 qemu_get_sbe32s(f, &env->CP0_EBase); |
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279 qemu_get_sbe32s(f, &env->CP0_Config0); |
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280 qemu_get_sbe32s(f, &env->CP0_Config1); |
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281 qemu_get_sbe32s(f, &env->CP0_Config2); |
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282 qemu_get_sbe32s(f, &env->CP0_Config3); |
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283 qemu_get_sbe32s(f, &env->CP0_Config6); |
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284 qemu_get_sbe32s(f, &env->CP0_Config7); |
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285 qemu_get_betls(f, &env->CP0_LLAddr); |
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286 for(i = 0; i < 8; i++) |
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287 qemu_get_betls(f, &env->CP0_WatchLo[i]); |
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288 for(i = 0; i < 8; i++) |
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289 qemu_get_sbe32s(f, &env->CP0_WatchHi[i]); |
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290 qemu_get_betls(f, &env->CP0_XContext); |
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291 qemu_get_sbe32s(f, &env->CP0_Framemask); |
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292 qemu_get_sbe32s(f, &env->CP0_Debug); |
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293 qemu_get_betls(f, &env->CP0_DEPC); |
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294 qemu_get_sbe32s(f, &env->CP0_Performance0); |
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295 qemu_get_sbe32s(f, &env->CP0_TagLo); |
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296 qemu_get_sbe32s(f, &env->CP0_DataLo); |
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297 qemu_get_sbe32s(f, &env->CP0_TagHi); |
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298 qemu_get_sbe32s(f, &env->CP0_DataHi); |
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299 qemu_get_betls(f, &env->CP0_ErrorEPC); |
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300 qemu_get_sbe32s(f, &env->CP0_DESAVE); |
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301 |
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302 /* Load inactive TC state */ |
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303 for (i = 0; i < MIPS_SHADOW_SET_MAX; i++) |
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304 load_tc(f, &env->tcs[i]); |
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305 for (i = 0; i < MIPS_FPU_MAX; i++) |
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306 load_fpu(f, &env->fpus[i]); |
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307 |
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308 /* XXX: ensure compatiblity for halted bit ? */ |
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309 tlb_flush(env, 1); |
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310 return 0; |
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311 } |