1 /*

     2  *  PowerPC emulation cpu definitions for qemu.

     3  *

     4  *  Copyright (c) 2003-2007 Jocelyn Mayer

     5  *

     6  * This library is free software; you can redistribute it and/or

     7  * modify it under the terms of the GNU Lesser General Public

     8  * License as published by the Free Software Foundation; either

     9  * version 2 of the License, or (at your option) any later version.

    10  *

    11  * This library is distributed in the hope that it will be useful,

    12  * but WITHOUT ANY WARRANTY; without even the implied warranty of

    13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

    14  * Lesser General Public License for more details.

    15  *

    16  * You should have received a copy of the GNU Lesser General Public

    17  * License along with this library; if not, write to the Free Software

    18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

    19  */

    20 #if !defined (__CPU_PPC_H__)

    21 #define __CPU_PPC_H__

    22 

    23 #include "config.h"

    24 #include <inttypes.h>

    25 

    26 //#define PPC_EMULATE_32BITS_HYPV

    27 

    28 #if defined (TARGET_PPC64)

    29 /* PowerPC 64 definitions */

    30 #define TARGET_LONG_BITS 64

    31 #define TARGET_PAGE_BITS 12

    32 

    33 #else /* defined (TARGET_PPC64) */

    34 /* PowerPC 32 definitions */

    35 #define TARGET_LONG_BITS 32

    36 

    37 #if defined(TARGET_PPCEMB)

    38 /* Specific definitions for PowerPC embedded */

    39 /* BookE have 36 bits physical address space */

    40 #define TARGET_PHYS_ADDR_BITS 64

    41 #if defined(CONFIG_USER_ONLY)

    42 /* It looks like a lot of Linux programs assume page size

    43  * is 4kB long. This is evil, but we have to deal with it...

    44  */

    45 #define TARGET_PAGE_BITS 12

    46 #else /* defined(CONFIG_USER_ONLY) */

    47 /* Pages can be 1 kB small */

    48 #define TARGET_PAGE_BITS 10

    49 #endif /* defined(CONFIG_USER_ONLY) */

    50 #else /* defined(TARGET_PPCEMB) */

    51 /* "standard" PowerPC 32 definitions */

    52 #define TARGET_PAGE_BITS 12

    53 #endif /* defined(TARGET_PPCEMB) */

    54 

    55 #endif /* defined (TARGET_PPC64) */

    56 

    57 #include "cpu-defs.h"

    58 

    59 #define REGX "%016" PRIx64

    60 #define ADDRX TARGET_FMT_lx

    61 #define PADDRX TARGET_FMT_plx

    62 

    63 #include <setjmp.h>

    64 

    65 #include "softfloat.h"

    66 

    67 #define TARGET_HAS_ICE 1

    68 

    69 #if defined (TARGET_PPC64)

    70 #define ELF_MACHINE     EM_PPC64

    71 #else

    72 #define ELF_MACHINE     EM_PPC

    73 #endif

    74 

    75 /*****************************************************************************/

    76 /* MMU model                                                                 */

    77 typedef enum powerpc_mmu_t powerpc_mmu_t;

    78 enum powerpc_mmu_t {

    79     POWERPC_MMU_UNKNOWN    = 0x00000000,

    80     /* Standard 32 bits PowerPC MMU                            */

    81     POWERPC_MMU_32B        = 0x00000001,

    82     /* PowerPC 6xx MMU with software TLB                       */

    83     POWERPC_MMU_SOFT_6xx   = 0x00000002,

    84     /* PowerPC 74xx MMU with software TLB                      */

    85     POWERPC_MMU_SOFT_74xx  = 0x00000003,

    86     /* PowerPC 4xx MMU with software TLB                       */

    87     POWERPC_MMU_SOFT_4xx   = 0x00000004,

    88     /* PowerPC 4xx MMU with software TLB and zones protections */

    89     POWERPC_MMU_SOFT_4xx_Z = 0x00000005,

    90     /* PowerPC MMU in real mode only                           */

    91     POWERPC_MMU_REAL       = 0x00000006,

    92     /* Freescale MPC8xx MMU model                              */

    93     POWERPC_MMU_MPC8xx     = 0x00000007,

    94     /* BookE MMU model                                         */

    95     POWERPC_MMU_BOOKE      = 0x00000008,

    96     /* BookE FSL MMU model                                     */

    97     POWERPC_MMU_BOOKE_FSL  = 0x00000009,

    98     /* PowerPC 601 MMU model (specific BATs format)            */

    99     POWERPC_MMU_601        = 0x0000000A,

   100 #if defined(TARGET_PPC64)

   101 #define POWERPC_MMU_64       0x00010000

   102     /* 64 bits PowerPC MMU                                     */

   103     POWERPC_MMU_64B        = POWERPC_MMU_64 | 0x00000001,

   104     /* 620 variant (no segment exceptions)                     */

   105     POWERPC_MMU_620        = POWERPC_MMU_64 | 0x00000002,

   106 #endif /* defined(TARGET_PPC64) */

   107 };

   108 

   109 /*****************************************************************************/

   110 /* Exception model                                                           */

   111 typedef enum powerpc_excp_t powerpc_excp_t;

   112 enum powerpc_excp_t {

   113     POWERPC_EXCP_UNKNOWN   = 0,

   114     /* Standard PowerPC exception model */

   115     POWERPC_EXCP_STD,

   116     /* PowerPC 40x exception model      */

   117     POWERPC_EXCP_40x,

   118     /* PowerPC 601 exception model      */

   119     POWERPC_EXCP_601,

   120     /* PowerPC 602 exception model      */

   121     POWERPC_EXCP_602,

   122     /* PowerPC 603 exception model      */

   123     POWERPC_EXCP_603,

   124     /* PowerPC 603e exception model     */

   125     POWERPC_EXCP_603E,

   126     /* PowerPC G2 exception model       */

   127     POWERPC_EXCP_G2,

   128     /* PowerPC 604 exception model      */

   129     POWERPC_EXCP_604,

   130     /* PowerPC 7x0 exception model      */

   131     POWERPC_EXCP_7x0,

   132     /* PowerPC 7x5 exception model      */

   133     POWERPC_EXCP_7x5,

   134     /* PowerPC 74xx exception model     */

   135     POWERPC_EXCP_74xx,

   136     /* BookE exception model            */

   137     POWERPC_EXCP_BOOKE,

   138 #if defined(TARGET_PPC64)

   139     /* PowerPC 970 exception model      */

   140     POWERPC_EXCP_970,

   141 #endif /* defined(TARGET_PPC64) */

   142 };

   143 

   144 /*****************************************************************************/

   145 /* Exception vectors definitions                                             */

   146 enum {

   147     POWERPC_EXCP_NONE    = -1,

   148     /* The 64 first entries are used by the PowerPC embedded specification   */

   149     POWERPC_EXCP_CRITICAL = 0,  /* Critical input                            */

   150     POWERPC_EXCP_MCHECK   = 1,  /* Machine check exception                   */

   151     POWERPC_EXCP_DSI      = 2,  /* Data storage exception                    */

   152     POWERPC_EXCP_ISI      = 3,  /* Instruction storage exception             */

   153     POWERPC_EXCP_EXTERNAL = 4,  /* External input                            */

   154     POWERPC_EXCP_ALIGN    = 5,  /* Alignment exception                       */

   155     POWERPC_EXCP_PROGRAM  = 6,  /* Program exception                         */

   156     POWERPC_EXCP_FPU      = 7,  /* Floating-point unavailable exception      */

   157     POWERPC_EXCP_SYSCALL  = 8,  /* System call exception                     */

   158     POWERPC_EXCP_APU      = 9,  /* Auxiliary processor unavailable           */

   159     POWERPC_EXCP_DECR     = 10, /* Decrementer exception                     */

   160     POWERPC_EXCP_FIT      = 11, /* Fixed-interval timer interrupt            */

   161     POWERPC_EXCP_WDT      = 12, /* Watchdog timer interrupt                  */

   162     POWERPC_EXCP_DTLB     = 13, /* Data TLB miss                             */

   163     POWERPC_EXCP_ITLB     = 14, /* Instruction TLB miss                      */

   164     POWERPC_EXCP_DEBUG    = 15, /* Debug interrupt                           */

   165     /* Vectors 16 to 31 are reserved                                         */

   166     POWERPC_EXCP_SPEU     = 32, /* SPE/embedded floating-point unavailable   */

   167     POWERPC_EXCP_EFPDI    = 33, /* Embedded floating-point data interrupt    */

   168     POWERPC_EXCP_EFPRI    = 34, /* Embedded floating-point round interrupt   */

   169     POWERPC_EXCP_EPERFM   = 35, /* Embedded performance monitor interrupt    */

   170     POWERPC_EXCP_DOORI    = 36, /* Embedded doorbell interrupt               */

   171     POWERPC_EXCP_DOORCI   = 37, /* Embedded doorbell critical interrupt      */

   172     /* Vectors 38 to 63 are reserved                                         */

   173     /* Exceptions defined in the PowerPC server specification                */

   174     POWERPC_EXCP_RESET    = 64, /* System reset exception                    */

   175     POWERPC_EXCP_DSEG     = 65, /* Data segment exception                    */

   176     POWERPC_EXCP_ISEG     = 66, /* Instruction segment exception             */

   177     POWERPC_EXCP_HDECR    = 67, /* Hypervisor decrementer exception          */

   178     POWERPC_EXCP_TRACE    = 68, /* Trace exception                           */

   179     POWERPC_EXCP_HDSI     = 69, /* Hypervisor data storage exception         */

   180     POWERPC_EXCP_HISI     = 70, /* Hypervisor instruction storage exception  */

   181     POWERPC_EXCP_HDSEG    = 71, /* Hypervisor data segment exception         */

   182     POWERPC_EXCP_HISEG    = 72, /* Hypervisor instruction segment exception  */

   183     POWERPC_EXCP_VPU      = 73, /* Vector unavailable exception              */

   184     /* 40x specific exceptions                                               */

   185     POWERPC_EXCP_PIT      = 74, /* Programmable interval timer interrupt     */

   186     /* 601 specific exceptions                                               */

   187     POWERPC_EXCP_IO       = 75, /* IO error exception                        */

   188     POWERPC_EXCP_RUNM     = 76, /* Run mode exception                        */

   189     /* 602 specific exceptions                                               */

   190     POWERPC_EXCP_EMUL     = 77, /* Emulation trap exception                  */

   191     /* 602/603 specific exceptions                                           */

   192     POWERPC_EXCP_IFTLB    = 78, /* Instruction fetch TLB miss                */

   193     POWERPC_EXCP_DLTLB    = 79, /* Data load TLB miss                        */

   194     POWERPC_EXCP_DSTLB    = 80, /* Data store TLB miss                       */

   195     /* Exceptions available on most PowerPC                                  */

   196     POWERPC_EXCP_FPA      = 81, /* Floating-point assist exception           */

   197     POWERPC_EXCP_DABR     = 82, /* Data address breakpoint                   */

   198     POWERPC_EXCP_IABR     = 83, /* Instruction address breakpoint            */

   199     POWERPC_EXCP_SMI      = 84, /* System management interrupt               */

   200     POWERPC_EXCP_PERFM    = 85, /* Embedded performance monitor interrupt    */

   201     /* 7xx/74xx specific exceptions                                          */

   202     POWERPC_EXCP_THERM    = 86, /* Thermal interrupt                         */

   203     /* 74xx specific exceptions                                              */

   204     POWERPC_EXCP_VPUA     = 87, /* Vector assist exception                   */

   205     /* 970FX specific exceptions                                             */

   206     POWERPC_EXCP_SOFTP    = 88, /* Soft patch exception                      */

   207     POWERPC_EXCP_MAINT    = 89, /* Maintenance exception                     */

   208     /* Freescale embeded cores specific exceptions                           */

   209     POWERPC_EXCP_MEXTBR   = 90, /* Maskable external breakpoint              */

   210     POWERPC_EXCP_NMEXTBR  = 91, /* Non maskable external breakpoint          */

   211     POWERPC_EXCP_ITLBE    = 92, /* Instruction TLB error                     */

   212     POWERPC_EXCP_DTLBE    = 93, /* Data TLB error                            */

   213     /* EOL                                                                   */

   214     POWERPC_EXCP_NB       = 96,

   215     /* Qemu exceptions: used internally during code translation              */

   216     POWERPC_EXCP_STOP         = 0x200, /* stop translation                   */

   217     POWERPC_EXCP_BRANCH       = 0x201, /* branch instruction                 */

   218     /* Qemu exceptions: special cases we want to stop translation            */

   219     POWERPC_EXCP_SYNC         = 0x202, /* context synchronizing instruction  */

   220     POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only      */

   221 };

   222 

   223 /* Exceptions error codes                                                    */

   224 enum {

   225     /* Exception subtypes for POWERPC_EXCP_ALIGN                             */

   226     POWERPC_EXCP_ALIGN_FP      = 0x01,  /* FP alignment exception            */

   227     POWERPC_EXCP_ALIGN_LST     = 0x02,  /* Unaligned mult/extern load/store  */

   228     POWERPC_EXCP_ALIGN_LE      = 0x03,  /* Multiple little-endian access     */

   229     POWERPC_EXCP_ALIGN_PROT    = 0x04,  /* Access cross protection boundary  */

   230     POWERPC_EXCP_ALIGN_BAT     = 0x05,  /* Access cross a BAT/seg boundary   */

   231     POWERPC_EXCP_ALIGN_CACHE   = 0x06,  /* Impossible dcbz access            */

   232     /* Exception subtypes for POWERPC_EXCP_PROGRAM                           */

   233     /* FP exceptions                                                         */

   234     POWERPC_EXCP_FP            = 0x10,

   235     POWERPC_EXCP_FP_OX         = 0x01,  /* FP overflow                       */

   236     POWERPC_EXCP_FP_UX         = 0x02,  /* FP underflow                      */

   237     POWERPC_EXCP_FP_ZX         = 0x03,  /* FP divide by zero                 */

   238     POWERPC_EXCP_FP_XX         = 0x04,  /* FP inexact                        */

   239     POWERPC_EXCP_FP_VXSNAN     = 0x05,  /* FP invalid SNaN op                */

   240     POWERPC_EXCP_FP_VXISI      = 0x06,  /* FP invalid infinite subtraction   */

   241     POWERPC_EXCP_FP_VXIDI      = 0x07,  /* FP invalid infinite divide        */

   242     POWERPC_EXCP_FP_VXZDZ      = 0x08,  /* FP invalid zero divide            */

   243     POWERPC_EXCP_FP_VXIMZ      = 0x09,  /* FP invalid infinite * zero        */

   244     POWERPC_EXCP_FP_VXVC       = 0x0A,  /* FP invalid compare                */

   245     POWERPC_EXCP_FP_VXSOFT     = 0x0B,  /* FP invalid operation              */

   246     POWERPC_EXCP_FP_VXSQRT     = 0x0C,  /* FP invalid square root            */

   247     POWERPC_EXCP_FP_VXCVI      = 0x0D,  /* FP invalid integer conversion     */

   248     /* Invalid instruction                                                   */

   249     POWERPC_EXCP_INVAL         = 0x20,

   250     POWERPC_EXCP_INVAL_INVAL   = 0x01,  /* Invalid instruction               */

   251     POWERPC_EXCP_INVAL_LSWX    = 0x02,  /* Invalid lswx instruction          */

   252     POWERPC_EXCP_INVAL_SPR     = 0x03,  /* Invalid SPR access                */

   253     POWERPC_EXCP_INVAL_FP      = 0x04,  /* Unimplemented mandatory fp instr  */

   254     /* Privileged instruction                                                */

   255     POWERPC_EXCP_PRIV          = 0x30,

   256     POWERPC_EXCP_PRIV_OPC      = 0x01,  /* Privileged operation exception    */

   257     POWERPC_EXCP_PRIV_REG      = 0x02,  /* Privileged register exception     */

   258     /* Trap                                                                  */

   259     POWERPC_EXCP_TRAP          = 0x40,

   260 };

   261 

   262 /*****************************************************************************/

   263 /* Input pins model                                                          */

   264 typedef enum powerpc_input_t powerpc_input_t;

   265 enum powerpc_input_t {

   266     PPC_FLAGS_INPUT_UNKNOWN = 0,

   267     /* PowerPC 6xx bus                  */

   268     PPC_FLAGS_INPUT_6xx,

   269     /* BookE bus                        */

   270     PPC_FLAGS_INPUT_BookE,

   271     /* PowerPC 405 bus                  */

   272     PPC_FLAGS_INPUT_405,

   273     /* PowerPC 970 bus                  */

   274     PPC_FLAGS_INPUT_970,

   275     /* PowerPC 401 bus                  */

   276     PPC_FLAGS_INPUT_401,

   277     /* Freescale RCPU bus               */

   278     PPC_FLAGS_INPUT_RCPU,

   279 };

   280 

   281 #define PPC_INPUT(env) (env->bus_model)

   282 

   283 /*****************************************************************************/

   284 typedef struct ppc_def_t ppc_def_t;

   285 typedef struct opc_handler_t opc_handler_t;

   286 

   287 /*****************************************************************************/

   288 /* Types used to describe some PowerPC registers */

   289 typedef struct CPUPPCState CPUPPCState;

   290 typedef struct ppc_tb_t ppc_tb_t;

   291 typedef struct ppc_spr_t ppc_spr_t;

   292 typedef struct ppc_dcr_t ppc_dcr_t;

   293 typedef union ppc_avr_t ppc_avr_t;

   294 typedef union ppc_tlb_t ppc_tlb_t;

   295 

   296 /* SPR access micro-ops generations callbacks */

   297 struct ppc_spr_t {

   298     void (*uea_read)(void *opaque, int gpr_num, int spr_num);

   299     void (*uea_write)(void *opaque, int spr_num, int gpr_num);

   300 #if !defined(CONFIG_USER_ONLY)

   301     void (*oea_read)(void *opaque, int gpr_num, int spr_num);

   302     void (*oea_write)(void *opaque, int spr_num, int gpr_num);

   303     void (*hea_read)(void *opaque, int gpr_num, int spr_num);

   304     void (*hea_write)(void *opaque, int spr_num, int gpr_num);

   305 #endif

   306     const char *name;

   307 };

   308 

   309 /* Altivec registers (128 bits) */

   310 union ppc_avr_t {

   311     uint8_t u8[16];

   312     uint16_t u16[8];

   313     uint32_t u32[4];

   314     uint64_t u64[2];

   315     int8_t s8[16];

   316     int16_t s16[8];

   317     int32_t s32[4];

   318     float f[4];

   319 };

   320 

   321 /* Software TLB cache */

   322 typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;

   323 struct ppc6xx_tlb_t {

   324     target_ulong pte0;

   325     target_ulong pte1;

   326     target_ulong EPN;

   327 };

   328 

   329 typedef struct ppcemb_tlb_t ppcemb_tlb_t;

   330 struct ppcemb_tlb_t {

   331     target_phys_addr_t RPN;

   332     target_ulong EPN;

   333     target_ulong PID;

   334     target_ulong size;

   335     uint32_t prot;

   336     uint32_t attr; /* Storage attributes */

   337 };

   338 

   339 union ppc_tlb_t {

   340     ppc6xx_tlb_t tlb6;

   341     ppcemb_tlb_t tlbe;

   342 };

   343 

   344 /*****************************************************************************/

   345 /* Machine state register bits definition                                    */

   346 #define MSR_SF   63 /* Sixty-four-bit mode                            hflags */

   347 #define MSR_TAG  62 /* Tag-active mode (POWERx ?)                            */

   348 #define MSR_ISF  61 /* Sixty-four-bit interrupt mode on 630                  */

   349 #define MSR_SHV  60 /* hypervisor state                               hflags */

   350 #define MSR_CM   31 /* Computation mode for BookE                     hflags */

   351 #define MSR_ICM  30 /* Interrupt computation mode for BookE                  */

   352 #define MSR_THV  29 /* hypervisor state for 32 bits PowerPC           hflags */

   353 #define MSR_UCLE 26 /* User-mode cache lock enable for BookE                 */

   354 #define MSR_VR   25 /* altivec available                            x hflags */

   355 #define MSR_SPE  25 /* SPE enable for BookE                         x hflags */

   356 #define MSR_AP   23 /* Access privilege state on 602                  hflags */

   357 #define MSR_SA   22 /* Supervisor access mode on 602                  hflags */

   358 #define MSR_KEY  19 /* key bit on 603e                                       */

   359 #define MSR_POW  18 /* Power management                                      */

   360 #define MSR_TGPR 17 /* TGPR usage on 602/603                        x        */

   361 #define MSR_CE   17 /* Critical interrupt enable on embedded PowerPC x       */

   362 #define MSR_ILE  16 /* Interrupt little-endian mode                          */

   363 #define MSR_EE   15 /* External interrupt enable                             */

   364 #define MSR_PR   14 /* Problem state                                  hflags */

   365 #define MSR_FP   13 /* Floating point available                       hflags */

   366 #define MSR_ME   12 /* Machine check interrupt enable                        */

   367 #define MSR_FE0  11 /* Floating point exception mode 0                hflags */

   368 #define MSR_SE   10 /* Single-step trace enable                     x hflags */

   369 #define MSR_DWE  10 /* Debug wait enable on 405                     x        */

   370 #define MSR_UBLE 10 /* User BTB lock enable on e500                 x        */

   371 #define MSR_BE   9  /* Branch trace enable                          x hflags */

   372 #define MSR_DE   9  /* Debug interrupts enable on embedded PowerPC  x        */

   373 #define MSR_FE1  8  /* Floating point exception mode 1                hflags */

   374 #define MSR_AL   7  /* AL bit on POWER                                       */

   375 #define MSR_EP   6  /* Exception prefix on 601                               */

   376 #define MSR_IR   5  /* Instruction relocate                                  */

   377 #define MSR_DR   4  /* Data relocate                                         */

   378 #define MSR_PE   3  /* Protection enable on 403                              */

   379 #define MSR_PX   2  /* Protection exclusive on 403                  x        */

   380 #define MSR_PMM  2  /* Performance monitor mark on POWER            x        */

   381 #define MSR_RI   1  /* Recoverable interrupt                        1        */

   382 #define MSR_LE   0  /* Little-endian mode                           1 hflags */

   383 

   384 #define msr_sf   ((env->msr >> MSR_SF)   & 1)

   385 #define msr_isf  ((env->msr >> MSR_ISF)  & 1)

   386 #define msr_shv  ((env->msr >> MSR_SHV)  & 1)

   387 #define msr_cm   ((env->msr >> MSR_CM)   & 1)

   388 #define msr_icm  ((env->msr >> MSR_ICM)  & 1)

   389 #define msr_thv  ((env->msr >> MSR_THV)  & 1)

   390 #define msr_ucle ((env->msr >> MSR_UCLE) & 1)

   391 #define msr_vr   ((env->msr >> MSR_VR)   & 1)

   392 #define msr_spe  ((env->msr >> MSR_SPE)  & 1)

   393 #define msr_ap   ((env->msr >> MSR_AP)   & 1)

   394 #define msr_sa   ((env->msr >> MSR_SA)   & 1)

   395 #define msr_key  ((env->msr >> MSR_KEY)  & 1)

   396 #define msr_pow  ((env->msr >> MSR_POW)  & 1)

   397 #define msr_tgpr ((env->msr >> MSR_TGPR) & 1)

   398 #define msr_ce   ((env->msr >> MSR_CE)   & 1)

   399 #define msr_ile  ((env->msr >> MSR_ILE)  & 1)

   400 #define msr_ee   ((env->msr >> MSR_EE)   & 1)

   401 #define msr_pr   ((env->msr >> MSR_PR)   & 1)

   402 #define msr_fp   ((env->msr >> MSR_FP)   & 1)

   403 #define msr_me   ((env->msr >> MSR_ME)   & 1)

   404 #define msr_fe0  ((env->msr >> MSR_FE0)  & 1)

   405 #define msr_se   ((env->msr >> MSR_SE)   & 1)

   406 #define msr_dwe  ((env->msr >> MSR_DWE)  & 1)

   407 #define msr_uble ((env->msr >> MSR_UBLE) & 1)

   408 #define msr_be   ((env->msr >> MSR_BE)   & 1)

   409 #define msr_de   ((env->msr >> MSR_DE)   & 1)

   410 #define msr_fe1  ((env->msr >> MSR_FE1)  & 1)

   411 #define msr_al   ((env->msr >> MSR_AL)   & 1)

   412 #define msr_ep   ((env->msr >> MSR_EP)   & 1)

   413 #define msr_ir   ((env->msr >> MSR_IR)   & 1)

   414 #define msr_dr   ((env->msr >> MSR_DR)   & 1)

   415 #define msr_pe   ((env->msr >> MSR_PE)   & 1)

   416 #define msr_px   ((env->msr >> MSR_PX)   & 1)

   417 #define msr_pmm  ((env->msr >> MSR_PMM)  & 1)

   418 #define msr_ri   ((env->msr >> MSR_RI)   & 1)

   419 #define msr_le   ((env->msr >> MSR_LE)   & 1)

   420 /* Hypervisor bit is more specific */

   421 #if defined(TARGET_PPC64)

   422 #define MSR_HVB (1ULL << MSR_SHV)

   423 #define msr_hv  msr_shv

   424 #else

   425 #if defined(PPC_EMULATE_32BITS_HYPV)

   426 #define MSR_HVB (1ULL << MSR_THV)

   427 #define msr_hv  msr_thv

   428 #else

   429 #define MSR_HVB (0ULL)

   430 #define msr_hv  (0)

   431 #endif

   432 #endif

   433 

   434 enum {

   435     POWERPC_FLAG_NONE     = 0x00000000,

   436     /* Flag for MSR bit 25 signification (VRE/SPE)                           */

   437     POWERPC_FLAG_SPE      = 0x00000001,

   438     POWERPC_FLAG_VRE      = 0x00000002,

   439     /* Flag for MSR bit 17 signification (TGPR/CE)                           */

   440     POWERPC_FLAG_TGPR     = 0x00000004,

   441     POWERPC_FLAG_CE       = 0x00000008,

   442     /* Flag for MSR bit 10 signification (SE/DWE/UBLE)                       */

   443     POWERPC_FLAG_SE       = 0x00000010,

   444     POWERPC_FLAG_DWE      = 0x00000020,

   445     POWERPC_FLAG_UBLE     = 0x00000040,

   446     /* Flag for MSR bit 9 signification (BE/DE)                              */

   447     POWERPC_FLAG_BE       = 0x00000080,

   448     POWERPC_FLAG_DE       = 0x00000100,

   449     /* Flag for MSR bit 2 signification (PX/PMM)                             */

   450     POWERPC_FLAG_PX       = 0x00000200,

   451     POWERPC_FLAG_PMM      = 0x00000400,

   452     /* Flag for special features                                             */

   453     /* Decrementer clock: RTC clock (POWER, 601) or bus clock                */

   454     POWERPC_FLAG_RTC_CLK  = 0x00010000,

   455     POWERPC_FLAG_BUS_CLK  = 0x00020000,

   456 };

   457 

   458 /*****************************************************************************/

   459 /* Floating point status and control register                                */

   460 #define FPSCR_FX     31 /* Floating-point exception summary                  */

   461 #define FPSCR_FEX    30 /* Floating-point enabled exception summary          */

   462 #define FPSCR_VX     29 /* Floating-point invalid operation exception summ.  */

   463 #define FPSCR_OX     28 /* Floating-point overflow exception                 */

   464 #define FPSCR_UX     27 /* Floating-point underflow exception                */

   465 #define FPSCR_ZX     26 /* Floating-point zero divide exception              */

   466 #define FPSCR_XX     25 /* Floating-point inexact exception                  */

   467 #define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */

   468 #define FPSCR_VXISI  23 /* Floating-point invalid operation exception (inf)  */

   469 #define FPSCR_VXIDI  22 /* Floating-point invalid operation exception (inf)  */

   470 #define FPSCR_VXZDZ  21 /* Floating-point invalid operation exception (zero) */

   471 #define FPSCR_VXIMZ  20 /* Floating-point invalid operation exception (inf)  */

   472 #define FPSCR_VXVC   19 /* Floating-point invalid operation exception (comp) */

   473 #define FPSCR_FR     18 /* Floating-point fraction rounded                   */

   474 #define FPSCR_FI     17 /* Floating-point fraction inexact                   */

   475 #define FPSCR_C      16 /* Floating-point result class descriptor            */

   476 #define FPSCR_FL     15 /* Floating-point less than or negative              */

   477 #define FPSCR_FG     14 /* Floating-point greater than or negative           */

   478 #define FPSCR_FE     13 /* Floating-point equal or zero                      */

   479 #define FPSCR_FU     12 /* Floating-point unordered or NaN                   */

   480 #define FPSCR_FPCC   12 /* Floating-point condition code                     */

   481 #define FPSCR_FPRF   12 /* Floating-point result flags                       */

   482 #define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */

   483 #define FPSCR_VXSQRT 9  /* Floating-point invalid operation exception (sqrt) */

   484 #define FPSCR_VXCVI  8  /* Floating-point invalid operation exception (int)  */

   485 #define FPSCR_VE     7  /* Floating-point invalid operation exception enable */

   486 #define FPSCR_OE     6  /* Floating-point overflow exception enable          */

   487 #define FPSCR_UE     5  /* Floating-point undeflow exception enable          */

   488 #define FPSCR_ZE     4  /* Floating-point zero divide exception enable       */

   489 #define FPSCR_XE     3  /* Floating-point inexact exception enable           */

   490 #define FPSCR_NI     2  /* Floating-point non-IEEE mode                      */

   491 #define FPSCR_RN1    1

   492 #define FPSCR_RN     0  /* Floating-point rounding control                   */

   493 #define fpscr_fex    (((env->fpscr) >> FPSCR_FEX)    & 0x1)

   494 #define fpscr_vx     (((env->fpscr) >> FPSCR_VX)     & 0x1)

   495 #define fpscr_ox     (((env->fpscr) >> FPSCR_OX)     & 0x1)

   496 #define fpscr_ux     (((env->fpscr) >> FPSCR_UX)     & 0x1)

   497 #define fpscr_zx     (((env->fpscr) >> FPSCR_ZX)     & 0x1)

   498 #define fpscr_xx     (((env->fpscr) >> FPSCR_XX)     & 0x1)

   499 #define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)

   500 #define fpscr_vxisi  (((env->fpscr) >> FPSCR_VXISI)  & 0x1)

   501 #define fpscr_vxidi  (((env->fpscr) >> FPSCR_VXIDI)  & 0x1)

   502 #define fpscr_vxzdz  (((env->fpscr) >> FPSCR_VXZDZ)  & 0x1)

   503 #define fpscr_vximz  (((env->fpscr) >> FPSCR_VXIMZ)  & 0x1)

   504 #define fpscr_vxvc   (((env->fpscr) >> FPSCR_VXVC)   & 0x1)

   505 #define fpscr_fpcc   (((env->fpscr) >> FPSCR_FPCC)   & 0xF)

   506 #define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)

   507 #define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)

   508 #define fpscr_vxcvi  (((env->fpscr) >> FPSCR_VXCVI)  & 0x1)

   509 #define fpscr_ve     (((env->fpscr) >> FPSCR_VE)     & 0x1)

   510 #define fpscr_oe     (((env->fpscr) >> FPSCR_OE)     & 0x1)

   511 #define fpscr_ue     (((env->fpscr) >> FPSCR_UE)     & 0x1)

   512 #define fpscr_ze     (((env->fpscr) >> FPSCR_ZE)     & 0x1)

   513 #define fpscr_xe     (((env->fpscr) >> FPSCR_XE)     & 0x1)

   514 #define fpscr_ni     (((env->fpscr) >> FPSCR_NI)     & 0x1)

   515 #define fpscr_rn     (((env->fpscr) >> FPSCR_RN)     & 0x3)

   516 /* Invalid operation exception summary */

   517 #define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI)  | \

   518                                   (1 << FPSCR_VXIDI)  | (1 << FPSCR_VXZDZ)  | \

   519                                   (1 << FPSCR_VXIMZ)  | (1 << FPSCR_VXVC)   | \

   520                                   (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \

   521                                   (1 << FPSCR_VXCVI)))

   522 /* exception summary */

   523 #define fpscr_ex  (((env->fpscr) >> FPSCR_XX) & 0x1F)

   524 /* enabled exception summary */

   525 #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) &  \

   526                    0x1F)

   527 

   528 /*****************************************************************************/

   529 /* Vector status and control register */

   530 #define VSCR_NJ		16 /* Vector non-java */

   531 #define VSCR_SAT	0 /* Vector saturation */

   532 #define vscr_nj		(((env->vscr) >> VSCR_NJ)	& 0x1)

   533 #define vscr_sat	(((env->vscr) >> VSCR_SAT)	& 0x1)

   534 

   535 

   536 /*****************************************************************************/

   537 /* The whole PowerPC CPU context */

   538 #define NB_MMU_MODES 3

   539 

   540 struct CPUPPCState {

   541     /* First are the most commonly used resources

   542      * during translated code execution

   543      */

   544     /* general purpose registers */

   545     target_ulong gpr[32];

   546 #if !defined(TARGET_PPC64)

   547     /* Storage for GPR MSB, used by the SPE extension */

   548     target_ulong gprh[32];

   549 #endif

   550     /* LR */

   551     target_ulong lr;

   552     /* CTR */

   553     target_ulong ctr;

   554     /* condition register */

   555     uint32_t crf[8];

   556     /* XER */

   557     target_ulong xer;

   558     /* Reservation address */

   559     target_ulong reserve;

   560 

   561     /* Those ones are used in supervisor mode only */

   562     /* machine state register */

   563     target_ulong msr;

   564     /* temporary general purpose registers */

   565     target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */

   566 

   567     /* Floating point execution context */

   568     float_status fp_status;

   569     /* floating point registers */

   570     float64 fpr[32];

   571     /* floating point status and control register */

   572     uint32_t fpscr;

   573 

   574     CPU_COMMON

   575 

   576     int access_type; /* when a memory exception occurs, the access

   577                         type is stored here */

   578 

   579     /* MMU context - only relevant for full system emulation */

   580 #if !defined(CONFIG_USER_ONLY)

   581 #if defined(TARGET_PPC64)

   582     /* Address space register */

   583     target_ulong asr;

   584     /* PowerPC 64 SLB area */

   585     int slb_nr;

   586 #endif

   587     /* segment registers */

   588     target_ulong sdr1;

   589     target_ulong sr[32];

   590     /* BATs */

   591     int nb_BATs;

   592     target_ulong DBAT[2][8];

   593     target_ulong IBAT[2][8];

   594     /* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */

   595     int nb_tlb;      /* Total number of TLB                                  */

   596     int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */

   597     int nb_ways;     /* Number of ways in the TLB set                        */

   598     int last_way;    /* Last used way used to allocate TLB in a LRU way      */

   599     int id_tlbs;     /* If 1, MMU has separated TLBs for instructions & data */

   600     int nb_pids;     /* Number of available PID registers                    */

   601     ppc_tlb_t *tlb;  /* TLB is optional. Allocate them only if needed        */

   602     /* 403 dedicated access protection registers */

   603     target_ulong pb[4];

   604 #endif

   605 

   606     /* Other registers */

   607     /* Special purpose registers */

   608     target_ulong spr[1024];

   609     ppc_spr_t spr_cb[1024];

   610     /* Altivec registers */

   611     ppc_avr_t avr[32];

   612     uint32_t vscr;

   613     /* SPE registers */

   614     uint64_t spe_acc;

   615     float_status spe_status;

   616     uint32_t spe_fscr;

   617 

   618     /* Internal devices resources */

   619     /* Time base and decrementer */

   620     ppc_tb_t *tb_env;

   621     /* Device control registers */

   622     ppc_dcr_t *dcr_env;

   623 

   624     int dcache_line_size;

   625     int icache_line_size;

   626 

   627     /* Those resources are used during exception processing */

   628     /* CPU model definition */

   629     target_ulong msr_mask;

   630     powerpc_mmu_t mmu_model;

   631     powerpc_excp_t excp_model;

   632     powerpc_input_t bus_model;

   633     int bfd_mach;

   634     uint32_t flags;

   635 

   636     int error_code;

   637     uint32_t pending_interrupts;

   638 #if !defined(CONFIG_USER_ONLY)

   639     /* This is the IRQ controller, which is implementation dependant

   640      * and only relevant when emulating a complete machine.

   641      */

   642     uint32_t irq_input_state;

   643     void **irq_inputs;

   644     /* Exception vectors */

   645     target_ulong excp_vectors[POWERPC_EXCP_NB];

   646     target_ulong excp_prefix;

   647     target_ulong ivor_mask;

   648     target_ulong ivpr_mask;

   649     target_ulong hreset_vector;

   650 #endif

   651 

   652     /* Those resources are used only during code translation */

   653     /* Next instruction pointer */

   654     target_ulong nip;

   655 

   656     /* opcode handlers */

   657     opc_handler_t *opcodes[0x40];

   658 

   659     /* Those resources are used only in Qemu core */

   660     target_ulong hflags;      /* hflags is a MSR & HFLAGS_MASK         */

   661     target_ulong hflags_nmsr; /* specific hflags, not comming from MSR */

   662     int mmu_idx;         /* precomputed MMU index to speed up mem accesses */

   663 

   664     /* Power management */

   665     int power_mode;

   666     int (*check_pow)(CPUPPCState *env);

   667 

   668     /* temporary hack to handle OSI calls (only used if non NULL) */

   669     int (*osi_call)(struct CPUPPCState *env);

   670 };

   671 

   672 /* Context used internally during MMU translations */

   673 typedef struct mmu_ctx_t mmu_ctx_t;

   674 struct mmu_ctx_t {

   675     target_phys_addr_t raddr;      /* Real address              */

   676     int prot;                      /* Protection bits           */

   677     target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */

   678     target_ulong ptem;             /* Virtual segment ID | API  */

   679     int key;                       /* Access key                */

   680     int nx;                        /* Non-execute area          */

   681 };

   682 

   683 /*****************************************************************************/

   684 CPUPPCState *cpu_ppc_init (const char *cpu_model);

   685 void ppc_translate_init(void);

   686 int cpu_ppc_exec (CPUPPCState *s);

   687 void cpu_ppc_close (CPUPPCState *s);

   688 /* you can call this signal handler from your SIGBUS and SIGSEGV

   689    signal handlers to inform the virtual CPU of exceptions. non zero

   690    is returned if the signal was handled by the virtual CPU.  */

   691 int cpu_ppc_signal_handler (int host_signum, void *pinfo,

   692                             void *puc);

   693 int cpu_ppc_handle_mmu_fault (CPUPPCState *env, target_ulong address, int rw,

   694                               int mmu_idx, int is_softmmu);

   695 int get_physical_address (CPUPPCState *env, mmu_ctx_t *ctx, target_ulong vaddr,

   696                           int rw, int access_type);

   697 void do_interrupt (CPUPPCState *env);

   698 void ppc_hw_interrupt (CPUPPCState *env);

   699 

   700 void cpu_dump_rfi (target_ulong RA, target_ulong msr);

   701 

   702 #if !defined(CONFIG_USER_ONLY)

   703 void ppc6xx_tlb_store (CPUPPCState *env, target_ulong EPN, int way, int is_code,

   704                        target_ulong pte0, target_ulong pte1);

   705 void ppc_store_ibatu (CPUPPCState *env, int nr, target_ulong value);

   706 void ppc_store_ibatl (CPUPPCState *env, int nr, target_ulong value);

   707 void ppc_store_dbatu (CPUPPCState *env, int nr, target_ulong value);

   708 void ppc_store_dbatl (CPUPPCState *env, int nr, target_ulong value);

   709 void ppc_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value);

   710 void ppc_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value);

   711 void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);

   712 #if defined(TARGET_PPC64)

   713 void ppc_store_asr (CPUPPCState *env, target_ulong value);

   714 target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr);

   715 void ppc_store_slb (CPUPPCState *env, int slb_nr, target_ulong rs);

   716 #endif /* defined(TARGET_PPC64) */

   717 void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value);

   718 void do_ppc_semihosting(CPUPPCState *env);

   719 #endif /* !defined(CONFIG_USER_ONLY) */

   720 void ppc_store_msr (CPUPPCState *env, target_ulong value);

   721 

   722 void cpu_ppc_reset (void *opaque);

   723 

   724 void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));

   725 

   726 const ppc_def_t *cpu_ppc_find_by_name (const char *name);

   727 int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def);

   728 

   729 /* Time-base and decrementer management */

   730 #ifndef NO_CPU_IO_DEFS

   731 uint32_t cpu_ppc_load_tbl (CPUPPCState *env);

   732 uint32_t cpu_ppc_load_tbu (CPUPPCState *env);

   733 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);

   734 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);

   735 uint32_t cpu_ppc_load_atbl (CPUPPCState *env);

   736 uint32_t cpu_ppc_load_atbu (CPUPPCState *env);

   737 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);

   738 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);

   739 uint32_t cpu_ppc_load_decr (CPUPPCState *env);

   740 void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);

   741 uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);

   742 void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);

   743 uint64_t cpu_ppc_load_purr (CPUPPCState *env);

   744 void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value);

   745 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);

   746 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);

   747 #if !defined(CONFIG_USER_ONLY)

   748 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);

   749 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);

   750 target_ulong load_40x_pit (CPUPPCState *env);

   751 void store_40x_pit (CPUPPCState *env, target_ulong val);

   752 void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);

   753 void store_40x_sler (CPUPPCState *env, uint32_t val);

   754 void store_booke_tcr (CPUPPCState *env, target_ulong val);

   755 void store_booke_tsr (CPUPPCState *env, target_ulong val);

   756 void ppc_tlb_invalidate_all (CPUPPCState *env);

   757 void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);

   758 #if defined(TARGET_PPC64)

   759 void ppc_slb_invalidate_all (CPUPPCState *env);

   760 void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0);

   761 #endif

   762 int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid);

   763 #endif

   764 #endif

   765 

   766 static always_inline uint64_t ppc_dump_gpr (CPUPPCState *env, int gprn)

   767 {

   768     uint64_t gprv;

   769 

   770     gprv = env->gpr[gprn];

   771 #if !defined(TARGET_PPC64)

   772     if (env->flags & POWERPC_FLAG_SPE) {

   773         /* If the CPU implements the SPE extension, we have to get the

   774          * high bits of the GPR from the gprh storage area

   775          */

   776         gprv &= 0xFFFFFFFFULL;

   777         gprv |= (uint64_t)env->gprh[gprn] << 32;

   778     }

   779 #endif

   780 

   781     return gprv;

   782 }

   783 

   784 /* Device control registers */

   785 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp);

   786 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);

   787 

   788 #define CPUState CPUPPCState

   789 #define cpu_init cpu_ppc_init

   790 #define cpu_exec cpu_ppc_exec

   791 #define cpu_gen_code cpu_ppc_gen_code

   792 #define cpu_signal_handler cpu_ppc_signal_handler

   793 #define cpu_list ppc_cpu_list

   794 

   795 #define CPU_SAVE_VERSION 3

   796 

   797 /* MMU modes definitions */

   798 #define MMU_MODE0_SUFFIX _user

   799 #define MMU_MODE1_SUFFIX _kernel

   800 #define MMU_MODE2_SUFFIX _hypv

   801 #define MMU_USER_IDX 0

   802 static inline int cpu_mmu_index (CPUState *env)

   803 {

   804     return env->mmu_idx;

   805 }

   806 

   807 #if defined(CONFIG_USER_ONLY)

   808 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)

   809 {

   810     int i;

   811     if (newsp)

   812         env->gpr[1] = newsp;

   813     for (i = 7; i < 32; i++)

   814         env->gpr[i] = 0;

   815 }

   816 #endif

   817 

   818 #include "cpu-all.h"

   819 #include "exec-all.h"

   820 

   821 /*****************************************************************************/

   822 /* CRF definitions */

   823 #define CRF_LT        3

   824 #define CRF_GT        2

   825 #define CRF_EQ        1

   826 #define CRF_SO        0

   827 #define CRF_CH        (1 << 4)

   828 #define CRF_CL        (1 << 3)

   829 #define CRF_CH_OR_CL  (1 << 2)

   830 #define CRF_CH_AND_CL (1 << 1)

   831 

   832 /* XER definitions */

   833 #define XER_SO  31

   834 #define XER_OV  30

   835 #define XER_CA  29

   836 #define XER_CMP  8

   837 #define XER_BC   0

   838 #define xer_so  ((env->xer >> XER_SO)  &    1)

   839 #define xer_ov  ((env->xer >> XER_OV)  &    1)

   840 #define xer_ca  ((env->xer >> XER_CA)  &    1)

   841 #define xer_cmp ((env->xer >> XER_CMP) & 0xFF)

   842 #define xer_bc  ((env->xer >> XER_BC)  & 0x7F)

   843 

   844 /* SPR definitions */

   845 #define SPR_MQ                (0x000)

   846 #define SPR_XER               (0x001)

   847 #define SPR_601_VRTCU         (0x004)

   848 #define SPR_601_VRTCL         (0x005)

   849 #define SPR_601_UDECR         (0x006)

   850 #define SPR_LR                (0x008)

   851 #define SPR_CTR               (0x009)

   852 #define SPR_DSISR             (0x012)

   853 #define SPR_DAR               (0x013) /* DAE for PowerPC 601 */

   854 #define SPR_601_RTCU          (0x014)

   855 #define SPR_601_RTCL          (0x015)

   856 #define SPR_DECR              (0x016)

   857 #define SPR_SDR1              (0x019)

   858 #define SPR_SRR0              (0x01A)

   859 #define SPR_SRR1              (0x01B)

   860 #define SPR_AMR               (0x01D)

   861 #define SPR_BOOKE_PID         (0x030)

   862 #define SPR_BOOKE_DECAR       (0x036)

   863 #define SPR_BOOKE_CSRR0       (0x03A)

   864 #define SPR_BOOKE_CSRR1       (0x03B)

   865 #define SPR_BOOKE_DEAR        (0x03D)

   866 #define SPR_BOOKE_ESR         (0x03E)

   867 #define SPR_BOOKE_IVPR        (0x03F)

   868 #define SPR_MPC_EIE           (0x050)

   869 #define SPR_MPC_EID           (0x051)

   870 #define SPR_MPC_NRI           (0x052)

   871 #define SPR_CTRL              (0x088)

   872 #define SPR_MPC_CMPA          (0x090)

   873 #define SPR_MPC_CMPB          (0x091)

   874 #define SPR_MPC_CMPC          (0x092)

   875 #define SPR_MPC_CMPD          (0x093)

   876 #define SPR_MPC_ECR           (0x094)

   877 #define SPR_MPC_DER           (0x095)

   878 #define SPR_MPC_COUNTA        (0x096)

   879 #define SPR_MPC_COUNTB        (0x097)

   880 #define SPR_UCTRL             (0x098)

   881 #define SPR_MPC_CMPE          (0x098)

   882 #define SPR_MPC_CMPF          (0x099)

   883 #define SPR_MPC_CMPG          (0x09A)

   884 #define SPR_MPC_CMPH          (0x09B)

   885 #define SPR_MPC_LCTRL1        (0x09C)

   886 #define SPR_MPC_LCTRL2        (0x09D)

   887 #define SPR_MPC_ICTRL         (0x09E)

   888 #define SPR_MPC_BAR           (0x09F)

   889 #define SPR_VRSAVE            (0x100)

   890 #define SPR_USPRG0            (0x100)

   891 #define SPR_USPRG1            (0x101)

   892 #define SPR_USPRG2            (0x102)

   893 #define SPR_USPRG3            (0x103)

   894 #define SPR_USPRG4            (0x104)

   895 #define SPR_USPRG5            (0x105)

   896 #define SPR_USPRG6            (0x106)

   897 #define SPR_USPRG7            (0x107)

   898 #define SPR_VTBL              (0x10C)

   899 #define SPR_VTBU              (0x10D)

   900 #define SPR_SPRG0             (0x110)

   901 #define SPR_SPRG1             (0x111)

   902 #define SPR_SPRG2             (0x112)

   903 #define SPR_SPRG3             (0x113)

   904 #define SPR_SPRG4             (0x114)

   905 #define SPR_SCOMC             (0x114)

   906 #define SPR_SPRG5             (0x115)

   907 #define SPR_SCOMD             (0x115)

   908 #define SPR_SPRG6             (0x116)

   909 #define SPR_SPRG7             (0x117)

   910 #define SPR_ASR               (0x118)

   911 #define SPR_EAR               (0x11A)

   912 #define SPR_TBL               (0x11C)

   913 #define SPR_TBU               (0x11D)

   914 #define SPR_TBU40             (0x11E)

   915 #define SPR_SVR               (0x11E)

   916 #define SPR_BOOKE_PIR         (0x11E)

   917 #define SPR_PVR               (0x11F)

   918 #define SPR_HSPRG0            (0x130)

   919 #define SPR_BOOKE_DBSR        (0x130)

   920 #define SPR_HSPRG1            (0x131)

   921 #define SPR_HDSISR            (0x132)

   922 #define SPR_HDAR              (0x133)

   923 #define SPR_BOOKE_DBCR0       (0x134)

   924 #define SPR_IBCR              (0x135)

   925 #define SPR_PURR              (0x135)

   926 #define SPR_BOOKE_DBCR1       (0x135)

   927 #define SPR_DBCR              (0x136)

   928 #define SPR_HDEC              (0x136)

   929 #define SPR_BOOKE_DBCR2       (0x136)

   930 #define SPR_HIOR              (0x137)

   931 #define SPR_MBAR              (0x137)

   932 #define SPR_RMOR              (0x138)

   933 #define SPR_BOOKE_IAC1        (0x138)

   934 #define SPR_HRMOR             (0x139)

   935 #define SPR_BOOKE_IAC2        (0x139)

   936 #define SPR_HSRR0             (0x13A)

   937 #define SPR_BOOKE_IAC3        (0x13A)

   938 #define SPR_HSRR1             (0x13B)

   939 #define SPR_BOOKE_IAC4        (0x13B)

   940 #define SPR_LPCR              (0x13C)

   941 #define SPR_BOOKE_DAC1        (0x13C)

   942 #define SPR_LPIDR             (0x13D)

   943 #define SPR_DABR2             (0x13D)

   944 #define SPR_BOOKE_DAC2        (0x13D)

   945 #define SPR_BOOKE_DVC1        (0x13E)

   946 #define SPR_BOOKE_DVC2        (0x13F)

   947 #define SPR_BOOKE_TSR         (0x150)

   948 #define SPR_BOOKE_TCR         (0x154)

   949 #define SPR_BOOKE_IVOR0       (0x190)

   950 #define SPR_BOOKE_IVOR1       (0x191)

   951 #define SPR_BOOKE_IVOR2       (0x192)

   952 #define SPR_BOOKE_IVOR3       (0x193)

   953 #define SPR_BOOKE_IVOR4       (0x194)

   954 #define SPR_BOOKE_IVOR5       (0x195)

   955 #define SPR_BOOKE_IVOR6       (0x196)

   956 #define SPR_BOOKE_IVOR7       (0x197)

   957 #define SPR_BOOKE_IVOR8       (0x198)

   958 #define SPR_BOOKE_IVOR9       (0x199)

   959 #define SPR_BOOKE_IVOR10      (0x19A)

   960 #define SPR_BOOKE_IVOR11      (0x19B)

   961 #define SPR_BOOKE_IVOR12      (0x19C)

   962 #define SPR_BOOKE_IVOR13      (0x19D)

   963 #define SPR_BOOKE_IVOR14      (0x19E)

   964 #define SPR_BOOKE_IVOR15      (0x19F)

   965 #define SPR_BOOKE_SPEFSCR     (0x200)

   966 #define SPR_Exxx_BBEAR        (0x201)

   967 #define SPR_Exxx_BBTAR        (0x202)

   968 #define SPR_Exxx_L1CFG0       (0x203)

   969 #define SPR_Exxx_NPIDR        (0x205)

   970 #define SPR_ATBL              (0x20E)

   971 #define SPR_ATBU              (0x20F)

   972 #define SPR_IBAT0U            (0x210)

   973 #define SPR_BOOKE_IVOR32      (0x210)

   974 #define SPR_RCPU_MI_GRA       (0x210)

   975 #define SPR_IBAT0L            (0x211)

   976 #define SPR_BOOKE_IVOR33      (0x211)

   977 #define SPR_IBAT1U            (0x212)

   978 #define SPR_BOOKE_IVOR34      (0x212)

   979 #define SPR_IBAT1L            (0x213)

   980 #define SPR_BOOKE_IVOR35      (0x213)

   981 #define SPR_IBAT2U            (0x214)

   982 #define SPR_BOOKE_IVOR36      (0x214)

   983 #define SPR_IBAT2L            (0x215)

   984 #define SPR_BOOKE_IVOR37      (0x215)

   985 #define SPR_IBAT3U            (0x216)

   986 #define SPR_IBAT3L            (0x217)

   987 #define SPR_DBAT0U            (0x218)

   988 #define SPR_RCPU_L2U_GRA      (0x218)

   989 #define SPR_DBAT0L            (0x219)

   990 #define SPR_DBAT1U            (0x21A)

   991 #define SPR_DBAT1L            (0x21B)

   992 #define SPR_DBAT2U            (0x21C)

   993 #define SPR_DBAT2L            (0x21D)

   994 #define SPR_DBAT3U            (0x21E)

   995 #define SPR_DBAT3L            (0x21F)

   996 #define SPR_IBAT4U            (0x230)

   997 #define SPR_RPCU_BBCMCR       (0x230)

   998 #define SPR_MPC_IC_CST        (0x230)

   999 #define SPR_Exxx_CTXCR        (0x230)

  1000 #define SPR_IBAT4L            (0x231)

  1001 #define SPR_MPC_IC_ADR        (0x231)

  1002 #define SPR_Exxx_DBCR3        (0x231)

  1003 #define SPR_IBAT5U            (0x232)

  1004 #define SPR_MPC_IC_DAT        (0x232)

  1005 #define SPR_Exxx_DBCNT        (0x232)

  1006 #define SPR_IBAT5L            (0x233)

  1007 #define SPR_IBAT6U            (0x234)

  1008 #define SPR_IBAT6L            (0x235)

  1009 #define SPR_IBAT7U            (0x236)

  1010 #define SPR_IBAT7L            (0x237)

  1011 #define SPR_DBAT4U            (0x238)

  1012 #define SPR_RCPU_L2U_MCR      (0x238)

  1013 #define SPR_MPC_DC_CST        (0x238)

  1014 #define SPR_Exxx_ALTCTXCR     (0x238)

  1015 #define SPR_DBAT4L            (0x239)

  1016 #define SPR_MPC_DC_ADR        (0x239)

  1017 #define SPR_DBAT5U            (0x23A)

  1018 #define SPR_BOOKE_MCSRR0      (0x23A)

  1019 #define SPR_MPC_DC_DAT        (0x23A)

  1020 #define SPR_DBAT5L            (0x23B)

  1021 #define SPR_BOOKE_MCSRR1      (0x23B)

  1022 #define SPR_DBAT6U            (0x23C)

  1023 #define SPR_BOOKE_MCSR        (0x23C)

  1024 #define SPR_DBAT6L            (0x23D)

  1025 #define SPR_Exxx_MCAR         (0x23D)

  1026 #define SPR_DBAT7U            (0x23E)

  1027 #define SPR_BOOKE_DSRR0       (0x23E)

  1028 #define SPR_DBAT7L            (0x23F)

  1029 #define SPR_BOOKE_DSRR1       (0x23F)

  1030 #define SPR_BOOKE_SPRG8       (0x25C)

  1031 #define SPR_BOOKE_SPRG9       (0x25D)

  1032 #define SPR_BOOKE_MAS0        (0x270)

  1033 #define SPR_BOOKE_MAS1        (0x271)

  1034 #define SPR_BOOKE_MAS2        (0x272)

  1035 #define SPR_BOOKE_MAS3        (0x273)

  1036 #define SPR_BOOKE_MAS4        (0x274)

  1037 #define SPR_BOOKE_MAS5        (0x275)

  1038 #define SPR_BOOKE_MAS6        (0x276)

  1039 #define SPR_BOOKE_PID1        (0x279)

  1040 #define SPR_BOOKE_PID2        (0x27A)

  1041 #define SPR_MPC_DPDR          (0x280)

  1042 #define SPR_MPC_IMMR          (0x288)

  1043 #define SPR_BOOKE_TLB0CFG     (0x2B0)

  1044 #define SPR_BOOKE_TLB1CFG     (0x2B1)

  1045 #define SPR_BOOKE_TLB2CFG     (0x2B2)

  1046 #define SPR_BOOKE_TLB3CFG     (0x2B3)

  1047 #define SPR_BOOKE_EPR         (0x2BE)

  1048 #define SPR_PERF0             (0x300)

  1049 #define SPR_RCPU_MI_RBA0      (0x300)

  1050 #define SPR_MPC_MI_CTR        (0x300)

  1051 #define SPR_PERF1             (0x301)

  1052 #define SPR_RCPU_MI_RBA1      (0x301)

  1053 #define SPR_PERF2             (0x302)

  1054 #define SPR_RCPU_MI_RBA2      (0x302)

  1055 #define SPR_MPC_MI_AP         (0x302)

  1056 #define SPR_PERF3             (0x303)

  1057 #define SPR_620_PMC1R         (0x303)

  1058 #define SPR_RCPU_MI_RBA3      (0x303)

  1059 #define SPR_MPC_MI_EPN        (0x303)

  1060 #define SPR_PERF4             (0x304)

  1061 #define SPR_620_PMC2R         (0x304)

  1062 #define SPR_PERF5             (0x305)

  1063 #define SPR_MPC_MI_TWC        (0x305)

  1064 #define SPR_PERF6             (0x306)

  1065 #define SPR_MPC_MI_RPN        (0x306)

  1066 #define SPR_PERF7             (0x307)

  1067 #define SPR_PERF8             (0x308)

  1068 #define SPR_RCPU_L2U_RBA0     (0x308)

  1069 #define SPR_MPC_MD_CTR        (0x308)

  1070 #define SPR_PERF9             (0x309)

  1071 #define SPR_RCPU_L2U_RBA1     (0x309)

  1072 #define SPR_MPC_MD_CASID      (0x309)

  1073 #define SPR_PERFA             (0x30A)

  1074 #define SPR_RCPU_L2U_RBA2     (0x30A)

  1075 #define SPR_MPC_MD_AP         (0x30A)

  1076 #define SPR_PERFB             (0x30B)

  1077 #define SPR_620_MMCR0R        (0x30B)

  1078 #define SPR_RCPU_L2U_RBA3     (0x30B)

  1079 #define SPR_MPC_MD_EPN        (0x30B)

  1080 #define SPR_PERFC             (0x30C)

  1081 #define SPR_MPC_MD_TWB        (0x30C)

  1082 #define SPR_PERFD             (0x30D)

  1083 #define SPR_MPC_MD_TWC        (0x30D)

  1084 #define SPR_PERFE             (0x30E)

  1085 #define SPR_MPC_MD_RPN        (0x30E)

  1086 #define SPR_PERFF             (0x30F)

  1087 #define SPR_MPC_MD_TW         (0x30F)

  1088 #define SPR_UPERF0            (0x310)

  1089 #define SPR_UPERF1            (0x311)

  1090 #define SPR_UPERF2            (0x312)

  1091 #define SPR_UPERF3            (0x313)

  1092 #define SPR_620_PMC1W         (0x313)

  1093 #define SPR_UPERF4            (0x314)

  1094 #define SPR_620_PMC2W         (0x314)

  1095 #define SPR_UPERF5            (0x315)

  1096 #define SPR_UPERF6            (0x316)

  1097 #define SPR_UPERF7            (0x317)

  1098 #define SPR_UPERF8            (0x318)

  1099 #define SPR_UPERF9            (0x319)

  1100 #define SPR_UPERFA            (0x31A)

  1101 #define SPR_UPERFB            (0x31B)

  1102 #define SPR_620_MMCR0W        (0x31B)

  1103 #define SPR_UPERFC            (0x31C)

  1104 #define SPR_UPERFD            (0x31D)

  1105 #define SPR_UPERFE            (0x31E)

  1106 #define SPR_UPERFF            (0x31F)

  1107 #define SPR_RCPU_MI_RA0       (0x320)

  1108 #define SPR_MPC_MI_DBCAM      (0x320)

  1109 #define SPR_RCPU_MI_RA1       (0x321)

  1110 #define SPR_MPC_MI_DBRAM0     (0x321)

  1111 #define SPR_RCPU_MI_RA2       (0x322)

  1112 #define SPR_MPC_MI_DBRAM1     (0x322)

  1113 #define SPR_RCPU_MI_RA3       (0x323)

  1114 #define SPR_RCPU_L2U_RA0      (0x328)

  1115 #define SPR_MPC_MD_DBCAM      (0x328)

  1116 #define SPR_RCPU_L2U_RA1      (0x329)

  1117 #define SPR_MPC_MD_DBRAM0     (0x329)

  1118 #define SPR_RCPU_L2U_RA2      (0x32A)

  1119 #define SPR_MPC_MD_DBRAM1     (0x32A)

  1120 #define SPR_RCPU_L2U_RA3      (0x32B)

  1121 #define SPR_440_INV0          (0x370)

  1122 #define SPR_440_INV1          (0x371)

  1123 #define SPR_440_INV2          (0x372)

  1124 #define SPR_440_INV3          (0x373)

  1125 #define SPR_440_ITV0          (0x374)

  1126 #define SPR_440_ITV1          (0x375)

  1127 #define SPR_440_ITV2          (0x376)

  1128 #define SPR_440_ITV3          (0x377)

  1129 #define SPR_440_CCR1          (0x378)

  1130 #define SPR_DCRIPR            (0x37B)

  1131 #define SPR_PPR               (0x380)

  1132 #define SPR_750_GQR0          (0x390)

  1133 #define SPR_440_DNV0          (0x390)

  1134 #define SPR_750_GQR1          (0x391)

  1135 #define SPR_440_DNV1          (0x391)