1 /*

     2  *  PowerPC emulation for qemu: main translation routines.

     3  *

     4  *  Copyright (c) 2003-2007 Jocelyn Mayer

     5  *

     6  * This library is free software; you can redistribute it and/or

     7  * modify it under the terms of the GNU Lesser General Public

     8  * License as published by the Free Software Foundation; either

     9  * version 2 of the License, or (at your option) any later version.

    10  *

    11  * This library is distributed in the hope that it will be useful,

    12  * but WITHOUT ANY WARRANTY; without even the implied warranty of

    13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

    14  * Lesser General Public License for more details.

    15  *

    16  * You should have received a copy of the GNU Lesser General Public

    17  * License along with this library; if not, write to the Free Software

    18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

    19  */

    20 #include <stdarg.h>

    21 #include <stdlib.h>

    22 #include <stdio.h>

    23 #include <string.h>

    24 #include <inttypes.h>

    25 

    26 #include "cpu.h"

    27 #include "exec-all.h"

    28 #include "disas.h"

    29 #include "tcg-op.h"

    30 #include "qemu-common.h"

    31 

    32 #include "helper.h"

    33 #define GEN_HELPER 1

    34 #include "helper.h"

    35 

    36 #define CPU_SINGLE_STEP 0x1

    37 #define CPU_BRANCH_STEP 0x2

    38 #define GDBSTUB_SINGLE_STEP 0x4

    39 

    40 /* Include definitions for instructions classes and implementations flags */

    41 //#define DO_SINGLE_STEP

    42 //#define PPC_DEBUG_DISAS

    43 //#define DO_PPC_STATISTICS

    44 

    45 /*****************************************************************************/

    46 /* Code translation helpers                                                  */

    47 

    48 /* global register indexes */

    49 static TCGv_ptr cpu_env;

    50 static char cpu_reg_names[10*3 + 22*4 /* GPR */

    51 #if !defined(TARGET_PPC64)

    52     + 10*4 + 22*5 /* SPE GPRh */

    53 #endif

    54     + 10*4 + 22*5 /* FPR */

    55     + 2*(10*6 + 22*7) /* AVRh, AVRl */

    56     + 8*5 /* CRF */];

    57 static TCGv cpu_gpr[32];

    58 #if !defined(TARGET_PPC64)

    59 static TCGv cpu_gprh[32];

    60 #endif

    61 static TCGv_i64 cpu_fpr[32];

    62 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];

    63 static TCGv_i32 cpu_crf[8];

    64 static TCGv cpu_nip;

    65 static TCGv cpu_msr;

    66 static TCGv cpu_ctr;

    67 static TCGv cpu_lr;

    68 static TCGv cpu_xer;

    69 static TCGv cpu_reserve;

    70 static TCGv_i32 cpu_fpscr;

    71 static TCGv_i32 cpu_access_type;

    72 

    73 #include "gen-icount.h"

    74 

    75 void ppc_translate_init(void)

    76 {

    77     int i;

    78     char* p;

    79     static int done_init = 0;

    80 

    81     if (done_init)

    82         return;

    83 

    84     cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");

    85 

    86     p = cpu_reg_names;

    87 

    88     for (i = 0; i < 8; i++) {

    89         sprintf(p, "crf%d", i);

    90         cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,

    91                                             offsetof(CPUState, crf[i]), p);

    92         p += 5;

    93     }

    94 

    95     for (i = 0; i < 32; i++) {

    96         sprintf(p, "r%d", i);

    97         cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,

    98                                         offsetof(CPUState, gpr[i]), p);

    99         p += (i < 10) ? 3 : 4;

   100 #if !defined(TARGET_PPC64)

   101         sprintf(p, "r%dH", i);

   102         cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,

   103                                              offsetof(CPUState, gprh[i]), p);

   104         p += (i < 10) ? 4 : 5;

   105 #endif

   106 

   107         sprintf(p, "fp%d", i);

   108         cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,

   109                                             offsetof(CPUState, fpr[i]), p);

   110         p += (i < 10) ? 4 : 5;

   111 

   112         sprintf(p, "avr%dH", i);

   113 #ifdef WORDS_BIGENDIAN

   114         cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,

   115                                              offsetof(CPUState, avr[i].u64[0]), p);

   116 #else

   117         cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,

   118                                              offsetof(CPUState, avr[i].u64[1]), p);

   119 #endif

   120         p += (i < 10) ? 6 : 7;

   121 

   122         sprintf(p, "avr%dL", i);

   123 #ifdef WORDS_BIGENDIAN

   124         cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,

   125                                              offsetof(CPUState, avr[i].u64[1]), p);

   126 #else

   127         cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,

   128                                              offsetof(CPUState, avr[i].u64[0]), p);

   129 #endif

   130         p += (i < 10) ? 6 : 7;

   131     }

   132 

   133     cpu_nip = tcg_global_mem_new(TCG_AREG0,

   134                                  offsetof(CPUState, nip), "nip");

   135 

   136     cpu_msr = tcg_global_mem_new(TCG_AREG0,

   137                                  offsetof(CPUState, msr), "msr");

   138 

   139     cpu_ctr = tcg_global_mem_new(TCG_AREG0,

   140                                  offsetof(CPUState, ctr), "ctr");

   141 

   142     cpu_lr = tcg_global_mem_new(TCG_AREG0,

   143                                 offsetof(CPUState, lr), "lr");

   144 

   145     cpu_xer = tcg_global_mem_new(TCG_AREG0,

   146                                  offsetof(CPUState, xer), "xer");

   147 

   148     cpu_reserve = tcg_global_mem_new(TCG_AREG0,

   149                                      offsetof(CPUState, reserve), "reserve");

   150 

   151     cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,

   152                                        offsetof(CPUState, fpscr), "fpscr");

   153 

   154     cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,

   155                                              offsetof(CPUState, access_type), "access_type");

   156 

   157     /* register helpers */

   158 #define GEN_HELPER 2

   159 #include "helper.h"

   160 

   161     done_init = 1;

   162 }

   163 

   164 /* internal defines */

   165 typedef struct DisasContext {

   166     struct TranslationBlock *tb;

   167     target_ulong nip;

   168     uint32_t opcode;

   169     uint32_t exception;

   170     /* Routine used to access memory */

   171     int mem_idx;

   172     int access_type;

   173     /* Translation flags */

   174     int le_mode;

   175 #if defined(TARGET_PPC64)

   176     int sf_mode;

   177 #endif

   178     int fpu_enabled;

   179     int altivec_enabled;

   180     int spe_enabled;

   181     ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */

   182     int singlestep_enabled;

   183 } DisasContext;

   184 

   185 struct opc_handler_t {

   186     /* invalid bits */

   187     uint32_t inval;

   188     /* instruction type */

   189     uint64_t type;

   190     /* handler */

   191     void (*handler)(DisasContext *ctx);

   192 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)

   193     const char *oname;

   194 #endif

   195 #if defined(DO_PPC_STATISTICS)

   196     uint64_t count;

   197 #endif

   198 };

   199 

   200 static always_inline void gen_reset_fpstatus (void)

   201 {

   202 #ifdef CONFIG_SOFTFLOAT

   203     gen_helper_reset_fpstatus();

   204 #endif

   205 }

   206 

   207 static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_rc)

   208 {

   209     TCGv_i32 t0 = tcg_temp_new_i32();

   210 

   211     if (set_fprf != 0) {

   212         /* This case might be optimized later */

   213         tcg_gen_movi_i32(t0, 1);

   214         gen_helper_compute_fprf(t0, arg, t0);

   215         if (unlikely(set_rc)) {

   216             tcg_gen_mov_i32(cpu_crf[1], t0);

   217         }

   218         gen_helper_float_check_status();

   219     } else if (unlikely(set_rc)) {

   220         /* We always need to compute fpcc */

   221         tcg_gen_movi_i32(t0, 0);

   222         gen_helper_compute_fprf(t0, arg, t0);

   223         tcg_gen_mov_i32(cpu_crf[1], t0);

   224     }

   225 

   226     tcg_temp_free_i32(t0);

   227 }

   228 

   229 static always_inline void gen_set_access_type (DisasContext *ctx, int access_type)

   230 {

   231     if (ctx->access_type != access_type) {

   232         tcg_gen_movi_i32(cpu_access_type, access_type);

   233         ctx->access_type = access_type;

   234     }

   235 }

   236 

   237 static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)

   238 {

   239 #if defined(TARGET_PPC64)

   240     if (ctx->sf_mode)

   241         tcg_gen_movi_tl(cpu_nip, nip);

   242     else

   243 #endif

   244         tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);

   245 }

   246 

   247 static always_inline void gen_exception_err (DisasContext *ctx, uint32_t excp, uint32_t error)

   248 {

   249     TCGv_i32 t0, t1;

   250     if (ctx->exception == POWERPC_EXCP_NONE) {

   251         gen_update_nip(ctx, ctx->nip);

   252     }

   253     t0 = tcg_const_i32(excp);

   254     t1 = tcg_const_i32(error);

   255     gen_helper_raise_exception_err(t0, t1);

   256     tcg_temp_free_i32(t0);

   257     tcg_temp_free_i32(t1);

   258     ctx->exception = (excp);

   259 }

   260 

   261 static always_inline void gen_exception (DisasContext *ctx, uint32_t excp)

   262 {

   263     TCGv_i32 t0;

   264     if (ctx->exception == POWERPC_EXCP_NONE) {

   265         gen_update_nip(ctx, ctx->nip);

   266     }

   267     t0 = tcg_const_i32(excp);

   268     gen_helper_raise_exception(t0);

   269     tcg_temp_free_i32(t0);

   270     ctx->exception = (excp);

   271 }

   272 

   273 static always_inline void gen_debug_exception (DisasContext *ctx)

   274 {

   275     TCGv_i32 t0;

   276     gen_update_nip(ctx, ctx->nip);

   277     t0 = tcg_const_i32(EXCP_DEBUG);

   278     gen_helper_raise_exception(t0);

   279     tcg_temp_free_i32(t0);

   280 }

   281 

   282 static always_inline void gen_inval_exception (DisasContext *ctx, uint32_t error)

   283 {

   284     gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);

   285 }

   286 

   287 /* Stop translation */

   288 static always_inline void gen_stop_exception (DisasContext *ctx)

   289 {

   290     gen_update_nip(ctx, ctx->nip);

   291     ctx->exception = POWERPC_EXCP_STOP;

   292 }

   293 

   294 /* No need to update nip here, as execution flow will change */

   295 static always_inline void gen_sync_exception (DisasContext *ctx)

   296 {

   297     ctx->exception = POWERPC_EXCP_SYNC;

   298 }

   299 

   300 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                      \

   301 static void gen_##name (DisasContext *ctx);                                   \

   302 GEN_OPCODE(name, opc1, opc2, opc3, inval, type);                              \

   303 static void gen_##name (DisasContext *ctx)

   304 

   305 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type)               \

   306 static void gen_##name (DisasContext *ctx);                                   \

   307 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type);                       \

   308 static void gen_##name (DisasContext *ctx)

   309 

   310 typedef struct opcode_t {

   311     unsigned char opc1, opc2, opc3;

   312 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */

   313     unsigned char pad[5];

   314 #else

   315     unsigned char pad[1];

   316 #endif

   317     opc_handler_t handler;

   318     const char *oname;

   319 } opcode_t;

   320 

   321 /*****************************************************************************/

   322 /***                           Instruction decoding                        ***/

   323 #define EXTRACT_HELPER(name, shift, nb)                                       \

   324 static always_inline uint32_t name (uint32_t opcode)                          \

   325 {                                                                             \

   326     return (opcode >> (shift)) & ((1 << (nb)) - 1);                           \

   327 }

   328 

   329 #define EXTRACT_SHELPER(name, shift, nb)                                      \

   330 static always_inline int32_t name (uint32_t opcode)                           \

   331 {                                                                             \

   332     return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1));                \

   333 }

   334 

   335 /* Opcode part 1 */

   336 EXTRACT_HELPER(opc1, 26, 6);

   337 /* Opcode part 2 */

   338 EXTRACT_HELPER(opc2, 1, 5);

   339 /* Opcode part 3 */

   340 EXTRACT_HELPER(opc3, 6, 5);

   341 /* Update Cr0 flags */

   342 EXTRACT_HELPER(Rc, 0, 1);

   343 /* Destination */

   344 EXTRACT_HELPER(rD, 21, 5);

   345 /* Source */

   346 EXTRACT_HELPER(rS, 21, 5);

   347 /* First operand */

   348 EXTRACT_HELPER(rA, 16, 5);

   349 /* Second operand */

   350 EXTRACT_HELPER(rB, 11, 5);

   351 /* Third operand */

   352 EXTRACT_HELPER(rC, 6, 5);

   353 /***                               Get CRn                                 ***/

   354 EXTRACT_HELPER(crfD, 23, 3);

   355 EXTRACT_HELPER(crfS, 18, 3);

   356 EXTRACT_HELPER(crbD, 21, 5);

   357 EXTRACT_HELPER(crbA, 16, 5);

   358 EXTRACT_HELPER(crbB, 11, 5);

   359 /* SPR / TBL */

   360 EXTRACT_HELPER(_SPR, 11, 10);

   361 static always_inline uint32_t SPR (uint32_t opcode)

   362 {

   363     uint32_t sprn = _SPR(opcode);

   364 

   365     return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);

   366 }

   367 /***                              Get constants                            ***/

   368 EXTRACT_HELPER(IMM, 12, 8);

   369 /* 16 bits signed immediate value */

   370 EXTRACT_SHELPER(SIMM, 0, 16);

   371 /* 16 bits unsigned immediate value */

   372 EXTRACT_HELPER(UIMM, 0, 16);

   373 /* 5 bits signed immediate value */

   374 EXTRACT_HELPER(SIMM5, 16, 5);

   375 /* 5 bits unsigned immediate value */

   376 EXTRACT_HELPER(UIMM5, 16, 5);

   377 /* Bit count */

   378 EXTRACT_HELPER(NB, 11, 5);

   379 /* Shift count */

   380 EXTRACT_HELPER(SH, 11, 5);

   381 /* Vector shift count */

   382 EXTRACT_HELPER(VSH, 6, 4);

   383 /* Mask start */

   384 EXTRACT_HELPER(MB, 6, 5);

   385 /* Mask end */

   386 EXTRACT_HELPER(ME, 1, 5);

   387 /* Trap operand */

   388 EXTRACT_HELPER(TO, 21, 5);

   389 

   390 EXTRACT_HELPER(CRM, 12, 8);

   391 EXTRACT_HELPER(FM, 17, 8);

   392 EXTRACT_HELPER(SR, 16, 4);

   393 EXTRACT_HELPER(FPIMM, 12, 4);

   394 

   395 /***                            Jump target decoding                       ***/

   396 /* Displacement */

   397 EXTRACT_SHELPER(d, 0, 16);

   398 /* Immediate address */

   399 static always_inline target_ulong LI (uint32_t opcode)

   400 {

   401     return (opcode >> 0) & 0x03FFFFFC;

   402 }

   403 

   404 static always_inline uint32_t BD (uint32_t opcode)

   405 {

   406     return (opcode >> 0) & 0xFFFC;

   407 }

   408 

   409 EXTRACT_HELPER(BO, 21, 5);

   410 EXTRACT_HELPER(BI, 16, 5);

   411 /* Absolute/relative address */

   412 EXTRACT_HELPER(AA, 1, 1);

   413 /* Link */

   414 EXTRACT_HELPER(LK, 0, 1);

   415 

   416 /* Create a mask between <start> and <end> bits */

   417 static always_inline target_ulong MASK (uint32_t start, uint32_t end)

   418 {

   419     target_ulong ret;

   420 

   421 #if defined(TARGET_PPC64)

   422     if (likely(start == 0)) {

   423         ret = UINT64_MAX << (63 - end);

   424     } else if (likely(end == 63)) {

   425         ret = UINT64_MAX >> start;

   426     }

   427 #else

   428     if (likely(start == 0)) {

   429         ret = UINT32_MAX << (31  - end);

   430     } else if (likely(end == 31)) {

   431         ret = UINT32_MAX >> start;

   432     }

   433 #endif

   434     else {

   435         ret = (((target_ulong)(-1ULL)) >> (start)) ^

   436             (((target_ulong)(-1ULL) >> (end)) >> 1);

   437         if (unlikely(start > end))

   438             return ~ret;

   439     }

   440 

   441     return ret;

   442 }

   443 

   444 /*****************************************************************************/

   445 /* PowerPC Instructions types definitions                                    */

   446 enum {

   447     PPC_NONE           = 0x0000000000000000ULL,

   448     /* PowerPC base instructions set                                         */

   449     PPC_INSNS_BASE     = 0x0000000000000001ULL,

   450     /*   integer operations instructions                                     */

   451 #define PPC_INTEGER PPC_INSNS_BASE

   452     /*   flow control instructions                                           */

   453 #define PPC_FLOW    PPC_INSNS_BASE

   454     /*   virtual memory instructions                                         */

   455 #define PPC_MEM     PPC_INSNS_BASE

   456     /*   ld/st with reservation instructions                                 */

   457 #define PPC_RES     PPC_INSNS_BASE

   458     /*   spr/msr access instructions                                         */

   459 #define PPC_MISC    PPC_INSNS_BASE

   460     /* Deprecated instruction sets                                           */

   461     /*   Original POWER instruction set                                      */

   462     PPC_POWER          = 0x0000000000000002ULL,

   463     /*   POWER2 instruction set extension                                    */

   464     PPC_POWER2         = 0x0000000000000004ULL,

   465     /*   Power RTC support                                                   */

   466     PPC_POWER_RTC      = 0x0000000000000008ULL,

   467     /*   Power-to-PowerPC bridge (601)                                       */

   468     PPC_POWER_BR       = 0x0000000000000010ULL,

   469     /* 64 bits PowerPC instruction set                                       */

   470     PPC_64B            = 0x0000000000000020ULL,

   471     /*   New 64 bits extensions (PowerPC 2.0x)                               */

   472     PPC_64BX           = 0x0000000000000040ULL,

   473     /*   64 bits hypervisor extensions                                       */

   474     PPC_64H            = 0x0000000000000080ULL,

   475     /*   New wait instruction (PowerPC 2.0x)                                 */

   476     PPC_WAIT           = 0x0000000000000100ULL,

   477     /*   Time base mftb instruction                                          */

   478     PPC_MFTB           = 0x0000000000000200ULL,

   479 

   480     /* Fixed-point unit extensions                                           */

   481     /*   PowerPC 602 specific                                                */

   482     PPC_602_SPEC       = 0x0000000000000400ULL,

   483     /*   isel instruction                                                    */

   484     PPC_ISEL           = 0x0000000000000800ULL,

   485     /*   popcntb instruction                                                 */

   486     PPC_POPCNTB        = 0x0000000000001000ULL,

   487     /*   string load / store                                                 */

   488     PPC_STRING         = 0x0000000000002000ULL,

   489 

   490     /* Floating-point unit extensions                                        */

   491     /*   Optional floating point instructions                                */

   492     PPC_FLOAT          = 0x0000000000010000ULL,

   493     /* New floating-point extensions (PowerPC 2.0x)                          */

   494     PPC_FLOAT_EXT      = 0x0000000000020000ULL,

   495     PPC_FLOAT_FSQRT    = 0x0000000000040000ULL,

   496     PPC_FLOAT_FRES     = 0x0000000000080000ULL,

   497     PPC_FLOAT_FRSQRTE  = 0x0000000000100000ULL,

   498     PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,

   499     PPC_FLOAT_FSEL     = 0x0000000000400000ULL,

   500     PPC_FLOAT_STFIWX   = 0x0000000000800000ULL,

   501 

   502     /* Vector/SIMD extensions                                                */

   503     /*   Altivec support                                                     */

   504     PPC_ALTIVEC        = 0x0000000001000000ULL,

   505     /*   PowerPC 2.03 SPE extension                                          */

   506     PPC_SPE            = 0x0000000002000000ULL,

   507     /*   PowerPC 2.03 SPE floating-point extension                           */

   508     PPC_SPEFPU         = 0x0000000004000000ULL,

   509 

   510     /* Optional memory control instructions                                  */

   511     PPC_MEM_TLBIA      = 0x0000000010000000ULL,

   512     PPC_MEM_TLBIE      = 0x0000000020000000ULL,

   513     PPC_MEM_TLBSYNC    = 0x0000000040000000ULL,

   514     /*   sync instruction                                                    */

   515     PPC_MEM_SYNC       = 0x0000000080000000ULL,

   516     /*   eieio instruction                                                   */

   517     PPC_MEM_EIEIO      = 0x0000000100000000ULL,

   518 

   519     /* Cache control instructions                                            */

   520     PPC_CACHE          = 0x0000000200000000ULL,

   521     /*   icbi instruction                                                    */

   522     PPC_CACHE_ICBI     = 0x0000000400000000ULL,

   523     /*   dcbz instruction with fixed cache line size                         */

   524     PPC_CACHE_DCBZ     = 0x0000000800000000ULL,

   525     /*   dcbz instruction with tunable cache line size                       */

   526     PPC_CACHE_DCBZT    = 0x0000001000000000ULL,

   527     /*   dcba instruction                                                    */

   528     PPC_CACHE_DCBA     = 0x0000002000000000ULL,

   529     /*   Freescale cache locking instructions                                */

   530     PPC_CACHE_LOCK     = 0x0000004000000000ULL,

   531 

   532     /* MMU related extensions                                                */

   533     /*   external control instructions                                       */

   534     PPC_EXTERN         = 0x0000010000000000ULL,

   535     /*   segment register access instructions                                */

   536     PPC_SEGMENT        = 0x0000020000000000ULL,

   537     /*   PowerPC 6xx TLB management instructions                             */

   538     PPC_6xx_TLB        = 0x0000040000000000ULL,

   539     /* PowerPC 74xx TLB management instructions                              */

   540     PPC_74xx_TLB       = 0x0000080000000000ULL,

   541     /*   PowerPC 40x TLB management instructions                             */

   542     PPC_40x_TLB        = 0x0000100000000000ULL,

   543     /*   segment register access instructions for PowerPC 64 "bridge"        */

   544     PPC_SEGMENT_64B    = 0x0000200000000000ULL,

   545     /*   SLB management                                                      */

   546     PPC_SLBI           = 0x0000400000000000ULL,

   547 

   548     /* Embedded PowerPC dedicated instructions                               */

   549     PPC_WRTEE          = 0x0001000000000000ULL,

   550     /* PowerPC 40x exception model                                           */

   551     PPC_40x_EXCP       = 0x0002000000000000ULL,

   552     /* PowerPC 405 Mac instructions                                          */

   553     PPC_405_MAC        = 0x0004000000000000ULL,

   554     /* PowerPC 440 specific instructions                                     */

   555     PPC_440_SPEC       = 0x0008000000000000ULL,

   556     /* BookE (embedded) PowerPC specification                                */

   557     PPC_BOOKE          = 0x0010000000000000ULL,

   558     /* mfapidi instruction                                                   */

   559     PPC_MFAPIDI        = 0x0020000000000000ULL,

   560     /* tlbiva instruction                                                    */

   561     PPC_TLBIVA         = 0x0040000000000000ULL,

   562     /* tlbivax instruction                                                   */

   563     PPC_TLBIVAX        = 0x0080000000000000ULL,

   564     /* PowerPC 4xx dedicated instructions                                    */

   565     PPC_4xx_COMMON     = 0x0100000000000000ULL,

   566     /* PowerPC 40x ibct instructions                                         */

   567     PPC_40x_ICBT       = 0x0200000000000000ULL,

   568     /* rfmci is not implemented in all BookE PowerPC                         */

   569     PPC_RFMCI          = 0x0400000000000000ULL,

   570     /* rfdi instruction                                                      */

   571     PPC_RFDI           = 0x0800000000000000ULL,

   572     /* DCR accesses                                                          */

   573     PPC_DCR            = 0x1000000000000000ULL,

   574     /* DCR extended accesse                                                  */

   575     PPC_DCRX           = 0x2000000000000000ULL,

   576     /* user-mode DCR access, implemented in PowerPC 460                      */

   577     PPC_DCRUX          = 0x4000000000000000ULL,

   578 };

   579 

   580 /*****************************************************************************/

   581 /* PowerPC instructions table                                                */

   582 #if HOST_LONG_BITS == 64

   583 #define OPC_ALIGN 8

   584 #else

   585 #define OPC_ALIGN 4

   586 #endif

   587 #if defined(__APPLE__)

   588 #define OPCODES_SECTION                                                       \

   589     __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))

   590 #else

   591 #define OPCODES_SECTION                                                       \

   592     __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))

   593 #endif

   594 

   595 #if defined(DO_PPC_STATISTICS)

   596 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ)                           \

   597 OPCODES_SECTION opcode_t opc_##name = {                                       \

   598     .opc1 = op1,                                                              \

   599     .opc2 = op2,                                                              \

   600     .opc3 = op3,                                                              \

   601     .pad  = { 0, },                                                           \

   602     .handler = {                                                              \

   603         .inval   = invl,                                                      \

   604         .type = _typ,                                                         \

   605         .handler = &gen_##name,                                               \

   606         .oname = stringify(name),                                             \

   607     },                                                                        \

   608     .oname = stringify(name),                                                 \

   609 }

   610 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ)                    \

   611 OPCODES_SECTION opcode_t opc_##name = {                                       \

   612     .opc1 = op1,                                                              \

   613     .opc2 = op2,                                                              \

   614     .opc3 = op3,                                                              \

   615     .pad  = { 0, },                                                           \

   616     .handler = {                                                              \

   617         .inval   = invl,                                                      \

   618         .type = _typ,                                                         \

   619         .handler = &gen_##name,                                               \

   620         .oname = onam,                                                        \

   621     },                                                                        \

   622     .oname = onam,                                                            \

   623 }

   624 #else

   625 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ)                           \

   626 OPCODES_SECTION opcode_t opc_##name = {                                       \

   627     .opc1 = op1,                                                              \

   628     .opc2 = op2,                                                              \

   629     .opc3 = op3,                                                              \

   630     .pad  = { 0, },                                                           \

   631     .handler = {                                                              \

   632         .inval   = invl,                                                      \

   633         .type = _typ,                                                         \

   634         .handler = &gen_##name,                                               \

   635     },                                                                        \

   636     .oname = stringify(name),                                                 \

   637 }

   638 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ)                    \

   639 OPCODES_SECTION opcode_t opc_##name = {                                       \

   640     .opc1 = op1,                                                              \

   641     .opc2 = op2,                                                              \

   642     .opc3 = op3,                                                              \

   643     .pad  = { 0, },                                                           \

   644     .handler = {                                                              \

   645         .inval   = invl,                                                      \

   646         .type = _typ,                                                         \

   647         .handler = &gen_##name,                                               \

   648     },                                                                        \

   649     .oname = onam,                                                            \

   650 }

   651 #endif

   652 

   653 #define GEN_OPCODE_MARK(name)                                                 \

   654 OPCODES_SECTION opcode_t opc_##name = {                                       \

   655     .opc1 = 0xFF,                                                             \

   656     .opc2 = 0xFF,                                                             \

   657     .opc3 = 0xFF,                                                             \

   658     .pad  = { 0, },                                                           \

   659     .handler = {                                                              \

   660         .inval   = 0x00000000,                                                \

   661         .type = 0x00,                                                         \

   662         .handler = NULL,                                                      \

   663     },                                                                        \

   664     .oname = stringify(name),                                                 \

   665 }

   666 

   667 /* SPR load/store helpers */

   668 static always_inline void gen_load_spr(TCGv t, int reg)

   669 {

   670     tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, spr[reg]));

   671 }

   672 

   673 static always_inline void gen_store_spr(int reg, TCGv t)

   674 {

   675     tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, spr[reg]));

   676 }

   677 

   678 /* Start opcode list */

   679 GEN_OPCODE_MARK(start);

   680 

   681 /* Invalid instruction */

   682 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)

   683 {

   684     gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);

   685 }

   686 

   687 static opc_handler_t invalid_handler = {

   688     .inval   = 0xFFFFFFFF,

   689     .type    = PPC_NONE,

   690     .handler = gen_invalid,

   691 };

   692 

   693 /***                           Integer comparison                          ***/

   694 

   695 static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)

   696 {

   697     int l1, l2, l3;

   698 

   699     tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);

   700     tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);

   701     tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);

   702 

   703     l1 = gen_new_label();

   704     l2 = gen_new_label();

   705     l3 = gen_new_label();

   706     if (s) {

   707         tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);

   708         tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);

   709     } else {

   710         tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);

   711         tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);

   712     }

   713     tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);

   714     tcg_gen_br(l3);

   715     gen_set_label(l1);

   716     tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);

   717     tcg_gen_br(l3);

   718     gen_set_label(l2);

   719     tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);

   720     gen_set_label(l3);

   721 }

   722 

   723 static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)

   724 {

   725     TCGv t0 = tcg_const_local_tl(arg1);

   726     gen_op_cmp(arg0, t0, s, crf);

   727     tcg_temp_free(t0);

   728 }

   729 

   730 #if defined(TARGET_PPC64)

   731 static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)

   732 {

   733     TCGv t0, t1;

   734     t0 = tcg_temp_local_new();

   735     t1 = tcg_temp_local_new();

   736     if (s) {

   737         tcg_gen_ext32s_tl(t0, arg0);

   738         tcg_gen_ext32s_tl(t1, arg1);

   739     } else {

   740         tcg_gen_ext32u_tl(t0, arg0);

   741         tcg_gen_ext32u_tl(t1, arg1);

   742     }

   743     gen_op_cmp(t0, t1, s, crf);

   744     tcg_temp_free(t1);

   745     tcg_temp_free(t0);

   746 }

   747 

   748 static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)

   749 {

   750     TCGv t0 = tcg_const_local_tl(arg1);

   751     gen_op_cmp32(arg0, t0, s, crf);

   752     tcg_temp_free(t0);

   753 }

   754 #endif

   755 

   756 static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg)

   757 {

   758 #if defined(TARGET_PPC64)

   759     if (!(ctx->sf_mode))

   760         gen_op_cmpi32(reg, 0, 1, 0);

   761     else

   762 #endif

   763         gen_op_cmpi(reg, 0, 1, 0);

   764 }

   765 

   766 /* cmp */

   767 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER)

   768 {

   769 #if defined(TARGET_PPC64)

   770     if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))

   771         gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],

   772                      1, crfD(ctx->opcode));

   773     else

   774 #endif

   775         gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],

   776                    1, crfD(ctx->opcode));

   777 }

   778 

   779 /* cmpi */

   780 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)

   781 {

   782 #if defined(TARGET_PPC64)

   783     if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))

   784         gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),

   785                       1, crfD(ctx->opcode));

   786     else

   787 #endif

   788         gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),

   789                     1, crfD(ctx->opcode));

   790 }

   791 

   792 /* cmpl */

   793 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER)

   794 {

   795 #if defined(TARGET_PPC64)

   796     if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))

   797         gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],

   798                      0, crfD(ctx->opcode));

   799     else

   800 #endif

   801         gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],

   802                    0, crfD(ctx->opcode));

   803 }

   804 

   805 /* cmpli */

   806 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)

   807 {

   808 #if defined(TARGET_PPC64)

   809     if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))

   810         gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),

   811                       0, crfD(ctx->opcode));

   812     else

   813 #endif

   814         gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),

   815                     0, crfD(ctx->opcode));

   816 }

   817 

   818 /* isel (PowerPC 2.03 specification) */

   819 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)

   820 {

   821     int l1, l2;

   822     uint32_t bi = rC(ctx->opcode);

   823     uint32_t mask;

   824     TCGv_i32 t0;

   825 

   826     l1 = gen_new_label();

   827     l2 = gen_new_label();

   828 

   829     mask = 1 << (3 - (bi & 0x03));

   830     t0 = tcg_temp_new_i32();

   831     tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);

   832     tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);

   833     if (rA(ctx->opcode) == 0)

   834         tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);

   835     else

   836         tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);

   837     tcg_gen_br(l2);

   838     gen_set_label(l1);

   839     tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);

   840     gen_set_label(l2);

   841     tcg_temp_free_i32(t0);

   842 }

   843 

   844 /***                           Integer arithmetic                          ***/

   845 

   846 static always_inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, TCGv arg1, TCGv arg2, int sub)

   847 {

   848     int l1;

   849     TCGv t0;

   850 

   851     l1 = gen_new_label();

   852     /* Start with XER OV disabled, the most likely case */

   853     tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));

   854     t0 = tcg_temp_local_new();

   855     tcg_gen_xor_tl(t0, arg0, arg1);

   856 #if defined(TARGET_PPC64)

   857     if (!ctx->sf_mode)

   858         tcg_gen_ext32s_tl(t0, t0);

   859 #endif

   860     if (sub)

   861         tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);

   862     else

   863         tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);

   864     tcg_gen_xor_tl(t0, arg1, arg2);

   865 #if defined(TARGET_PPC64)

   866     if (!ctx->sf_mode)

   867         tcg_gen_ext32s_tl(t0, t0);

   868 #endif

   869     if (sub)

   870         tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);

   871     else

   872         tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);

   873     tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));

   874     gen_set_label(l1);

   875     tcg_temp_free(t0);

   876 }

   877 

   878 static always_inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, TCGv arg2, int sub)

   879 {

   880     int l1 = gen_new_label();

   881 

   882 #if defined(TARGET_PPC64)

   883     if (!(ctx->sf_mode)) {

   884         TCGv t0, t1;

   885         t0 = tcg_temp_new();

   886         t1 = tcg_temp_new();

   887 

   888         tcg_gen_ext32u_tl(t0, arg1);

   889         tcg_gen_ext32u_tl(t1, arg2);

   890         if (sub) {

   891             tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);

   892         } else {

   893             tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);

   894         }

   895         tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);

   896         gen_set_label(l1);

   897         tcg_temp_free(t0);

   898         tcg_temp_free(t1);

   899     } else

   900 #endif

   901     {

   902         if (sub) {

   903             tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);

   904         } else {

   905             tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);

   906         }

   907         tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);

   908         gen_set_label(l1);

   909     }

   910 }

   911 

   912 /* Common add function */

   913 static always_inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,

   914                                            int add_ca, int compute_ca, int compute_ov)

   915 {

   916     TCGv t0, t1;

   917 

   918     if ((!compute_ca && !compute_ov) ||

   919         (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2)))  {

   920         t0 = ret;

   921     } else {

   922         t0 = tcg_temp_local_new();

   923     }

   924 

   925     if (add_ca) {

   926         t1 = tcg_temp_local_new();

   927         tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));

   928         tcg_gen_shri_tl(t1, t1, XER_CA);

   929     }

   930 

   931     if (compute_ca && compute_ov) {

   932         /* Start with XER CA and OV disabled, the most likely case */

   933         tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));

   934     } else if (compute_ca) {

   935         /* Start with XER CA disabled, the most likely case */

   936         tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));

   937     } else if (compute_ov) {

   938         /* Start with XER OV disabled, the most likely case */

   939         tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));

   940     }

   941 

   942     tcg_gen_add_tl(t0, arg1, arg2);

   943 

   944     if (compute_ca) {

   945         gen_op_arith_compute_ca(ctx, t0, arg1, 0);

   946     }

   947     if (add_ca) {

   948         tcg_gen_add_tl(t0, t0, t1);

   949         gen_op_arith_compute_ca(ctx, t0, t1, 0);

   950         tcg_temp_free(t1);

   951     }

   952     if (compute_ov) {

   953         gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);

   954     }

   955 

   956     if (unlikely(Rc(ctx->opcode) != 0))

   957         gen_set_Rc0(ctx, t0);

   958 

   959     if (!TCGV_EQUAL(t0, ret)) {

   960         tcg_gen_mov_tl(ret, t0);

   961         tcg_temp_free(t0);

   962     }

   963 }

   964 /* Add functions with two operands */

   965 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov)         \

   966 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER)                  \

   967 {                                                                             \

   968     gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)],                           \

   969                      cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],      \

   970                      add_ca, compute_ca, compute_ov);                         \

   971 }

   972 /* Add functions with one operand and one immediate */

   973 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val,                        \

   974                                 add_ca, compute_ca, compute_ov)               \

   975 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER)                  \

   976 {                                                                             \

   977     TCGv t0 = tcg_const_local_tl(const_val);                                  \

   978     gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)],                           \

   979                      cpu_gpr[rA(ctx->opcode)], t0,                            \

   980                      add_ca, compute_ca, compute_ov);                         \

   981     tcg_temp_free(t0);                                                        \

   982 }

   983 

   984 /* add  add.  addo  addo. */

   985 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)

   986 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)

   987 /* addc  addc.  addco  addco. */

   988 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)

   989 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)

   990 /* adde  adde.  addeo  addeo. */

   991 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)

   992 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)

   993 /* addme  addme.  addmeo  addmeo.  */

   994 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)

   995 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)

   996 /* addze  addze.  addzeo  addzeo.*/

   997 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)

   998 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)

   999 /* addi */

  1000 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)

  1001 {

  1002     target_long simm = SIMM(ctx->opcode);

  1003 

  1004     if (rA(ctx->opcode) == 0) {

  1005         /* li case */

  1006         tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);

  1007     } else {

  1008         tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);

  1009     }

  1010 }

  1011 /* addic  addic.*/

  1012 static always_inline void gen_op_addic (DisasContext *ctx, TCGv ret, TCGv arg1,

  1013                                         int compute_Rc0)

  1014 {

  1015     target_long simm = SIMM(ctx->opcode);

  1016 

  1017     /* Start with XER CA and OV disabled, the most likely case */

  1018     tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));

  1019 

  1020     if (likely(simm != 0)) {

  1021         TCGv t0 = tcg_temp_local_new();

  1022         tcg_gen_addi_tl(t0, arg1, simm);

  1023         gen_op_arith_compute_ca(ctx, t0, arg1, 0);

  1024         tcg_gen_mov_tl(ret, t0);

  1025         tcg_temp_free(t0);

  1026     } else {

  1027         tcg_gen_mov_tl(ret, arg1);

  1028     }

  1029     if (compute_Rc0) {

  1030         gen_set_Rc0(ctx, ret);

  1031     }

  1032 }

  1033 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)

  1034 {

  1035     gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);

  1036 }

  1037 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)

  1038 {

  1039     gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);

  1040 }

  1041 /* addis */

  1042 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)

  1043 {

  1044     target_long simm = SIMM(ctx->opcode);

  1045 

  1046     if (rA(ctx->opcode) == 0) {

  1047         /* lis case */

  1048         tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);

  1049     } else {

  1050         tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);

  1051     }

  1052 }

  1053 

  1054 static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,

  1055                                              int sign, int compute_ov)

  1056 {

  1057     int l1 = gen_new_label();

  1058     int l2 = gen_new_label();

  1059     TCGv_i32 t0 = tcg_temp_local_new_i32();

  1060     TCGv_i32 t1 = tcg_temp_local_new_i32();

  1061 

  1062     tcg_gen_trunc_tl_i32(t0, arg1);

  1063     tcg_gen_trunc_tl_i32(t1, arg2);

  1064     tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);

  1065     if (sign) {

  1066         int l3 = gen_new_label();

  1067         tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);

  1068         tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);

  1069         gen_set_label(l3);

  1070         tcg_gen_div_i32(t0, t0, t1);

  1071     } else {

  1072         tcg_gen_divu_i32(t0, t0, t1);

  1073     }

  1074     if (compute_ov) {

  1075         tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));

  1076     }

  1077     tcg_gen_br(l2);

  1078     gen_set_label(l1);

  1079     if (sign) {

  1080         tcg_gen_sari_i32(t0, t0, 31);

  1081     } else {

  1082         tcg_gen_movi_i32(t0, 0);

  1083     }

  1084     if (compute_ov) {

  1085         tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));

  1086     }

  1087     gen_set_label(l2);

  1088     tcg_gen_extu_i32_tl(ret, t0);

  1089     tcg_temp_free_i32(t0);

  1090     tcg_temp_free_i32(t1);

  1091     if (unlikely(Rc(ctx->opcode) != 0))

  1092         gen_set_Rc0(ctx, ret);

  1093 }

  1094 /* Div functions */

  1095 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov)                      \

  1096 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)                  \

  1097 {                                                                             \

  1098     gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)],                          \

  1099                      cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],      \

  1100                      sign, compute_ov);                                       \

  1101 }

  1102 /* divwu  divwu.  divwuo  divwuo.   */

  1103 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);

  1104 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);

  1105 /* divw  divw.  divwo  divwo.   */

  1106 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);

  1107 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);

  1108 #if defined(TARGET_PPC64)

  1109 static always_inline void gen_op_arith_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,

  1110                                              int sign, int compute_ov)

  1111 {

  1112     int l1 = gen_new_label();

  1113     int l2 = gen_new_label();

  1114 

  1115     tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);

  1116     if (sign) {

  1117         int l3 = gen_new_label();

  1118         tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);

  1119         tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);

  1120         gen_set_label(l3);

  1121         tcg_gen_div_i64(ret, arg1, arg2);

  1122     } else {

  1123         tcg_gen_divu_i64(ret, arg1, arg2);

  1124     }

  1125     if (compute_ov) {

  1126         tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));

  1127     }

  1128     tcg_gen_br(l2);

  1129     gen_set_label(l1);

  1130     if (sign) {

  1131         tcg_gen_sari_i64(ret, arg1, 63);

  1132     } else {

  1133         tcg_gen_movi_i64(ret, 0);

  1134     }

  1135     if (compute_ov) {