1 /*

     2  *  PowerPC CPU initialization for qemu.

     3  *

     4  *  Copyright (c) 2003-2007 Jocelyn Mayer

     5  *

     6  * This library is free software; you can redistribute it and/or

     7  * modify it under the terms of the GNU Lesser General Public

     8  * License as published by the Free Software Foundation; either

     9  * version 2 of the License, or (at your option) any later version.

    10  *

    11  * This library is distributed in the hope that it will be useful,

    12  * but WITHOUT ANY WARRANTY; without even the implied warranty of

    13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

    14  * Lesser General Public License for more details.

    15  *

    16  * You should have received a copy of the GNU Lesser General Public

    17  * License along with this library; if not, write to the Free Software

    18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

    19  */

    20 

    21 /* A lot of PowerPC definition have been included here.

    22  * Most of them are not usable for now but have been kept

    23  * inside "#if defined(TODO) ... #endif" statements to make tests easier.

    24  */

    25 

    26 #include "dis-asm.h"

    27 #include "host-utils.h"

    28 

    29 //#define PPC_DUMP_CPU

    30 //#define PPC_DEBUG_SPR

    31 //#define PPC_DUMP_SPR_ACCESSES

    32 #if defined(CONFIG_USER_ONLY)

    33 #define TODO_USER_ONLY 1

    34 #endif

    35 

    36 struct ppc_def_t {

    37     const char *name;

    38     uint32_t pvr;

    39     uint32_t svr;

    40     uint64_t insns_flags;

    41     uint64_t msr_mask;

    42     powerpc_mmu_t   mmu_model;

    43     powerpc_excp_t  excp_model;

    44     powerpc_input_t bus_model;

    45     uint32_t flags;

    46     int bfd_mach;

    47     void (*init_proc)(CPUPPCState *env);

    48     int  (*check_pow)(CPUPPCState *env);

    49 };

    50 

    51 /* For user-mode emulation, we don't emulate any IRQ controller */

    52 #if defined(CONFIG_USER_ONLY)

    53 #define PPC_IRQ_INIT_FN(name)                                                 \

    54 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env)         \

    55 {                                                                             \

    56 }

    57 #else

    58 #define PPC_IRQ_INIT_FN(name)                                                 \

    59 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);

    60 #endif

    61 

    62 PPC_IRQ_INIT_FN(40x);

    63 PPC_IRQ_INIT_FN(6xx);

    64 PPC_IRQ_INIT_FN(970);

    65 

    66 /* Generic callbacks:

    67  * do nothing but store/retrieve spr value

    68  */

    69 static void spr_read_generic (void *opaque, int gprn, int sprn)

    70 {

    71     gen_load_spr(cpu_gpr[gprn], sprn);

    72 #ifdef PPC_DUMP_SPR_ACCESSES

    73     {

    74         TCGv t0 = tcg_const_i32(sprn);

    75         gen_helper_load_dump_spr(t0);

    76         tcg_temp_free_i32(t0);

    77     }

    78 #endif

    79 }

    80 

    81 static void spr_write_generic (void *opaque, int sprn, int gprn)

    82 {

    83     gen_store_spr(sprn, cpu_gpr[gprn]);

    84 #ifdef PPC_DUMP_SPR_ACCESSES

    85     {

    86         TCGv t0 = tcg_const_i32(sprn);

    87         gen_helper_store_dump_spr(t0);

    88         tcg_temp_free_i32(t0);

    89     }

    90 #endif

    91 }

    92 

    93 #if !defined(CONFIG_USER_ONLY)

    94 static void spr_write_clear (void *opaque, int sprn, int gprn)

    95 {

    96     TCGv t0 = tcg_temp_new();

    97     TCGv t1 = tcg_temp_new();

    98     gen_load_spr(t0, sprn);

    99     tcg_gen_neg_tl(t1, cpu_gpr[gprn]);

   100     tcg_gen_and_tl(t0, t0, t1);

   101     gen_store_spr(sprn, t0);

   102     tcg_temp_free(t0);

   103     tcg_temp_free(t1);

   104 }

   105 #endif

   106 

   107 /* SPR common to all PowerPC */

   108 /* XER */

   109 static void spr_read_xer (void *opaque, int gprn, int sprn)

   110 {

   111     tcg_gen_mov_tl(cpu_gpr[gprn], cpu_xer);

   112 }

   113 

   114 static void spr_write_xer (void *opaque, int sprn, int gprn)

   115 {

   116     tcg_gen_mov_tl(cpu_xer, cpu_gpr[gprn]);

   117 }

   118 

   119 /* LR */

   120 static void spr_read_lr (void *opaque, int gprn, int sprn)

   121 {

   122     tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);

   123 }

   124 

   125 static void spr_write_lr (void *opaque, int sprn, int gprn)

   126 {

   127     tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);

   128 }

   129 

   130 /* CTR */

   131 static void spr_read_ctr (void *opaque, int gprn, int sprn)

   132 {

   133     tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);

   134 }

   135 

   136 static void spr_write_ctr (void *opaque, int sprn, int gprn)

   137 {

   138     tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);

   139 }

   140 

   141 /* User read access to SPR */

   142 /* USPRx */

   143 /* UMMCRx */

   144 /* UPMCx */

   145 /* USIA */

   146 /* UDECR */

   147 static void spr_read_ureg (void *opaque, int gprn, int sprn)

   148 {

   149     gen_load_spr(cpu_gpr[gprn], sprn + 0x10);

   150 }

   151 

   152 /* SPR common to all non-embedded PowerPC */

   153 /* DECR */

   154 #if !defined(CONFIG_USER_ONLY)

   155 static void spr_read_decr (void *opaque, int gprn, int sprn)

   156 {

   157     gen_helper_load_decr(cpu_gpr[gprn]);

   158 }

   159 

   160 static void spr_write_decr (void *opaque, int sprn, int gprn)

   161 {

   162     gen_helper_store_decr(cpu_gpr[gprn]);

   163 }

   164 #endif

   165 

   166 /* SPR common to all non-embedded PowerPC, except 601 */

   167 /* Time base */

   168 static void spr_read_tbl (void *opaque, int gprn, int sprn)

   169 {

   170     gen_helper_load_tbl(cpu_gpr[gprn]);

   171 }

   172 

   173 static void spr_read_tbu (void *opaque, int gprn, int sprn)

   174 {

   175     gen_helper_load_tbu(cpu_gpr[gprn]);

   176 }

   177 

   178 __attribute__ (( unused ))

   179 static void spr_read_atbl (void *opaque, int gprn, int sprn)

   180 {

   181     gen_helper_load_atbl(cpu_gpr[gprn]);

   182 }

   183 

   184 __attribute__ (( unused ))

   185 static void spr_read_atbu (void *opaque, int gprn, int sprn)

   186 {

   187     gen_helper_load_atbu(cpu_gpr[gprn]);

   188 }

   189 

   190 #if !defined(CONFIG_USER_ONLY)

   191 static void spr_write_tbl (void *opaque, int sprn, int gprn)

   192 {

   193     gen_helper_store_tbl(cpu_gpr[gprn]);

   194 }

   195 

   196 static void spr_write_tbu (void *opaque, int sprn, int gprn)

   197 {

   198     gen_helper_store_tbu(cpu_gpr[gprn]);

   199 }

   200 

   201 __attribute__ (( unused ))

   202 static void spr_write_atbl (void *opaque, int sprn, int gprn)

   203 {

   204     gen_helper_store_atbl(cpu_gpr[gprn]);

   205 }

   206 

   207 __attribute__ (( unused ))

   208 static void spr_write_atbu (void *opaque, int sprn, int gprn)

   209 {

   210     gen_helper_store_atbu(cpu_gpr[gprn]);

   211 }

   212 #endif

   213 

   214 #if !defined(CONFIG_USER_ONLY)

   215 /* IBAT0U...IBAT0U */

   216 /* IBAT0L...IBAT7L */

   217 static void spr_read_ibat (void *opaque, int gprn, int sprn)

   218 {

   219     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));

   220 }

   221 

   222 static void spr_read_ibat_h (void *opaque, int gprn, int sprn)

   223 {

   224     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));

   225 }

   226 

   227 static void spr_write_ibatu (void *opaque, int sprn, int gprn)

   228 {

   229     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);

   230     gen_helper_store_ibatu(t0, cpu_gpr[gprn]);

   231     tcg_temp_free_i32(t0);

   232 }

   233 

   234 static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)

   235 {

   236     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT4U) / 2);

   237     gen_helper_store_ibatu(t0, cpu_gpr[gprn]);

   238     tcg_temp_free_i32(t0);

   239 }

   240 

   241 static void spr_write_ibatl (void *opaque, int sprn, int gprn)

   242 {

   243     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);

   244     gen_helper_store_ibatl(t0, cpu_gpr[gprn]);

   245     tcg_temp_free_i32(t0);

   246 }

   247 

   248 static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)

   249 {

   250     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT4L) / 2);

   251     gen_helper_store_ibatl(t0, cpu_gpr[gprn]);

   252     tcg_temp_free_i32(t0);

   253 }

   254 

   255 /* DBAT0U...DBAT7U */

   256 /* DBAT0L...DBAT7L */

   257 static void spr_read_dbat (void *opaque, int gprn, int sprn)

   258 {

   259     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));

   260 }

   261 

   262 static void spr_read_dbat_h (void *opaque, int gprn, int sprn)

   263 {

   264     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));

   265 }

   266 

   267 static void spr_write_dbatu (void *opaque, int sprn, int gprn)

   268 {

   269     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);

   270     gen_helper_store_dbatu(t0, cpu_gpr[gprn]);

   271     tcg_temp_free_i32(t0);

   272 }

   273 

   274 static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)

   275 {

   276     TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);

   277     gen_helper_store_dbatu(t0, cpu_gpr[gprn]);

   278     tcg_temp_free_i32(t0);

   279 }

   280 

   281 static void spr_write_dbatl (void *opaque, int sprn, int gprn)

   282 {

   283     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);

   284     gen_helper_store_dbatl(t0, cpu_gpr[gprn]);

   285     tcg_temp_free_i32(t0);

   286 }

   287 

   288 static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)

   289 {

   290     TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);

   291     gen_helper_store_dbatl(t0, cpu_gpr[gprn]);

   292     tcg_temp_free_i32(t0);

   293 }

   294 

   295 /* SDR1 */

   296 static void spr_read_sdr1 (void *opaque, int gprn, int sprn)

   297 {

   298     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, sdr1));

   299 }

   300 

   301 static void spr_write_sdr1 (void *opaque, int sprn, int gprn)

   302 {

   303     gen_helper_store_sdr1(cpu_gpr[gprn]);

   304 }

   305 

   306 /* 64 bits PowerPC specific SPRs */

   307 /* ASR */

   308 #if defined(TARGET_PPC64)

   309 static void spr_read_asr (void *opaque, int gprn, int sprn)

   310 {

   311     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, asr));

   312 }

   313 

   314 static void spr_write_asr (void *opaque, int sprn, int gprn)

   315 {

   316     gen_helper_store_asr(cpu_gpr[gprn]);

   317 }

   318 #endif

   319 #endif

   320 

   321 /* PowerPC 601 specific registers */

   322 /* RTC */

   323 static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)

   324 {

   325     gen_helper_load_601_rtcl(cpu_gpr[gprn]);

   326 }

   327 

   328 static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)

   329 {

   330     gen_helper_load_601_rtcu(cpu_gpr[gprn]);

   331 }

   332 

   333 #if !defined(CONFIG_USER_ONLY)

   334 static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)

   335 {

   336     gen_helper_store_601_rtcu(cpu_gpr[gprn]);

   337 }

   338 

   339 static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)

   340 {

   341     gen_helper_store_601_rtcl(cpu_gpr[gprn]);

   342 }

   343 

   344 static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)

   345 {

   346     DisasContext *ctx = opaque;

   347 

   348     gen_helper_store_hid0_601(cpu_gpr[gprn]);

   349     /* Must stop the translation as endianness may have changed */

   350     gen_stop_exception(ctx);

   351 }

   352 #endif

   353 

   354 /* Unified bats */

   355 #if !defined(CONFIG_USER_ONLY)

   356 static void spr_read_601_ubat (void *opaque, int gprn, int sprn)

   357 {

   358     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));

   359 }

   360 

   361 static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)

   362 {

   363     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);

   364     gen_helper_store_601_batl(t0, cpu_gpr[gprn]);

   365     tcg_temp_free_i32(t0);

   366 }

   367 

   368 static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)

   369 {

   370     TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);

   371     gen_helper_store_601_batu(t0, cpu_gpr[gprn]);

   372     tcg_temp_free_i32(t0);

   373 }

   374 #endif

   375 

   376 /* PowerPC 40x specific registers */

   377 #if !defined(CONFIG_USER_ONLY)

   378 static void spr_read_40x_pit (void *opaque, int gprn, int sprn)

   379 {

   380     gen_helper_load_40x_pit(cpu_gpr[gprn]);

   381 }

   382 

   383 static void spr_write_40x_pit (void *opaque, int sprn, int gprn)

   384 {

   385     gen_helper_store_40x_pit(cpu_gpr[gprn]);

   386 }

   387 

   388 static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)

   389 {

   390     DisasContext *ctx = opaque;

   391 

   392     gen_helper_store_40x_dbcr0(cpu_gpr[gprn]);

   393     /* We must stop translation as we may have rebooted */

   394     gen_stop_exception(ctx);

   395 }

   396 

   397 static void spr_write_40x_sler (void *opaque, int sprn, int gprn)

   398 {

   399     gen_helper_store_40x_sler(cpu_gpr[gprn]);

   400 }

   401 

   402 static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)

   403 {

   404     gen_helper_store_booke_tcr(cpu_gpr[gprn]);

   405 }

   406 

   407 static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)

   408 {

   409     gen_helper_store_booke_tsr(cpu_gpr[gprn]);

   410 }

   411 #endif

   412 

   413 /* PowerPC 403 specific registers */

   414 /* PBL1 / PBU1 / PBL2 / PBU2 */

   415 #if !defined(CONFIG_USER_ONLY)

   416 static void spr_read_403_pbr (void *opaque, int gprn, int sprn)

   417 {

   418     tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, pb[sprn - SPR_403_PBL1]));

   419 }

   420 

   421 static void spr_write_403_pbr (void *opaque, int sprn, int gprn)

   422 {

   423     TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);

   424     gen_helper_store_403_pbr(t0, cpu_gpr[gprn]);

   425     tcg_temp_free_i32(t0);

   426 }

   427 

   428 static void spr_write_pir (void *opaque, int sprn, int gprn)

   429 {

   430     TCGv t0 = tcg_temp_new();

   431     tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);

   432     gen_store_spr(SPR_PIR, t0);

   433     tcg_temp_free(t0);

   434 }

   435 #endif

   436 

   437 /* E500 specific registers */

   438 static void spr_read_spefscr (void *opaque, int gprn, int sprn)

   439 {

   440     TCGv_i32 tmp = tcg_temp_new_i32();

   441     tcg_gen_trunc_tl_i32(tmp, cpu_gpr[gprn]);

   442     tcg_gen_ld_i32(tmp, cpu_env, offsetof(CPUState, spe_fscr));

   443     tcg_temp_free_i32(tmp);

   444 }

   445 

   446 static void spr_write_spefscr (void *opaque, int sprn, int gprn)

   447 {

   448     TCGv_i32 tmp = tcg_temp_new_i32();

   449     tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, spe_fscr));

   450     tcg_gen_extu_i32_tl(cpu_gpr[gprn], tmp);

   451     tcg_temp_free_i32(tmp);

   452 }

   453 

   454 #if !defined(CONFIG_USER_ONLY)

   455 /* Callback used to write the exception vector base */

   456 static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)

   457 {

   458     TCGv t0 = tcg_temp_new();

   459     tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivpr_mask));

   460     tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);

   461     tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));

   462     gen_store_spr(sprn, t0);

   463 }

   464 

   465 static void spr_write_excp_vector (void *opaque, int sprn, int gprn)

   466 {

   467     DisasContext *ctx = opaque;

   468 

   469     if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {

   470         TCGv t0 = tcg_temp_new();

   471         tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));

   472         tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);

   473         tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR0]));

   474         gen_store_spr(sprn, t0);

   475         tcg_temp_free(t0);

   476     } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {

   477         TCGv t0 = tcg_temp_new();

   478         tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));

   479         tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);

   480         tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR32 + 32]));

   481         gen_store_spr(sprn, t0);

   482         tcg_temp_free(t0);

   483     } else {

   484         printf("Trying to write an unknown exception vector %d %03x\n",

   485                sprn, sprn);

   486         gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);

   487     }

   488 }

   489 #endif

   490 

   491 #if defined(CONFIG_USER_ONLY)

   492 #define spr_register(env, num, name, uea_read, uea_write,                     \

   493                      oea_read, oea_write, initial_value)                      \

   494 do {                                                                          \

   495      _spr_register(env, num, name, uea_read, uea_write, initial_value);       \

   496 } while (0)

   497 static inline void _spr_register (CPUPPCState *env, int num,

   498                                   const char *name,

   499                                   void (*uea_read)(void *opaque, int gprn, int sprn),

   500                                   void (*uea_write)(void *opaque, int sprn, int gprn),

   501                                   target_ulong initial_value)

   502 #else

   503 static inline void spr_register (CPUPPCState *env, int num,

   504                                  const char *name,

   505                                  void (*uea_read)(void *opaque, int gprn, int sprn),

   506                                  void (*uea_write)(void *opaque, int sprn, int gprn),

   507                                  void (*oea_read)(void *opaque, int gprn, int sprn),

   508                                  void (*oea_write)(void *opaque, int sprn, int gprn),

   509                                  target_ulong initial_value)

   510 #endif

   511 {

   512     ppc_spr_t *spr;

   513 

   514     spr = &env->spr_cb[num];

   515     if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||

   516 #if !defined(CONFIG_USER_ONLY)

   517         spr->oea_read != NULL || spr->oea_write != NULL ||

   518 #endif

   519         spr->uea_read != NULL || spr->uea_write != NULL) {

   520         printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);

   521         exit(1);

   522     }

   523 #if defined(PPC_DEBUG_SPR)

   524     printf("*** register spr %d (%03x) %s val " ADDRX "\n", num, num, name,

   525            initial_value);

   526 #endif

   527     spr->name = name;

   528     spr->uea_read = uea_read;

   529     spr->uea_write = uea_write;

   530 #if !defined(CONFIG_USER_ONLY)

   531     spr->oea_read = oea_read;

   532     spr->oea_write = oea_write;

   533 #endif

   534     env->spr[num] = initial_value;

   535 }

   536 

   537 /* Generic PowerPC SPRs */

   538 static void gen_spr_generic (CPUPPCState *env)

   539 {

   540     /* Integer processing */

   541     spr_register(env, SPR_XER, "XER",

   542                  &spr_read_xer, &spr_write_xer,

   543                  &spr_read_xer, &spr_write_xer,

   544                  0x00000000);

   545     /* Branch contol */

   546     spr_register(env, SPR_LR, "LR",

   547                  &spr_read_lr, &spr_write_lr,

   548                  &spr_read_lr, &spr_write_lr,

   549                  0x00000000);

   550     spr_register(env, SPR_CTR, "CTR",

   551                  &spr_read_ctr, &spr_write_ctr,

   552                  &spr_read_ctr, &spr_write_ctr,

   553                  0x00000000);

   554     /* Interrupt processing */

   555     spr_register(env, SPR_SRR0, "SRR0",

   556                  SPR_NOACCESS, SPR_NOACCESS,

   557                  &spr_read_generic, &spr_write_generic,

   558                  0x00000000);

   559     spr_register(env, SPR_SRR1, "SRR1",

   560                  SPR_NOACCESS, SPR_NOACCESS,

   561                  &spr_read_generic, &spr_write_generic,

   562                  0x00000000);

   563     /* Processor control */

   564     spr_register(env, SPR_SPRG0, "SPRG0",

   565                  SPR_NOACCESS, SPR_NOACCESS,

   566                  &spr_read_generic, &spr_write_generic,

   567                  0x00000000);

   568     spr_register(env, SPR_SPRG1, "SPRG1",

   569                  SPR_NOACCESS, SPR_NOACCESS,

   570                  &spr_read_generic, &spr_write_generic,

   571                  0x00000000);

   572     spr_register(env, SPR_SPRG2, "SPRG2",

   573                  SPR_NOACCESS, SPR_NOACCESS,

   574                  &spr_read_generic, &spr_write_generic,

   575                  0x00000000);

   576     spr_register(env, SPR_SPRG3, "SPRG3",

   577                  SPR_NOACCESS, SPR_NOACCESS,

   578                  &spr_read_generic, &spr_write_generic,

   579                  0x00000000);

   580 }

   581 

   582 /* SPR common to all non-embedded PowerPC, including 601 */

   583 static void gen_spr_ne_601 (CPUPPCState *env)

   584 {

   585     /* Exception processing */

   586     spr_register(env, SPR_DSISR, "DSISR",

   587                  SPR_NOACCESS, SPR_NOACCESS,

   588                  &spr_read_generic, &spr_write_generic,

   589                  0x00000000);

   590     spr_register(env, SPR_DAR, "DAR",

   591                  SPR_NOACCESS, SPR_NOACCESS,

   592                  &spr_read_generic, &spr_write_generic,

   593                  0x00000000);

   594     /* Timer */

   595     spr_register(env, SPR_DECR, "DECR",

   596                  SPR_NOACCESS, SPR_NOACCESS,

   597                  &spr_read_decr, &spr_write_decr,

   598                  0x00000000);

   599     /* Memory management */

   600     spr_register(env, SPR_SDR1, "SDR1",

   601                  SPR_NOACCESS, SPR_NOACCESS,

   602                  &spr_read_sdr1, &spr_write_sdr1,

   603                  0x00000000);

   604 }

   605 

   606 /* BATs 0-3 */

   607 static void gen_low_BATs (CPUPPCState *env)

   608 {

   609 #if !defined(CONFIG_USER_ONLY)

   610     spr_register(env, SPR_IBAT0U, "IBAT0U",

   611                  SPR_NOACCESS, SPR_NOACCESS,

   612                  &spr_read_ibat, &spr_write_ibatu,

   613                  0x00000000);

   614     spr_register(env, SPR_IBAT0L, "IBAT0L",

   615                  SPR_NOACCESS, SPR_NOACCESS,

   616                  &spr_read_ibat, &spr_write_ibatl,

   617                  0x00000000);

   618     spr_register(env, SPR_IBAT1U, "IBAT1U",

   619                  SPR_NOACCESS, SPR_NOACCESS,

   620                  &spr_read_ibat, &spr_write_ibatu,

   621                  0x00000000);

   622     spr_register(env, SPR_IBAT1L, "IBAT1L",

   623                  SPR_NOACCESS, SPR_NOACCESS,

   624                  &spr_read_ibat, &spr_write_ibatl,

   625                  0x00000000);

   626     spr_register(env, SPR_IBAT2U, "IBAT2U",

   627                  SPR_NOACCESS, SPR_NOACCESS,

   628                  &spr_read_ibat, &spr_write_ibatu,

   629                  0x00000000);

   630     spr_register(env, SPR_IBAT2L, "IBAT2L",

   631                  SPR_NOACCESS, SPR_NOACCESS,

   632                  &spr_read_ibat, &spr_write_ibatl,

   633                  0x00000000);

   634     spr_register(env, SPR_IBAT3U, "IBAT3U",

   635                  SPR_NOACCESS, SPR_NOACCESS,

   636                  &spr_read_ibat, &spr_write_ibatu,

   637                  0x00000000);

   638     spr_register(env, SPR_IBAT3L, "IBAT3L",

   639                  SPR_NOACCESS, SPR_NOACCESS,

   640                  &spr_read_ibat, &spr_write_ibatl,

   641                  0x00000000);

   642     spr_register(env, SPR_DBAT0U, "DBAT0U",

   643                  SPR_NOACCESS, SPR_NOACCESS,

   644                  &spr_read_dbat, &spr_write_dbatu,

   645                  0x00000000);

   646     spr_register(env, SPR_DBAT0L, "DBAT0L",

   647                  SPR_NOACCESS, SPR_NOACCESS,

   648                  &spr_read_dbat, &spr_write_dbatl,

   649                  0x00000000);

   650     spr_register(env, SPR_DBAT1U, "DBAT1U",

   651                  SPR_NOACCESS, SPR_NOACCESS,

   652                  &spr_read_dbat, &spr_write_dbatu,

   653                  0x00000000);

   654     spr_register(env, SPR_DBAT1L, "DBAT1L",

   655                  SPR_NOACCESS, SPR_NOACCESS,

   656                  &spr_read_dbat, &spr_write_dbatl,

   657                  0x00000000);

   658     spr_register(env, SPR_DBAT2U, "DBAT2U",

   659                  SPR_NOACCESS, SPR_NOACCESS,

   660                  &spr_read_dbat, &spr_write_dbatu,

   661                  0x00000000);

   662     spr_register(env, SPR_DBAT2L, "DBAT2L",

   663                  SPR_NOACCESS, SPR_NOACCESS,

   664                  &spr_read_dbat, &spr_write_dbatl,

   665                  0x00000000);

   666     spr_register(env, SPR_DBAT3U, "DBAT3U",

   667                  SPR_NOACCESS, SPR_NOACCESS,

   668                  &spr_read_dbat, &spr_write_dbatu,

   669                  0x00000000);

   670     spr_register(env, SPR_DBAT3L, "DBAT3L",

   671                  SPR_NOACCESS, SPR_NOACCESS,

   672                  &spr_read_dbat, &spr_write_dbatl,

   673                  0x00000000);

   674     env->nb_BATs += 4;

   675 #endif

   676 }

   677 

   678 /* BATs 4-7 */

   679 static void gen_high_BATs (CPUPPCState *env)

   680 {

   681 #if !defined(CONFIG_USER_ONLY)

   682     spr_register(env, SPR_IBAT4U, "IBAT4U",

   683                  SPR_NOACCESS, SPR_NOACCESS,

   684                  &spr_read_ibat_h, &spr_write_ibatu_h,

   685                  0x00000000);

   686     spr_register(env, SPR_IBAT4L, "IBAT4L",

   687                  SPR_NOACCESS, SPR_NOACCESS,

   688                  &spr_read_ibat_h, &spr_write_ibatl_h,

   689                  0x00000000);

   690     spr_register(env, SPR_IBAT5U, "IBAT5U",

   691                  SPR_NOACCESS, SPR_NOACCESS,

   692                  &spr_read_ibat_h, &spr_write_ibatu_h,

   693                  0x00000000);

   694     spr_register(env, SPR_IBAT5L, "IBAT5L",

   695                  SPR_NOACCESS, SPR_NOACCESS,

   696                  &spr_read_ibat_h, &spr_write_ibatl_h,

   697                  0x00000000);

   698     spr_register(env, SPR_IBAT6U, "IBAT6U",

   699                  SPR_NOACCESS, SPR_NOACCESS,

   700                  &spr_read_ibat_h, &spr_write_ibatu_h,

   701                  0x00000000);

   702     spr_register(env, SPR_IBAT6L, "IBAT6L",

   703                  SPR_NOACCESS, SPR_NOACCESS,

   704                  &spr_read_ibat_h, &spr_write_ibatl_h,

   705                  0x00000000);

   706     spr_register(env, SPR_IBAT7U, "IBAT7U",

   707                  SPR_NOACCESS, SPR_NOACCESS,

   708                  &spr_read_ibat_h, &spr_write_ibatu_h,

   709                  0x00000000);

   710     spr_register(env, SPR_IBAT7L, "IBAT7L",

   711                  SPR_NOACCESS, SPR_NOACCESS,

   712                  &spr_read_ibat_h, &spr_write_ibatl_h,

   713                  0x00000000);

   714     spr_register(env, SPR_DBAT4U, "DBAT4U",

   715                  SPR_NOACCESS, SPR_NOACCESS,

   716                  &spr_read_dbat_h, &spr_write_dbatu_h,

   717                  0x00000000);

   718     spr_register(env, SPR_DBAT4L, "DBAT4L",

   719                  SPR_NOACCESS, SPR_NOACCESS,

   720                  &spr_read_dbat_h, &spr_write_dbatl_h,

   721                  0x00000000);

   722     spr_register(env, SPR_DBAT5U, "DBAT5U",

   723                  SPR_NOACCESS, SPR_NOACCESS,

   724                  &spr_read_dbat_h, &spr_write_dbatu_h,

   725                  0x00000000);

   726     spr_register(env, SPR_DBAT5L, "DBAT5L",

   727                  SPR_NOACCESS, SPR_NOACCESS,

   728                  &spr_read_dbat_h, &spr_write_dbatl_h,

   729                  0x00000000);

   730     spr_register(env, SPR_DBAT6U, "DBAT6U",

   731                  SPR_NOACCESS, SPR_NOACCESS,

   732                  &spr_read_dbat_h, &spr_write_dbatu_h,

   733                  0x00000000);

   734     spr_register(env, SPR_DBAT6L, "DBAT6L",

   735                  SPR_NOACCESS, SPR_NOACCESS,

   736                  &spr_read_dbat_h, &spr_write_dbatl_h,

   737                  0x00000000);

   738     spr_register(env, SPR_DBAT7U, "DBAT7U",

   739                  SPR_NOACCESS, SPR_NOACCESS,

   740                  &spr_read_dbat_h, &spr_write_dbatu_h,

   741                  0x00000000);

   742     spr_register(env, SPR_DBAT7L, "DBAT7L",

   743                  SPR_NOACCESS, SPR_NOACCESS,

   744                  &spr_read_dbat_h, &spr_write_dbatl_h,

   745                  0x00000000);

   746     env->nb_BATs += 4;

   747 #endif

   748 }

   749 

   750 /* Generic PowerPC time base */

   751 static void gen_tbl (CPUPPCState *env)

   752 {

   753     spr_register(env, SPR_VTBL,  "TBL",

   754                  &spr_read_tbl, SPR_NOACCESS,

   755                  &spr_read_tbl, SPR_NOACCESS,

   756                  0x00000000);

   757     spr_register(env, SPR_TBL,   "TBL",

   758                  SPR_NOACCESS, SPR_NOACCESS,

   759                  SPR_NOACCESS, &spr_write_tbl,

   760                  0x00000000);

   761     spr_register(env, SPR_VTBU,  "TBU",

   762                  &spr_read_tbu, SPR_NOACCESS,

   763                  &spr_read_tbu, SPR_NOACCESS,

   764                  0x00000000);

   765     spr_register(env, SPR_TBU,   "TBU",

   766                  SPR_NOACCESS, SPR_NOACCESS,

   767                  SPR_NOACCESS, &spr_write_tbu,

   768                  0x00000000);

   769 }

   770 

   771 /* Softare table search registers */

   772 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)

   773 {

   774 #if !defined(CONFIG_USER_ONLY)

   775     env->nb_tlb = nb_tlbs;

   776     env->nb_ways = nb_ways;

   777     env->id_tlbs = 1;

   778     spr_register(env, SPR_DMISS, "DMISS",

   779                  SPR_NOACCESS, SPR_NOACCESS,

   780                  &spr_read_generic, SPR_NOACCESS,

   781                  0x00000000);

   782     spr_register(env, SPR_DCMP, "DCMP",

   783                  SPR_NOACCESS, SPR_NOACCESS,

   784                  &spr_read_generic, SPR_NOACCESS,

   785                  0x00000000);

   786     spr_register(env, SPR_HASH1, "HASH1",

   787                  SPR_NOACCESS, SPR_NOACCESS,

   788                  &spr_read_generic, SPR_NOACCESS,

   789                  0x00000000);

   790     spr_register(env, SPR_HASH2, "HASH2",

   791                  SPR_NOACCESS, SPR_NOACCESS,

   792                  &spr_read_generic, SPR_NOACCESS,

   793                  0x00000000);

   794     spr_register(env, SPR_IMISS, "IMISS",

   795                  SPR_NOACCESS, SPR_NOACCESS,

   796                  &spr_read_generic, SPR_NOACCESS,

   797                  0x00000000);

   798     spr_register(env, SPR_ICMP, "ICMP",

   799                  SPR_NOACCESS, SPR_NOACCESS,

   800                  &spr_read_generic, SPR_NOACCESS,

   801                  0x00000000);

   802     spr_register(env, SPR_RPA, "RPA",

   803                  SPR_NOACCESS, SPR_NOACCESS,

   804                  &spr_read_generic, &spr_write_generic,

   805                  0x00000000);

   806 #endif

   807 }

   808 

   809 /* SPR common to MPC755 and G2 */

   810 static void gen_spr_G2_755 (CPUPPCState *env)

   811 {

   812     /* SGPRs */

   813     spr_register(env, SPR_SPRG4, "SPRG4",

   814                  SPR_NOACCESS, SPR_NOACCESS,

   815                  &spr_read_generic, &spr_write_generic,

   816                  0x00000000);

   817     spr_register(env, SPR_SPRG5, "SPRG5",

   818                  SPR_NOACCESS, SPR_NOACCESS,

   819                  &spr_read_generic, &spr_write_generic,

   820                  0x00000000);

   821     spr_register(env, SPR_SPRG6, "SPRG6",

   822                  SPR_NOACCESS, SPR_NOACCESS,

   823                  &spr_read_generic, &spr_write_generic,

   824                  0x00000000);

   825     spr_register(env, SPR_SPRG7, "SPRG7",

   826                  SPR_NOACCESS, SPR_NOACCESS,

   827                  &spr_read_generic, &spr_write_generic,

   828                  0x00000000);

   829 }

   830 

   831 /* SPR common to all 7xx PowerPC implementations */

   832 static void gen_spr_7xx (CPUPPCState *env)

   833 {

   834     /* Breakpoints */

   835     /* XXX : not implemented */

   836     spr_register(env, SPR_DABR, "DABR",

   837                  SPR_NOACCESS, SPR_NOACCESS,

   838                  &spr_read_generic, &spr_write_generic,

   839                  0x00000000);

   840     /* XXX : not implemented */

   841     spr_register(env, SPR_IABR, "IABR",

   842                  SPR_NOACCESS, SPR_NOACCESS,

   843                  &spr_read_generic, &spr_write_generic,

   844                  0x00000000);

   845     /* Cache management */

   846     /* XXX : not implemented */

   847     spr_register(env, SPR_ICTC, "ICTC",

   848                  SPR_NOACCESS, SPR_NOACCESS,

   849                  &spr_read_generic, &spr_write_generic,

   850                  0x00000000);

   851     /* Performance monitors */

   852     /* XXX : not implemented */

   853     spr_register(env, SPR_MMCR0, "MMCR0",

   854                  SPR_NOACCESS, SPR_NOACCESS,

   855                  &spr_read_generic, &spr_write_generic,

   856                  0x00000000);

   857     /* XXX : not implemented */

   858     spr_register(env, SPR_MMCR1, "MMCR1",

   859                  SPR_NOACCESS, SPR_NOACCESS,

   860                  &spr_read_generic, &spr_write_generic,

   861                  0x00000000);

   862     /* XXX : not implemented */

   863     spr_register(env, SPR_PMC1, "PMC1",

   864                  SPR_NOACCESS, SPR_NOACCESS,

   865                  &spr_read_generic, &spr_write_generic,

   866                  0x00000000);

   867     /* XXX : not implemented */

   868     spr_register(env, SPR_PMC2, "PMC2",

   869                  SPR_NOACCESS, SPR_NOACCESS,

   870                  &spr_read_generic, &spr_write_generic,

   871                  0x00000000);

   872     /* XXX : not implemented */

   873     spr_register(env, SPR_PMC3, "PMC3",

   874                  SPR_NOACCESS, SPR_NOACCESS,

   875                  &spr_read_generic, &spr_write_generic,

   876                  0x00000000);

   877     /* XXX : not implemented */

   878     spr_register(env, SPR_PMC4, "PMC4",

   879                  SPR_NOACCESS, SPR_NOACCESS,

   880                  &spr_read_generic, &spr_write_generic,

   881                  0x00000000);

   882     /* XXX : not implemented */

   883     spr_register(env, SPR_SIAR, "SIAR",

   884                  SPR_NOACCESS, SPR_NOACCESS,

   885                  &spr_read_generic, SPR_NOACCESS,

   886                  0x00000000);

   887     /* XXX : not implemented */

   888     spr_register(env, SPR_UMMCR0, "UMMCR0",

   889                  &spr_read_ureg, SPR_NOACCESS,

   890                  &spr_read_ureg, SPR_NOACCESS,

   891                  0x00000000);

   892     /* XXX : not implemented */

   893     spr_register(env, SPR_UMMCR1, "UMMCR1",

   894                  &spr_read_ureg, SPR_NOACCESS,

   895                  &spr_read_ureg, SPR_NOACCESS,

   896                  0x00000000);

   897     /* XXX : not implemented */

   898     spr_register(env, SPR_UPMC1, "UPMC1",

   899                  &spr_read_ureg, SPR_NOACCESS,

   900                  &spr_read_ureg, SPR_NOACCESS,

   901                  0x00000000);

   902     /* XXX : not implemented */

   903     spr_register(env, SPR_UPMC2, "UPMC2",

   904                  &spr_read_ureg, SPR_NOACCESS,

   905                  &spr_read_ureg, SPR_NOACCESS,

   906                  0x00000000);

   907     /* XXX : not implemented */

   908     spr_register(env, SPR_UPMC3, "UPMC3",

   909                  &spr_read_ureg, SPR_NOACCESS,

   910                  &spr_read_ureg, SPR_NOACCESS,

   911                  0x00000000);

   912     /* XXX : not implemented */

   913     spr_register(env, SPR_UPMC4, "UPMC4",

   914                  &spr_read_ureg, SPR_NOACCESS,

   915                  &spr_read_ureg, SPR_NOACCESS,

   916                  0x00000000);

   917     /* XXX : not implemented */

   918     spr_register(env, SPR_USIAR, "USIAR",

   919                  &spr_read_ureg, SPR_NOACCESS,

   920                  &spr_read_ureg, SPR_NOACCESS,

   921                  0x00000000);

   922     /* External access control */

   923     /* XXX : not implemented */

   924     spr_register(env, SPR_EAR, "EAR",

   925                  SPR_NOACCESS, SPR_NOACCESS,

   926                  &spr_read_generic, &spr_write_generic,

   927                  0x00000000);

   928 }

   929 

   930 static void gen_spr_thrm (CPUPPCState *env)

   931 {

   932     /* Thermal management */

   933     /* XXX : not implemented */

   934     spr_register(env, SPR_THRM1, "THRM1",

   935                  SPR_NOACCESS, SPR_NOACCESS,

   936                  &spr_read_generic, &spr_write_generic,

   937                  0x00000000);

   938     /* XXX : not implemented */

   939     spr_register(env, SPR_THRM2, "THRM2",

   940                  SPR_NOACCESS, SPR_NOACCESS,

   941                  &spr_read_generic, &spr_write_generic,

   942                  0x00000000);

   943     /* XXX : not implemented */

   944     spr_register(env, SPR_THRM3, "THRM3",

   945                  SPR_NOACCESS, SPR_NOACCESS,

   946                  &spr_read_generic, &spr_write_generic,

   947                  0x00000000);

   948 }

   949 

   950 /* SPR specific to PowerPC 604 implementation */

   951 static void gen_spr_604 (CPUPPCState *env)

   952 {

   953     /* Processor identification */

   954     spr_register(env, SPR_PIR, "PIR",

   955                  SPR_NOACCESS, SPR_NOACCESS,

   956                  &spr_read_generic, &spr_write_pir,

   957                  0x00000000);

   958     /* Breakpoints */

   959     /* XXX : not implemented */

   960     spr_register(env, SPR_IABR, "IABR",

   961                  SPR_NOACCESS, SPR_NOACCESS,

   962                  &spr_read_generic, &spr_write_generic,

   963                  0x00000000);

   964     /* XXX : not implemented */

   965     spr_register(env, SPR_DABR, "DABR",

   966                  SPR_NOACCESS, SPR_NOACCESS,

   967                  &spr_read_generic, &spr_write_generic,

   968                  0x00000000);

   969     /* Performance counters */

   970     /* XXX : not implemented */

   971     spr_register(env, SPR_MMCR0, "MMCR0",

   972                  SPR_NOACCESS, SPR_NOACCESS,

   973                  &spr_read_generic, &spr_write_generic,

   974                  0x00000000);

   975     /* XXX : not implemented */

   976     spr_register(env, SPR_PMC1, "PMC1",

   977                  SPR_NOACCESS, SPR_NOACCESS,

   978                  &spr_read_generic, &spr_write_generic,

   979                  0x00000000);

   980     /* XXX : not implemented */

   981     spr_register(env, SPR_PMC2, "PMC2",

   982                  SPR_NOACCESS, SPR_NOACCESS,

   983                  &spr_read_generic, &spr_write_generic,

   984                  0x00000000);

   985     /* XXX : not implemented */

   986     spr_register(env, SPR_SIAR, "SIAR",

   987                  SPR_NOACCESS, SPR_NOACCESS,

   988                  &spr_read_generic, SPR_NOACCESS,

   989                  0x00000000);

   990     /* XXX : not implemented */

   991     spr_register(env, SPR_SDA, "SDA",

   992                  SPR_NOACCESS, SPR_NOACCESS,

   993                  &spr_read_generic, SPR_NOACCESS,

   994                  0x00000000);

   995     /* External access control */

   996     /* XXX : not implemented */

   997     spr_register(env, SPR_EAR, "EAR",

   998                  SPR_NOACCESS, SPR_NOACCESS,

   999                  &spr_read_generic, &spr_write_generic,

  1000                  0x00000000);

  1001 }

  1002 

  1003 /* SPR specific to PowerPC 603 implementation */

  1004 static void gen_spr_603 (CPUPPCState *env)

  1005 {

  1006     /* External access control */

  1007     /* XXX : not implemented */

  1008     spr_register(env, SPR_EAR, "EAR",

  1009                  SPR_NOACCESS, SPR_NOACCESS,

  1010                  &spr_read_generic, &spr_write_generic,

  1011                  0x00000000);

  1012 }

  1013 

  1014 /* SPR specific to PowerPC G2 implementation */

  1015 static void gen_spr_G2 (CPUPPCState *env)

  1016 {

  1017     /* Memory base address */

  1018     /* MBAR */

  1019     /* XXX : not implemented */

  1020     spr_register(env, SPR_MBAR, "MBAR",

  1021                  SPR_NOACCESS, SPR_NOACCESS,

  1022                  &spr_read_generic, &spr_write_generic,

  1023                  0x00000000);

  1024     /* Exception processing */

  1025     spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",

  1026                  SPR_NOACCESS, SPR_NOACCESS,

  1027                  &spr_read_generic, &spr_write_generic,

  1028                  0x00000000);

  1029     spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",

  1030                  SPR_NOACCESS, SPR_NOACCESS,

  1031                  &spr_read_generic, &spr_write_generic,

  1032                  0x00000000);

  1033     /* Breakpoints */

  1034     /* XXX : not implemented */

  1035     spr_register(env, SPR_DABR, "DABR",

  1036                  SPR_NOACCESS, SPR_NOACCESS,

  1037                  &spr_read_generic, &spr_write_generic,

  1038                  0x00000000);

  1039     /* XXX : not implemented */

  1040     spr_register(env, SPR_DABR2, "DABR2",

  1041                  SPR_NOACCESS, SPR_NOACCESS,

  1042                  &spr_read_generic, &spr_write_generic,

  1043                  0x00000000);

  1044     /* XXX : not implemented */

  1045     spr_register(env, SPR_IABR, "IABR",

  1046                  SPR_NOACCESS, SPR_NOACCESS,

  1047                  &spr_read_generic, &spr_write_generic,

  1048                  0x00000000);

  1049     /* XXX : not implemented */

  1050     spr_register(env, SPR_IABR2, "IABR2",

  1051                  SPR_NOACCESS, SPR_NOACCESS,

  1052                  &spr_read_generic, &spr_write_generic,

  1053                  0x00000000);

  1054     /* XXX : not implemented */

  1055     spr_register(env, SPR_IBCR, "IBCR",

  1056                  SPR_NOACCESS, SPR_NOACCESS,

  1057                  &spr_read_generic, &spr_write_generic,

  1058                  0x00000000);

  1059     /* XXX : not implemented */

  1060     spr_register(env, SPR_DBCR, "DBCR",

  1061                  SPR_NOACCESS, SPR_NOACCESS,

  1062                  &spr_read_generic, &spr_write_generic,

  1063                  0x00000000);

  1064 }

  1065 

  1066 /* SPR specific to PowerPC 602 implementation */

  1067 static void gen_spr_602 (CPUPPCState *env)

  1068 {

  1069     /* ESA registers */

  1070     /* XXX : not implemented */

  1071     spr_register(env, SPR_SER, "SER",

  1072                  SPR_NOACCESS, SPR_NOACCESS,

  1073                  &spr_read_generic, &spr_write_generic,

  1074                  0x00000000);

  1075     /* XXX : not implemented */

  1076     spr_register(env, SPR_SEBR, "SEBR",

  1077                  SPR_NOACCESS, SPR_NOACCESS,

  1078                  &spr_read_generic, &spr_write_generic,

  1079                  0x00000000);

  1080     /* XXX : not implemented */

  1081     spr_register(env, SPR_ESASRR, "ESASRR",

  1082                  SPR_NOACCESS, SPR_NOACCESS,

  1083                  &spr_read_generic, &spr_write_generic,

  1084                  0x00000000);

  1085     /* Floating point status */

  1086     /* XXX : not implemented */

  1087     spr_register(env, SPR_SP, "SP",

  1088                  SPR_NOACCESS, SPR_NOACCESS,

  1089                  &spr_read_generic, &spr_write_generic,

  1090                  0x00000000);

  1091     /* XXX : not implemented */

  1092     spr_register(env, SPR_LT, "LT",

  1093                  SPR_NOACCESS, SPR_NOACCESS,

  1094                  &spr_read_generic, &spr_write_generic,

  1095                  0x00000000);

  1096     /* Watchdog timer */

  1097     /* XXX : not implemented */

  1098     spr_register(env, SPR_TCR, "TCR",

  1099                  SPR_NOACCESS, SPR_NOACCESS,

  1100                  &spr_read_generic, &spr_write_generic,

  1101                  0x00000000);

  1102     /* Interrupt base */

  1103     spr_register(env, SPR_IBR, "IBR",

  1104                  SPR_NOACCESS, SPR_NOACCESS,

  1105                  &spr_read_generic, &spr_write_generic,

  1106                  0x00000000);

  1107     /* XXX : not implemented */

  1108     spr_register(env, SPR_IABR, "IABR",

  1109                  SPR_NOACCESS, SPR_NOACCESS,

  1110                  &spr_read_generic, &spr_write_generic,

  1111                  0x00000000);

  1112 }

  1113 

  1114 /* SPR specific to PowerPC 601 implementation */

  1115 static void gen_spr_601 (CPUPPCState *env)

  1116 {

  1117     /* Multiplication/division register */

  1118     /* MQ */

  1119     spr_register(env, SPR_MQ, "MQ",

  1120                  &spr_read_generic, &spr_write_generic,

  1121                  &spr_read_generic, &spr_write_generic,

  1122                  0x00000000);

  1123     /* RTC registers */

  1124     spr_register(env, SPR_601_RTCU, "RTCU",

  1125                  SPR_NOACCESS, SPR_NOACCESS,

  1126                  SPR_NOACCESS, &spr_write_601_rtcu,

  1127                  0x00000000);

  1128     spr_register(env, SPR_601_VRTCU, "RTCU",

  1129                  &spr_read_601_rtcu, SPR_NOACCESS,

  1130                  &spr_read_601_rtcu, SPR_NOACCESS,

  1131                  0x00000000);

  1132     spr_register(env, SPR_601_RTCL, "RTCL",

  1133                  SPR_NOACCESS, SPR_NOACCESS,

  1134                  SPR_NOACCESS, &spr_write_601_rtcl,

  1135                  0x00000000);