baseport/syborg/bootstrap/syborg.s
changeset 2 d55eb581a87c
parent 0 ffa851df0825
equal deleted inserted replaced
1:2fb8b9db1c86 2:d55eb581a87c
       
     1 ;/*
       
     2 ;* Copyright (c) 2009 Nokia Corporation and/or its subsidiary(-ies).
       
     3 ;* All rights reserved.
       
     4 ;* This component and the accompanying materials are made available
       
     5 ;* under the terms of the License "Eclipse Public License v1.0"
       
     6 ;* which accompanies this distribution, and is available
       
     7 ;* at the URL "http://www.eclipse.org/legal/epl-v10.html".
       
     8 ;*
       
     9 ;* Initial Contributors:
       
    10 ;* Nokia Corporation - initial contribution.
       
    11 ;*
       
    12 ;* Contributors:
       
    13 ;*
       
    14 ;* Description:
       
    15 ;*
       
    16 ;*/
       
    17 		
       
    18 		GBLL	__VARIANT_S__       ; indicates that this is platform-specific code
       
    19 		GBLL	__SYBORG_S__		; indicates which source file this is
       
    20 
       
    21 		INCLUDE	bootcpu.inc
       
    22 		INCLUDE syborg.inc
       
    23 ;
       
    24 ;*******************************************************************************
       
    25 ;
       
    26         IMPORT	ResetEntry
       
    27 ;
       
    28 ;*******************************************************************************
       
    29 ;
       
    30         AREA |Boot$$Code|, CODE, READONLY, ALIGN=6
       
    31 ;
       
    32 ;*******************************************************************************
       
    33 ; Initialise Hardware
       
    34 ;	Determine the hardware configuration
       
    35 ;	Determine the reset reason. If it is wakeup from a low power mode, perform
       
    36 ;		whatever reentry sequence is required and jump back to the kernel.
       
    37 ;	Set up the memory controller so that at least some RAM is available
       
    38 ;	Set R10 to point to the super page or to a temporary version of the super page
       
    39 ;		with at least the following fields valid:
       
    40 ;		iBootTable, iCodeBase, iActiveVariant, iCpuId
       
    41 ;	Initialise the debug serial port
       
    42 ;
       
    43 ; Enter with:
       
    44 ;	R12 points to TRomHeader
       
    45 ;	NO STACK
       
    46 ;	R14 = return address (as usual)
       
    47 ;
       
    48 ; All registers may be modified by this call
       
    49 ;*******************************************************************************
       
    50 	EXPORT	InitialiseHardware
       
    51 InitialiseHardware	ROUT
       
    52 		mov		r13, lr							    ; save return address
       
    53 
       
    54 		adrl	r1, ParameterTable	        ; pass address of parameter table
       
    55 		bl		InitCpu				        ; initialise CPU/MMU registers
       
    56 						
       
    57 ;*******************************************************************************
       
    58 ; DoInitialise Hardware
       
    59 ;	Initialise CPU registers
       
    60 ;	Determine the hardware configuration
       
    61 ;	Determine the reset reason. If it is wakeup from a low power mode, perform
       
    62 ;		whatever reentry sequence is required and jump back to the kernel.
       
    63 ;	Set up the memory controller so that at least some RAM is available
       
    64 ;	Set R10 to point to the super page or to a temporary version of the super page
       
    65 ;		with at least the following fields valid:
       
    66 ;		iBootTable, iCodeBase, iActiveVariant, iCpuId
       
    67 ;	In debug builds initialise the debug serial port
       
    68 ;
       
    69 ; Enter with:
       
    70 ;	R12 points to TRomHeader
       
    71 ;	NO STACK
       
    72 ;	R13 = return address (as usual)
       
    73 ;
       
    74 ; All registers may be modified by this call
       
    75 ;*******************************************************************************
       
    76 DoInitialiseHardware	ROUT
       
    77 		
       
    78 ; Hardware memory size is 128MB - 32MB reserved for bootloader
       
    79 		mov		r4, #KHwRamSizeMb
       
    80 
       
    81 		bl		InitDebugPort
       
    82 
       
    83 		ldr		r7, =CFG_HWVD					; variant number
       
    84 
       
    85 		lsl		r10, r4, #20				    ; R10 = top of RAM
       
    86 		sub		r10, #0x2000				    ; put super page at end for now
       
    87 
       
    88 ; Set up the required super page values
       
    89 		str		r7, [r10, #SSuperPageBase_iActiveVariant]
       
    90 
       
    91 		mov		r1, #0
       
    92 		str		r1, [r10, #SSuperPageBase_iHwStartupReason]	; reset reason (from hardware)
       
    93 
       
    94 		add		r1, r10, #CpuPageOffset
       
    95 		str		r1, [r10, #SSuperPageBase_iMachineData]
       
    96 		bl		GetBootTableAddress
       
    97 		str		r0, [r10, #SSuperPageBase_iBootTable]		; set the boot function table
       
    98 		str		r12, [r10, #SSuperPageBase_iCodeBase]		; set the base address of bootstrap code
       
    99 		mrc		p15, 0, r0, c0, c0, 0						; read CPU ID from CP15 (remove if no CP15)
       
   100 		str		r0, [r10, #SSuperPageBase_iCpuId]
       
   101 
       
   102 		mov		r0, r13
       
   103 		add		sp, r10, #CpuBootStackTop		            ; set up a boot stack
       
   104 		push    {r0}						                ; save return address
       
   105 		bl		DoInitHw2						            ; any extra CPU-dependent stuff
       
   106 				
       
   107 		ldr		r7, [r10, #SSuperPageBase_iActiveVariant]
       
   108 		DWORD	r7, "ActiveVariant"
       
   109 
       
   110 		pop     {pc}						                ; return
       
   111 
       
   112 ;*******************************************************************************
       
   113 DoInitHw2	ROUT
       
   114 		mrc		p15, 0, r0, c0, c0, 0
       
   115 		DWORD	r0, "MMUID"
       
   116 		mrc		p15, 0, r0, c0, c0, 1
       
   117 		DWORD	r0, "CacheType"
       
   118 		mrc		p15, 0, r0, c0, c0, 2
       
   119 		DWORD	r0, "TCMType"
       
   120 		mrc		p15, 0, r0, c0, c0, 3
       
   121 		DWORD	r0, "TLBType"
       
   122         bx      lr
       
   123 
       
   124 ;*******************************************************************************
       
   125 ; Get a pointer to the list of hardware banks
       
   126 ;
       
   127 ; The pointer returned should point to a list of hardware banks declared with
       
   128 ; the HW_MAPPING and/or HW_MAPPING_EXT macros. A zero word terminates the list.
       
   129 ; For the direct memory model, all hardware on the system should be mapped here
       
   130 ; and the mapping will set linear address = physical address.
       
   131 ; For the moving or multiple model, only the hardware required to boot the kernel
       
   132 ; and do debug tracing needs to be mapped here. The linear addresses used will
       
   133 ; start at KPrimaryIOBase and step up as required with the order of banks in
       
   134 ; the list being maintained in the linear addresses used.
       
   135 ;
       
   136 ; HW_MAPPING PB, SIZE, MULT
       
   137 ;	This declares a block of I/O with physical base PB and address range SIZE
       
   138 ;	blocks each of which has a size determined by MULT. The page size used for
       
   139 ;	the mapping is determined by MULT. The linear address base of the mapping
       
   140 ;	will be the next free linear address rounded up to the size specified by
       
   141 ;	MULT.
       
   142 ;	The permissions used for the mapping are the standard I/O permissions (BTP_Hw).
       
   143 ;
       
   144 ; HW_MAPPING_EXT PB, SIZE, MULT
       
   145 ;	This declares a block of I/O with physical base PB and address range SIZE
       
   146 ;	blocks each of which has a size determined by MULT. The page size used for
       
   147 ;	the mapping is determined by MULT. The linear address base of the mapping
       
   148 ;	will be the next free linear address rounded up to the size specified by
       
   149 ;	MULT.
       
   150 ;	The permissions used for the mapping are determined by a BTP_ENTRY macro
       
   151 ;	immediately following this macro in the HW bank list or by a DCD directive
       
   152 ;	specifying a different standard permission type.
       
   153 ;
       
   154 ; Configurations without an MMU need not implement this function.
       
   155 ;
       
   156 ; Enter with :
       
   157 ;		R10 points to super page
       
   158 ;		R12 points to ROM header
       
   159 ;		R13 points to valid stack
       
   160 ;
       
   161 ; Leave with :
       
   162 ;		R0 = pointer
       
   163 ;		Nothing else modified
       
   164 ;*******************************************************************************
       
   165 	EXPORT	GetHwBanks
       
   166 GetHwBanks	ROUT
       
   167 		adr		r0, %FT1
       
   168 		bx      lr
       
   169 1
       
   170 		HW_MAPPING		KHwBaseSic,			1,	HW_MULT_4K
       
   171 		HW_MAPPING		KHwBaseRtc,			1,	HW_MULT_4K
       
   172 		HW_MAPPING		KHwBaseTimer,			1,	HW_MULT_4K	
       
   173 		HW_MAPPING		KHwBaseKmiKeyboard,		1,	HW_MULT_4K
       
   174 		HW_MAPPING		KHwBaseKmiPointer,		1,	HW_MULT_4K
       
   175 		HW_MAPPING		KHwBaseClcd,			1,	HW_MULT_4K
       
   176 		HW_MAPPING		KHwBaseUart0,			1,	HW_MULT_4K
       
   177 		HW_MAPPING		KHwBaseUart1,			1,	HW_MULT_4K
       
   178 		HW_MAPPING		KHwBaseUart2,			1,	HW_MULT_4K
       
   179 		HW_MAPPING		KHwBaseUart3,    		1,	HW_MULT_4K
       
   180 		HW_MAPPING		KHwBaseHostFs,    		1,	HW_MULT_4K
       
   181 		HW_MAPPING		KHwBaseSnap,    		1,	HW_MULT_4K
       
   182 		HW_MAPPING		KHwBaseNet,			1,	HW_MULT_4K
       
   183 		HW_MAPPING		KHwBaseNand,    		1,	HW_MULT_4K
       
   184 		HW_MAPPING		KHwBaseAudio,    		1,	HW_MULT_4K
       
   185 		HW_MAPPING		KHwBasePlatform,    		8,	HW_MULT_4K
       
   186 	
       
   187 		DCD     0   ; terminator
       
   188 
       
   189 ;*******************************************************************************
       
   190 ; Notify an unrecoverable error during the boot process
       
   191 ;
       
   192 ; Enter with:
       
   193 ;	R14 = address at which fault detected
       
   194 ;
       
   195 ; Don't return
       
   196 ;*******************************************************************************
       
   197 	EXPORT	Fault
       
   198 Fault	ROUT
       
   199 		b		BasicFaultHandler	; generic handler dumps registers via debug
       
   200 									; serial port
       
   201 
       
   202 ;*******************************************************************************
       
   203 ; Reboot the system
       
   204 ;
       
   205 ; Enter with:
       
   206 ;		R0 = reboot reason code
       
   207 ;
       
   208 ; Don't return (of course)
       
   209 ;*******************************************************************************
       
   210 	ALIGN	32, 0
       
   211 	EXPORT	RestartEntry
       
   212 RestartEntry	ROUT
       
   213 
       
   214 ; Save R0 parameter in HW dependent register which is preserved over reset
       
   215 ; Put HW specific code here to reset system
       
   216 	    GETCPSR	r1
       
   217 		orr		r1, #0xC0
       
   218 		SETCPSR	r1										; disable interrupts
       
   219 
       
   220         ldr     r10, =KSuperPageLinAddr
       
   221         adr     r0, Run_Physical
       
   222         bl      RomLinearToPhysical                 ; physical address in r0
       
   223 
       
   224 ; Disable MMU
       
   225 		mrc		p15, 0, r1, c1, c0, 0		        ; get MMUCR
       
   226 		bic		r1, #MMUCR_M		                ; clear M bit
       
   227 		mcr		p15, 0, r1, c1, c0, 0		        ; set MMUCR
       
   228         bx      r0                                  ; jump to the physical address
       
   229         
       
   230 ; Now running from physical address
       
   231 
       
   232 Run_Physical
       
   233         mov     r3, #KHwNorFlashBaseAddr            ; r3 = NOR flash image base
       
   234         
       
   235 ; Jump to the NOR flash image
       
   236         bx      r3                              
       
   237 
       
   238 ;*******************************************************************************
       
   239 ; Get a pointer to the list of RAM banks
       
   240 ;
       
   241 ; The pointer returned should point to a list of {BASE; MAXSIZE;} pairs, where
       
   242 ; BASE is the physical base address of the bank and MAXSIZE is the maximum
       
   243 ; amount of RAM which may be present in that bank. MAXSIZE should be a power of
       
   244 ; 2 and BASE should be a multiple of MAXSIZE. The generic code will examine the
       
   245 ; specified range of addresses and determine the actual amount of RAM if any
       
   246 ; present in the bank. The list is terminated by an entry with zero size.
       
   247 ;
       
   248 ; The pointer returned will usually be to constant data, but could equally well
       
   249 ; point to RAM if dynamic determination of the list is required.
       
   250 ;
       
   251 ; Enter with :
       
   252 ;		R10 points to super page
       
   253 ;		R12 points to ROM header
       
   254 ;		R13 points to valid stack
       
   255 ;
       
   256 ; Leave with :
       
   257 ;		R0 = pointer
       
   258 ;		Nothing else modified
       
   259 ;*******************************************************************************
       
   260 	EXPORT	GetRamBanks
       
   261 GetRamBanks	ROUT
       
   262 	    push    {r1-r3,lr}
       
   263 		mov		r0, #KHwRamSizeMb
       
   264 		lsl		r2, r0, #20			    ; R2 = RAM size in bytes
       
   265 		mov		r1, #KHwRamBaseAddr		; R1 = base address of usable RAM area
       
   266 		sub		r2, r1				    ; R2 = size of usable RAM area
       
   267 		orr		r1, #RAM_VERBATIM   	; prevent testing (overlay would break it)
       
   268 		mov		r3, #0
       
   269 		mov		lr, #0					; terminator
       
   270 		add		r0, r10, #CpuPageOffset	;
       
   271 		stm	    r0, {r1-r3,lr}			; store single bank descriptor and terminator
       
   272 		pop     {r1-r3,pc}
       
   273 
       
   274 ;*******************************************************************************
       
   275 ; Get a pointer to the list of ROM banks
       
   276 ;
       
   277 ; The pointer returned should point to a list of entries of SRomBank structures,
       
   278 ; usually declared with the ROM_BANK macro.
       
   279 ; The list is terminated by a zero size entry (four zero words)
       
   280 ;
       
   281 ; ROM_BANK	PB, SIZE, LB, W, T, RS, SS
       
   282 ; PB = physical base address of bank
       
   283 ; SIZE = size of bank
       
   284 ; LB = linear base if override required - usually set this to 0
       
   285 ; W = bus width (ROM_WIDTH_8, ROM_WIDTH_16, ROM_WIDTH_32)
       
   286 ; T = type (see TRomType enum in kernboot.h)
       
   287 ; RS = random speed
       
   288 ; SS = sequential speed
       
   289 ;
       
   290 ; Only PB, SIZE, LB are used by the rest of the bootstrap.
       
   291 ; The information given here can be modified by the SetupRomBank call, if
       
   292 ; dynamic detection and sizing of ROMs is required.
       
   293 ;
       
   294 ; Enter with :
       
   295 ;		R10 points to super page
       
   296 ;		R12 points to ROM header
       
   297 ;		R13 points to valid stack
       
   298 ;
       
   299 ; Leave with :
       
   300 ;		R0 = pointer
       
   301 ;		Nothing else modified
       
   302 ;*******************************************************************************
       
   303 	EXPORT	GetRomBanks
       
   304 GetRomBanks	ROUT
       
   305         adr		r0, RomBanksFlashTable      ; NOR flash
       
   306         bx      lr
       
   307 
       
   308 RomBanksFlashTable
       
   309 		ROM_BANK	KHwNorFlashBaseAddr, KHwNorFlashCodeSize, 0, ROM_WIDTH_32, ERomTypeXIPFlash, 0, 0
       
   310 		DCD		0,0,0,0			; terminator
       
   311 
       
   312 ;*******************************************************************************
       
   313 ; Set up RAM bank
       
   314 ;
       
   315 ; Do any additional RAM controller initialisation for each RAM bank which wasn't
       
   316 ; done by InitialiseHardware.
       
   317 ; Called twice for each RAM bank :-
       
   318 ;	First with R3 = 0xFFFFFFFF before bank has been probed
       
   319 ;	Then, if RAM is present, with R3 indicating validity of each byte lane, ie
       
   320 ;	R3 bit 0=1 if D0-7 are valid, bit1=1 if D8-15 are valid etc.
       
   321 ; For each call R1 specifies the bank physical base address.
       
   322 ;
       
   323 ; Enter with :
       
   324 ;		R10 points to super page
       
   325 ;		R12 points to ROM header
       
   326 ;		R13 points to stack
       
   327 ;		R1 = physical base address of bank
       
   328 ;		R3 = width (bottom 4 bits indicate validity of byte lanes)
       
   329 ;			 0xffffffff = preliminary initialise
       
   330 ;
       
   331 ; Leave with :
       
   332 ;		No registers modified
       
   333 ;*******************************************************************************
       
   334 	EXPORT	SetupRamBank
       
   335 SetupRamBank	ROUT
       
   336 		bx      lr
       
   337 
       
   338 ;*******************************************************************************
       
   339 ; Set up ROM bank
       
   340 ;
       
   341 ; Do any required autodetection and autosizing of ROMs and any additional memory
       
   342 ; controller initialisation for each ROM bank which wasn't done by
       
   343 ; InitialiseHardware.
       
   344 ;
       
   345 ; The first time this function is called R11=0 and R0 points to the list of
       
   346 ; ROM banks returned by the BTF_RomBanks call. This allows any preliminary setup
       
   347 ; before autodetection begins.
       
   348 ;
       
   349 ; This function is subsequently called once for each ROM bank with R11 pointing
       
   350 ; to the current information held about that ROM bank (SRomBank structure).
       
   351 ; The structure pointed to by R11 should be updated with the size and width
       
   352 ; determined. The size should be set to zero if there is no ROM present in the
       
   353 ; bank.
       
   354 ;
       
   355 ; Enter with :
       
   356 ;		R10 points to super page
       
   357 ;		R12 points to ROM header
       
   358 ;		R13 points to stack
       
   359 ;		R11 points to SRomBank info for this bank
       
   360 ;		R11 = 0 for preliminary initialise (all banks)
       
   361 ;
       
   362 ; Leave with :
       
   363 ;		Update SRomBank info with detected size/width
       
   364 ;		Set the size field to 0 if the ROM bank is absent
       
   365 ;		Can modify R0-R4 but not other registers
       
   366 ;
       
   367 ;*******************************************************************************
       
   368 	EXPORT	SetupRomBank
       
   369 SetupRomBank	ROUT						    ; only get here if running from ROM
       
   370 		cmp		r11, #0
       
   371 		bxeq	lr						        ; don't do anything for preliminary
       
   372 		ldm	    r11, {r0,r1}				    ; r0 = base, r1 = size
       
   373         lsr     r0, pc, #20
       
   374         lsl     r0, #20                         ; r0 = image base
       
   375    		ldr		r1, [r12, #TRomHeader_iRomSize] ; r1 = size of ROM block
       
   376 		stm 	r11, {r0,r1}
       
   377         bx      lr
       
   378 
       
   379 ;*******************************************************************************
       
   380 ; Reserve physical memory
       
   381 ;
       
   382 ; Reserve any physical RAM needed for platform-specific purposes before the
       
   383 ; bootstrap begins allocating RAM for page tables/kernel data etc.
       
   384 ;
       
   385 ; There are two methods for this:
       
   386 ;	1.	The function ExciseRamArea may be used. This will remove a contiguous
       
   387 ;		region of physical RAM from the RAM bank list. That region will never
       
   388 ;		again be identified as RAM.
       
   389 ;	2.	A list of excluded physical address ranges may be written at [R11].
       
   390 ;		This should be a list of (base,size) pairs terminated by a (0,0) entry.
       
   391 ;		This RAM will still be identified as RAM by the kernel but will not
       
   392 ;		be allocated by the bootstrap and will subsequently be marked as
       
   393 ;		allocated by the kernel immediately after boot.
       
   394 ;
       
   395 ; Enter with :
       
   396 ;		R10 points to super page
       
   397 ;		R11 indicates where preallocated RAM list should be written.
       
   398 ;		R12 points to ROM header
       
   399 ;		R13 points to stack
       
   400 ;
       
   401 ; Leave with :
       
   402 ;		R0-R3 may be modified. Other registers should be preserved.
       
   403 ;*******************************************************************************
       
   404 	EXPORT	ReservePhysicalMemory
       
   405 ReservePhysicalMemory	ROUT
       
   406 		bx      lr
       
   407 
       
   408 ;*******************************************************************************
       
   409 ; Do final platform-specific initialisation before booting the kernel
       
   410 ;
       
   411 ; Typical uses for this call would be:
       
   412 ;	1.	Mapping cache flushing areas
       
   413 ;	2.	Setting up pointers to routines in the bootstrap which are used by
       
   414 ;		the variant or drivers (eg idle code).
       
   415 ;
       
   416 ; Enter with :
       
   417 ;		R10 points to super page
       
   418 ;		R11 points to TRomImageHeader for the kernel
       
   419 ;		R12 points to ROM header
       
   420 ;		R13 points to stack
       
   421 ;
       
   422 ; Leave with :
       
   423 ;		R0-R9 may be modified. Other registers should be preserved.
       
   424 ;
       
   425 ;*******************************************************************************
       
   426 	EXPORT	FinalInitialise
       
   427 FinalInitialise ROUT
       
   428 		bx      lr
       
   429 
       
   430 ;*******************************************************************************
       
   431 ; Debug port write routine associated with debug port in the super page
       
   432 ; Enter with :
       
   433 ;		R0  character to be written
       
   434 ;		R12 points to rom header
       
   435 ;		R13 points to valid stack
       
   436 ;
       
   437 ; Leave with :
       
   438 ;		nothing modified 
       
   439 ;*******************************************************************************
       
   440 	EXPORT	DoWriteC
       
   441 DoWriteC	ROUT
       
   442 	IF	CFG_DebugBootRom
       
   443 		push    {r1,lr}
       
   444 		bl		GetDebugPortBase			; r1 = base address of UART registers
       
   445 	
       
   446 		str		r0, [r1, #4]				; Store to data register
       
   447 
       
   448 		pop     {r1,pc}
       
   449 	ELSE
       
   450 		bx      lr
       
   451 	ENDIF
       
   452 
       
   453 ;*******************************************************************************
       
   454 ; Initialise the debug port
       
   455 ;
       
   456 ; Enter with :
       
   457 ;		R12 points to ROM header
       
   458 ;		There is no valid stack
       
   459 ;
       
   460 ; Leave with :
       
   461 ;		R0-R2 modified
       
   462 ;		Other registers unmodified
       
   463 ;*******************************************************************************
       
   464 InitDebugPort	ROUT
       
   465 		GET_ADDRESS	r1, KHwBaseUart0, KHwLinBaseUart0
       
   466 		ldr		r0,[r1, #0]		
       
   467 		bx		lr
       
   468 
       
   469 ;*******************************************************************************
       
   470 ; Get the base address of the debug UART
       
   471 ;
       
   472 ; Enter with :
       
   473 ;		R12 points to ROM header
       
   474 ;		There may be no stack
       
   475 ;
       
   476 ; Leave with :
       
   477 ;		R1 = base address of port, 0 for JTAG
       
   478 ;		Z flag set for JTAG, clear for non-JTAG
       
   479 ;		No other registers modified
       
   480 ;*******************************************************************************
       
   481 GetDebugPortBase	ROUT
       
   482 		ldr		r1, [r12, #TRomHeader_iDebugPort]
       
   483 		cmp		r1, #42							; JTAG?
       
   484 		movseq	r1, #0
       
   485 		bxeq	lr							    ; yes - return 0 and set Z
       
   486 		cmp		r1, #1
       
   487         blo     GetUartPort0          
       
   488         beq     GetUartPort1
       
   489 		cmp		r1, #3
       
   490         blo     GetUartPort2
       
   491 		beq		GetUartPort3
       
   492 GetUartPort0
       
   493 		GET_ADDRESS	r1, KHwBaseUart0, KHwLinBaseUart0
       
   494 		movs	r1, r1							; clear Z
       
   495 		bx      lr
       
   496 
       
   497 GetUartPort1
       
   498 		GET_ADDRESS	r1, KHwBaseUart1, KHwLinBaseUart1
       
   499 		movs	r1, r1							; clear Z
       
   500 		bx      lr
       
   501 
       
   502 GetUartPort2
       
   503 		GET_ADDRESS	r1, KHwBaseUart2, KHwLinBaseUart2
       
   504 		movs	r1, r1							; clear Z
       
   505 		bx      lr
       
   506 
       
   507 GetUartPort3
       
   508 		GET_ADDRESS	r1, KHwBaseUart3, KHwLinBaseUart3
       
   509 		movs	r1, r1							; clear Z
       
   510 		bx      lr
       
   511 
       
   512 ;*******************************************************************************
       
   513 ; Return parameter specified by R0 (see TBootParam enum)
       
   514 ;
       
   515 ; Enter with :
       
   516 ;		R0 = parameter number
       
   517 ;
       
   518 ; Leave with :
       
   519 ;		If parameter value is supplied, R0 = value and N flag clear
       
   520 ;		If parameter value is not supplied, N flag set. In this case the
       
   521 ;		parameter may be defaulted or the system may fault.
       
   522 ;		R0, R1 modified. No other registers modified.
       
   523 ;
       
   524 ;*******************************************************************************
       
   525 GetParameters ROUT
       
   526 		adr		r1, ParameterTable
       
   527 		b		FindParameter
       
   528 
       
   529 ParameterTable
       
   530 		DCD		-1								; terminator
       
   531 
       
   532 ;*******************************************************************************
       
   533 ; BOOT FUNCTION TABLE
       
   534 ;*******************************************************************************
       
   535 GetBootTableAddress	ROUT
       
   536 		adr		r0, SyborgBootTable
       
   537         bx      lr
       
   538 
       
   539 SyborgBootTable
       
   540 		DCD	DoWriteC					; output a debug character
       
   541 		DCD	GetRamBanks					; get list of RAM banks
       
   542 		DCD	SetupRamBank				; set up a RAM bank
       
   543 		DCD	GetRomBanks					; get list of ROM banks
       
   544 		DCD	SetupRomBank				; set up a ROM bank
       
   545 		DCD	GetHwBanks					; get list of HW banks
       
   546 		DCD	ReservePhysicalMemory		; reserve physical RAM if required
       
   547 		DCD	GetParameters				; get addresses for direct memory model
       
   548 		DCD	FinalInitialise				; Final initialisation before booting the kernel
       
   549 		DCD	HandleAllocRequest			; allocate memory (usually in generic code)
       
   550 		DCD	GetPdeValue					; usually in generic code
       
   551 		DCD	GetPteValue					; usually in generic code
       
   552 		DCD	PageTableUpdate				; usually in generic code
       
   553 		DCD	EnableMmu					; Enable the MMU (usually in generic code)
       
   554 
       
   555 ; These entries specify the standard MMU permissions for various areas
       
   556 		
       
   557 	IF  CFG_MMMultiple
       
   558 ;	IF  CFG_MMFlexible
       
   559 	    IF CFG_ARMV7
       
   560 		BTP_ENTRY   CLIENT_DOMAIN, PERM_RORO, MEMORY_FULLY_CACHED,       	1,  1,  0,  0   ; ROM
       
   561 		BTP_ENTRY   CLIENT_DOMAIN, PERM_RWNO, MEMORY_FULLY_CACHED,       	0,  1,  0,  0   ; kernel data/stack/heap
       
   562 		BTP_ENTRY   CLIENT_DOMAIN, PERM_RWNO, MEMORY_FULLY_CACHED,       	0,  1,  0,  0   ; super page/CPU page
       
   563 		BTP_ENTRY   CLIENT_DOMAIN, PERM_RWNO, MEMORY_FULLY_CACHED,  	0,  1,  0,  0   ; page directory/tables
       
   564 		BTP_ENTRY   CLIENT_DOMAIN, PERM_RONO, MEMORY_FULLY_CACHED,       	1,  1,  0,  0   ; exception vectors
       
   565 		BTP_ENTRY   CLIENT_DOMAIN, PERM_RWNO, MEMORY_STRONGLY_ORDERED,      0,  1,  0,  0   ; hardware registers
       
   566 		DCD         0                                                           ; unused (minicache flush)
       
   567 		DCD         0                                                           ; unused (maincache flush)
       
   568 		BTP_ENTRY   CLIENT_DOMAIN, PERM_RWNO, MEMORY_FULLY_CACHED,       	0,  1,  0,  0   ; page table info
       
   569 		BTP_ENTRY   CLIENT_DOMAIN, PERM_RWRW, MEMORY_FULLY_CACHED,       	1,  1,  0,  0   ; user RAM
       
   570 		BTP_ENTRY   CLIENT_DOMAIN, PERM_RONO, MEMORY_STRONGLY_ORDERED,      1,  1,  0,  0   ; temporary identity mapping
       
   571 		BTP_ENTRY   CLIENT_DOMAIN, UNC_PERM,  MEMORY_STRONGLY_ORDERED,      0,  1,  0,  0   ; uncached
       
   572 	    ENDIF	
       
   573 	    IF CFG_ARMV6
       
   574 		BTP_ENTRY   CLIENT_DOMAIN, PERM_RORO, CACHE_WBWA,       1,  1,  0,  0       ; ROM
       
   575 	        BTP_ENTRY   CLIENT_DOMAIN, PERM_RWNO, CACHE_WBWA,       0,  1,  0,  0       ; kernel data/stack/heap
       
   576 	        BTP_ENTRY   CLIENT_DOMAIN, PERM_RWNO, CACHE_WBWA,       0,  1,  0,  0       ; super page/CPU page
       
   577 		BTP_ENTRY   CLIENT_DOMAIN, PERM_RWNO, CACHE_WBWA,		0,  1,  0,  0       ; page directory/tables
       
   578 	        BTP_ENTRY   CLIENT_DOMAIN, PERM_RONO, CACHE_WTRA,       1,  1,  0,  0       ; exception vectors
       
   579 		BTP_ENTRY   CLIENT_DOMAIN, PERM_RWNO, CACHE_SO,         0,  1,  0,  0       ; hardware registers
       
   580 		DCD			0										; unused (minicache flush)
       
   581 		DCD			0										; unused (maincache flush)
       
   582 	        BTP_ENTRY   CLIENT_DOMAIN, PERM_RWNO, CACHE_WBWA,       0,  1,  0,  0       ; page table info
       
   583 	        BTP_ENTRY   CLIENT_DOMAIN, PERM_RWRW, CACHE_WBWA,       1,  1,  0,  0       ; user RAM
       
   584 		BTP_ENTRY   CLIENT_DOMAIN, PERM_RONO, CACHE_SO,         1,  1,  0,  0       ; temporary identity mapping
       
   585 	        BTP_ENTRY   CLIENT_DOMAIN, UNC_PERM,  CACHE_SO,         0,  1,  0,  0       ; uncached
       
   586 	    ENDIF
       
   587 	ENDIF
       
   588 	IF CFG_MMMoving
       
   589 		BTP_ENTRY	CLIENT_DOMAIN, PERM_RORO, CACHE_WT		; ROM
       
   590 		BTP_ENTRY	CLIENT_DOMAIN, PERM_RWNO, CACHE_WB		; kernel data/stack/heap
       
   591 		BTP_ENTRY	CLIENT_DOMAIN, PERM_RWNO, CACHE_WB		; super page/CPU page
       
   592 		BTP_ENTRY	CLIENT_DOMAIN, PERM_RWNO, CACHE_WT		; page directory/tables
       
   593 		BTP_ENTRY	CLIENT_DOMAIN, PERM_RORO, CACHE_WT		; exception vectors
       
   594 		BTP_ENTRY	CLIENT_DOMAIN, PERM_RWRO, CACHE_NCNB	; hardware registers
       
   595 		DCD			0										; unused (minicache flush)
       
   596 		DCD			0										; unused (maincache flush)
       
   597 		BTP_ENTRY	CLIENT_DOMAIN, PERM_RWNO, CACHE_WB		; page table info
       
   598 		BTP_ENTRY	CLIENT_DOMAIN, PERM_RWRW, CACHE_WB		; user RAM
       
   599 		BTP_ENTRY	CLIENT_DOMAIN, PERM_RORO, CACHE_NCNB	; temporary identity mapping
       
   600 		BTP_ENTRY	CLIENT_DOMAIN, UNC_PERM,  CACHE_NCNB	; uncached
       
   601 	ENDIF
       
   602 
       
   603 	END