baseport/syborg/variant.mmh
changeset 2 d55eb581a87c
parent 0 ffa851df0825
child 3 c2946f91d81f
equal deleted inserted replaced
1:2fb8b9db1c86 2:d55eb581a87c
       
     1 /*
       
     2 * Copyright (c) 2009 Nokia Corporation and/or its subsidiary(-ies).
       
     3 * All rights reserved.
       
     4 * This component and the accompanying materials are made available
       
     5 * under the terms of the License "Eclipse Public License v1.0"
       
     6 * which accompanies this distribution, and is available
       
     7 * at the URL "http://www.eclipse.org/legal/epl-v10.html".
       
     8 *
       
     9 * Initial Contributors:
       
    10 * Nokia Corporation - initial contribution.
       
    11 *
       
    12 * Contributors:
       
    13 *
       
    14 * Description:
       
    15 *
       
    16 */
       
    17 
       
    18 //macro   __CPU_ARM926J__
       
    19 //#define __CPU__ ARM926EJ-S
       
    20 
       
    21 //macro __CPU_ARM1136__
       
    22 
       
    23 //#define __CPU_ARM1176__
       
    24 
       
    25 macro __CPU_CORTEX_A8N__
       
    26 macro __VFP_V3
       
    27 #define SYBORG
       
    28 macro __SYBORG__
       
    29 
       
    30 #define MM_MULTIPLE
       
    31 //#define MM_FLEXIBLE
       
    32 
       
    33 // TO DO: decide if we need to switch these on or off!!
       
    34 //
       
    35 // Uncomment the following line if using the r1p0 release or later of the ARM1136 processor.
       
    36 // 
       
    37 //#define __CPU_ARM1136_IS_R1__
       
    38 //
       
    39 
       
    40 /* Uncomment if ARM1136 Erratum 351912
       
    41  * "VFP11 double precision multiply can corrupt data"
       
    42  * is fixed on this hardware.
       
    43  */
       
    44 //macro __CPU_ARM1136_ERRATUM_351912_FIXED
       
    45 
       
    46 /* Uncomment if ARM1136 Erratum 353494
       
    47  * "Rare conditions can cause corruption of the Instruction Cache"
       
    48  * is fixed on this hardware.
       
    49  */
       
    50 //macro __CPU_ARM1136_ERRATUM_353494_FIXED
       
    51 
       
    52 /* Uncomment if ARM1136 Erratum 371025
       
    53  * "Invalidate Instruction Cache operation can fail"
       
    54  * is fixed on this hardware.
       
    55  */
       
    56 //macro __CPU_ARM1136_ERRATUM_371025_FIXED
       
    57 
       
    58 /* Uncomment if using ARM1136 processor and ARM1136 Erratum 399234
       
    59  * "Write back data cache entry evicted by write through entry causes data corruption"
       
    60  * is fixed on this hardware.
       
    61  * Workaround
       
    62  * The erratum may be avoided by marking all cacheable memory as one of write through or write back.
       
    63  * This requires the memory attributes described in the translation tables to be modified by software
       
    64  * appropriately, or the use of the remapping capability to remap write through regions to non cacheable.
       
    65  * If this macro is enabled, it should be acompanied by:
       
    66  *					GBLL	CFG_CPU_ARM1136_ERRATUM_399234_FIXED in config.inc
       
    67  */
       
    68 //macro __CPU_ARM1136_ERRATUM_399234_FIXED
       
    69 
       
    70 /* Uncomment if ARM1136 Erratum 408022 "Cancelled write to CONTEXTID register might update ASID" 
       
    71  * is fixed on this hardware.
       
    72  */
       
    73 //macro __CPU_ARM1136_ERRATUM_408022_FIXED
       
    74 
       
    75 // TO DO:
       
    76 //
       
    77 // Uncomment the next line if using the ARM1136 processor and ARM1136 Erratum 406973
       
    78 // "CLREX instruction might be ignored during data cache line fill"
       
    79 // is fixed on this hardware.
       
    80 // 
       
    81 //#define __CPU_ARM1136_ERRATUM_406973_FIXED
       
    82 
       
    83 
       
    84 // Uncomment if:
       
    85 //	1)	using ARM1136 processor and ARM1136 Erratum 411920: "Invalidate Entire Instruction Cache
       
    86 //	  	operation might fail to invalidate some lines if coincident with linefill"
       
    87 //  	  	is fixed on this hardware, or
       
    88 //	2)	using ARM1176 processor and ARM1176 Erratum 415045: "Invalidate Entire Instruction Cache
       
    89 // 	  	operation might fail to invalidate some lines if coincident with linefill
       
    90 //	  	is fixed on this hardware.
       
    91 // Workaround:
       
    92 //	1)	Disables the use of of prefetch range cache operations by setting RV bit in Auxiliary Ctrl Reg.
       
    93 //	2)	Replaces Invalidate ICache operation with the sequence defined in the errata document.
       
    94 // If this macro is enabled, it should be accompanied by:
       
    95 // 	"GBLL CFG_CPU_ARM1136_ERRATUM_411920_FIXED" in variant.mmh
       
    96 //
       
    97 //macro __CPU_ARM1136_ERRATUM_411920_FIXED
       
    98 
       
    99 
       
   100 
       
   101 macro __CPU_HAS_VFP
       
   102 #define USE_VFP_MATH
       
   103 // !@! not moving when 1136
       
   104 //#define MM_MOVING
       
   105 macro __DEBUGGER_SUPPORT__
       
   106 macro FASTTRACE_KERNEL_ALL
       
   107 macro __EMI_SUPPORT__
       
   108 
       
   109 #define VariantTarget(name,ext)     _syborg_##name##.##ext
       
   110 #define AsspNKernIncludePath        \..\..\src\cedar\generic\base\syborg\specific
       
   111 #define VariantMediaDefIncludePath  AsspNKernIncludePath        
       
   112 #define PlatformLib		   		    kasyborg.lib
       
   113 
       
   114 systeminclude	\epoc32\include\memmodel\epoc\mmubase
       
   115 //systeminclude	\epoc32\include\memmodel\epoc\moving
       
   116 //systeminclude	\epoc32\include\memmodel\epoc\moving\arm
       
   117 //systeminclude	\epoc32\include\memmodel\epoc\flexible
       
   118 //systeminclude	\epoc32\include\memmodel\epoc\flexible\arm
       
   119 systeminclude	\epoc32\include\memmodel\epoc\multiple
       
   120 systeminclude	\epoc32\include\memmodel\epoc\multiple\arm
       
   121 
       
   122 systeminclude	..\soc\interface
       
   123 
       
   124 // Uncomment for T_USERCOMDEB test
       
   125 //#define BUILD_TESTS
       
   126 
       
   127 #ifdef BUILD_TESTS
       
   128 macro BTRACE_KERNEL_ALL
       
   129 #endif
       
   130 
       
   131 //OPTION_REPLACE	ARMCC  --cpu __CPU__
       
   132 //OPTION_REPLACE	ARMASM --cpu __CPU__