omap3530/beagle_drivers/usbv/usbv.cpp
author arunabha
Wed, 03 Mar 2010 13:10:32 +0000
changeset 23 117faf51deac
parent 0 6663340f3fc9
child 51 254b9435d75e
permissions -rwxr-xr-x
Bug 1996 - Contribution for West Bridge Astoria Symbian Storage Driver this storage driver is for the West Bridge Astoria chipset. This device has a USB, SD and processor port for communication with a baseband processor. In our port, we connected this device DVK to the Beagleboard through the SPI interface of the OMAP3. After driver installation, the Symbian OS can see an external device or D: drive represented by the SD card. In this driver, the USB interface is not used directly, though this may be the subject of future contributions. The appropriate way to test the driver is to access the external volume and do file read and write to it, pretty much the same way you would test a thumb drive on your PC
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// Copyright (c) 2004-2009 Nokia Corporation and/or its subsidiary(-ies).
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// All rights reserved.
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// This component and the accompanying materials are made available
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// under the terms of the License "Eclipse Public License v1.0"
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// which accompanies this distribution, and is available
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// at the URL "http://www.eclipse.org/legal/epl-v10.html".
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//
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// Initial Contributors:
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// Nokia Corporation - initial contribution.
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//
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// Contributors:
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//
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// Description:
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// omap3530/beagle_drivers/usb/usbv.cpp
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//
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#include <kernel.h>
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#include <assp/omap3530_assp/omap3530_usbc.h>
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// Platform-dependent USB client controller layer (USB PSL).
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#include <assp/omap3530_assp/omap3530_i2c.h>
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#include <assp/omap3530_assp/omap3530_i2creg.h>
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#include <assp/omap3530_shared/tps65950.h>
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// I2C Bit definitions
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// PHY_CLK_CTRL
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const TUint KCLK32K_EN = KBit1;
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const TUint KREQ_PHY_DPLL_CLK = KBit0;
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// PHY_CLK_STS
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const TUint KPHY_DPLL_CLK = KBit0;
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// MCPC_CTRL2
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const TUint KMPC_CLK_EN = KBit0;
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// FUNC_CTRL
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const TUint KXCVRSELECT_HS = 0x0;
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const TUint KXCVRSELECT_FS = KBit0;
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const TUint KXCVRSELECT_MASK = 0x3;
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const TUint KTERMSELECT = KBit2;
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const TUint KOPMODE_DISABLED = KBit4;
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const TUint KOPMODE_MASK = KBit3 | KBit4;
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// MCPC_IO_CTRL
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const TUint KRXD_PU = KBit3;
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// OTG_CTRL
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const TUint KDPPULLDOWN = KBit1;
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const TUint KDMPULLDOWN = KBit2;
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// POWER_CTRL
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const TUint KOTG_EN = KBit5;
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// VUSB???_DEV_GRP
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const TUint KDEV_GRP_P1 = KBit5;
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// CFG_BOOT
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const TUint KHFCLK_FREQ_26Mhz = KBit1;
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NONSHARABLE_CLASS( TBeagleUsbPhy ) : public MOmap3530UsbPhy
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	{
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public:
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	TBeagleUsbPhy();
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	TInt Construct();
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	virtual void StartPHY();
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	virtual void SetPHYMode( DOmap3530Usbcc::TPHYMode aMode );
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	virtual void EnablePHY();
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	virtual void DisablePHY();
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private:
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	TInt iPHYEnabled;
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	};
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TBeagleUsbPhy::TBeagleUsbPhy()
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	{
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	}
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TInt TBeagleUsbPhy::Construct()
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	{
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	return KErrNone;
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	}
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void TBeagleUsbPhy::StartPHY()
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	{
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	// PHY clock must be enabled before this point (can't enable it in this function as it is called from an ISR context)
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	TPS65950::DisableProtect();
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	// Enable the USB LDO's (low-dropout regulators)
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	TPS65950::ClearSetSync(TPS65950::Register::VUSB1V5_DEV_GRP,0x00,KDEV_GRP_P1);
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	TPS65950::ClearSetSync(TPS65950::Register::VUSB1V8_DEV_GRP,0x00,KDEV_GRP_P1);
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	TPS65950::ClearSetSync(TPS65950::Register::VUSB3V1_DEV_GRP,0x00,KDEV_GRP_P1);
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	TPS65950::ClearSetSync(TPS65950::Register::CFG_BOOT,0x00, KHFCLK_FREQ_26Mhz);	
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	TPS65950::RestoreProtect();
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	}
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void TBeagleUsbPhy::SetPHYMode( DOmap3530Usbcc::TPHYMode aMode )
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	{
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	EnablePHY();
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	switch(aMode)
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		{
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		// Configure trancever (see swcu05b.pdf table 15-21 D+/D- Termination settings) 
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		case DOmap3530Usbcc::ENormal:
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			TPS65950::WriteSync(TPS65950::Register::MCPC_CTRL2_CLR, KMPC_CLK_EN); // Not UART Mode
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			TPS65950::WriteSync(TPS65950::Register::FUNC_CTRL_CLR,(KXCVRSELECT_MASK | KTERMSELECT | KOPMODE_DISABLED ));	 // XCVRSELECT high speed mode (HS), TERM SELECT=0, OPMODE=0 (normal operation)	
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			TPS65950::WriteSync(TPS65950::Register::MCPC_IO_CTRL_CLR, KRXD_PU);
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			TPS65950::WriteSync(TPS65950::Register::OTG_CTRL_CLR, KDPPULLDOWN | KDMPULLDOWN); // Disable DP pulldown 
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			TPS65950::WriteSync(TPS65950::Register::POWER_CTRL_SET, KOTG_EN);
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			break;
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		case DOmap3530Usbcc::EPowerUp:
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			// Power up or VBUS<VSESSEND			
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			TPS65950::WriteSync(TPS65950::Register::MCPC_CTRL2_CLR, KMPC_CLK_EN); // Not UART Mode
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			TPS65950::WriteSync(TPS65950::Register::FUNC_CTRL, KXCVRSELECT_FS);		 // XXcvr Select 01, Term select 0, opmode 0,
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			TPS65950::WriteSync(TPS65950::Register::OTG_CTRL_SET, KDPPULLDOWN | KDMPULLDOWN); // Disable DP pulldown 
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			TPS65950::WriteSync(TPS65950::Register::POWER_CTRL_CLR, KOTG_EN); // Power down OTG
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			break;
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		case DOmap3530Usbcc::EPeripheralChirp:
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			// OTG device Peripheral chirp			
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			TPS65950::WriteSync(TPS65950::Register::MCPC_CTRL2_CLR, KMPC_CLK_EN); // Not UART Mode
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			TPS65950::WriteSync(TPS65950::Register::FUNC_CTRL,(KXCVRSELECT_HS | KTERMSELECT | KOPMODE_MASK )); //Term select 1, opmode 10,  Xcvr Select 00,
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			TPS65950::WriteSync(TPS65950::Register::MCPC_IO_CTRL_CLR, KRXD_PU);
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			TPS65950::WriteSync(TPS65950::Register::OTG_CTRL_CLR, KDPPULLDOWN | KDMPULLDOWN); // Disable DP pulldown 
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			TPS65950::WriteSync(TPS65950::Register::POWER_CTRL_SET, KOTG_EN);
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			break;
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		case DOmap3530Usbcc::EUART:
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			// UART Mode
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			TPS65950::WriteSync(TPS65950::Register::MCPC_CTRL2_SET, KMPC_CLK_EN); // Not UART Mode
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			TPS65950::WriteSync(TPS65950::Register::MCPC_IO_CTRL_SET, KRXD_PU);
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			break;
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		default:
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			// Don't change mode
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			break;
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		}
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	DisablePHY();
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	}
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// The PHY 60Mhz clock must be enabled before Register accesses are attempted.
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void TBeagleUsbPhy::EnablePHY()
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	{
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	__KTRACE_OPT(KUSB, Kern::Printf("TBeagleUsbPhy::EnablePHY"));	
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	if(iPHYEnabled==0)
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		{		
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		TPS65950::WriteSync(TPS65950::Register::PHY_CLK_CTRL, KREQ_PHY_DPLL_CLK | KCLK32K_EN);
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		TUint8 val=0;
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		TInt retries =0;
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		do
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			{
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			TPS65950::ReadSync(TPS65950::Register::PHY_CLK_CTRL_STS, val);
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			NKern::Sleep( NKern::TimerTicks( 1 ) );
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			//Kern::NanoWait(50000); // wait 1/2 millis to prevent soak
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			retries++;
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			}
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		while(! (val & KPHY_DPLL_CLK) && (retries < 1000) );
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		__ASSERT_ALWAYS(retries < 1000,Kern::Fault("TBeagleUsbPhy::EnablePHY Cant enable in 5s ",__LINE__));		
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		__KTRACE_OPT(KUSB, Kern::Printf("TBeagleUsbPhy: PHY Enabled"));
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		}
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	iPHYEnabled++;
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	}
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void TBeagleUsbPhy::DisablePHY()
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	{
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	__KTRACE_OPT(KUSB, Kern::Printf("TBeagleUsbPhy::DisablePHY"));
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	if(iPHYEnabled==1)
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		{
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		TPS65950::WriteSync(TPS65950::Register::PHY_CLK_CTRL, 0x0);			
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		}
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	if(iPHYEnabled>0)
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		{
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		iPHYEnabled--;
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		}
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	}
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EXPORT_C MOmap3530UsbPhy* MOmap3530UsbPhy::New()
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	{
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	__KTRACE_OPT(KUSB, Kern::Printf(" > Initializing USB PHY"));
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	TBeagleUsbPhy* const phy = new TBeagleUsbPhy;
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	if (!phy)
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		{
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		__KTRACE_OPT(KPANIC, Kern::Printf("  Error: Memory allocation for TBeagleUsbPhy failed"));
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		return NULL;
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		}
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	TInt r;
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	if ((r = phy->Construct()) != KErrNone)
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		{
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		__KTRACE_OPT(KPANIC, Kern::Printf("  Error: Construction of TBeagleUsbPhy failed (%d)", r));
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		delete phy;
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		return NULL;
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		}
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	return phy;
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	}
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DECLARE_STANDARD_EXTENSION()
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	{
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	return KErrNone;
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	}
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   202