0
+ − 1 // Copyright (c) 2009 Nokia Corporation and/or its subsidiary(-ies).
+ − 2 // All rights reserved.
+ − 3 // This component and the accompanying materials are made available
+ − 4 // under the terms of the License "Eclipse Public License v1.0"
+ − 5 // which accompanies this distribution, and is available
+ − 6 // at the URL "http://www.eclipse.org/legal/epl-v10.html".
+ − 7 //
+ − 8 // Initial Contributors:
+ − 9 // Nokia Corporation - initial contribution.
+ − 10 //
+ − 11 // Contributors:
+ − 12 //
+ − 13 // Description:
+ − 14 // /omap3530/assp/inc/omap3530_timer.h
+ − 15 //
+ − 16
+ − 17 #ifndef HEADER_OMAP3530_TIMER_H_INCLUDED
+ − 18 # define HEADER_OMAP3530_TIMER_H_INCLUDED
+ − 19
+ − 20 /**
+ − 21 @file
+ − 22 omap3530_timer.h header file
+ − 23 This file provides timer handling for the omap3530 timers
+ − 24 @publishedAll
+ − 25 @released
+ − 26 */
+ − 27
+ − 28 #include <assp/omap3530_assp/omap3530_hardware_base.h>
+ − 29 #include <assp/omap3530_assp/omap3530_irqmap.h>
+ − 30
+ − 31 namespace TexasInstruments
+ − 32 {
+ − 33
+ − 34 namespace Omap3530
+ − 35 {
+ − 36
+ − 37
+ − 38 namespace GPTimer
+ − 39 {
+ − 40
+ − 41 namespace TIOCP_CFG
+ − 42 {
+ − 43 /**
+ − 44 0 AUTOIDLE Internal L4 interface clock gating strategy 0
+ − 45 0x0: L4 interface clock is free-running.
+ − 46 0x1: Automatic L4 interface clock gating strategy isapplied, based on the L4 interface activity.
+ − 47 */
+ − 48 typedef TSingleBitField<0> T_AUTOIDLE ;
+ − 49
+ − 50 /**
+ − 51 1 SOFTRESET Software reset. This bit is automatically reset by the RW 0 hardware. During reads, it always returns 0.
+ − 52 0x0: Normal mode
+ − 53 0x1: The module is reset.
+ − 54 */
+ − 55 typedef TSingleBitField<1> T_SOFTRESET ;
+ − 56
+ − 57 /**
+ − 58 2 ENAWAKEUP Wake-up feature global control RW 0
+ − 59 0x0: No wake-up line assertion in idle mode
+ − 60 0x1: Wake-up line assertion enabled in smart-idle mode
+ − 61 */
+ − 62 typedef TSingleBitField<2> T_ENAWAKEUP ;
+ − 63
+ − 64 /**
+ − 65 4:3 IDLEMODE Power management, req/ack control RW 0x0
+ − 66 0x0: Force-idle. An idle request is acknowledged unconditionally.
+ − 67 0x1: No-idle. An idle request is never acknowledged.
+ − 68 0x2: Smart-idle. Acknowledgement to an idle request is given based on the internal activity of the module.
+ − 69 0x3: Reserved. Do not use.
+ − 70 */
+ − 71 class T_IDLEMODE : public TBitField<3, 2>
+ − 72 {
+ − 73 public :
+ − 74 enum TConstants
+ − 75 {
+ − 76 KForceIdle = TConstVal<0>::KValue,
+ − 77 KNoIdle = TConstVal<1>::KValue,
+ − 78 KSmartIdle = TConstVal<2>::KValue
+ − 79 } ;
+ − 80 } ;
+ − 81
+ − 82 /**
+ − 83 5 EMUFREE Emulation mode RW 0
+ − 84 0x0: Timer counter frozen in emulation
+ − 85 0x1: Timer counter free-running in emulation
+ − 86 */
+ − 87 typedef TSingleBitField<5> T_EMUFREE ;
+ − 88
+ − 89 /**
+ − 90 9:8 CLOCKACTIVITY Clock activity during wakeup mode period: RW 0x0
+ − 91 0x0: L4 interface and Functional clocks can be switched off.
+ − 92 0x1: L4 interface clock is maintained during wake-up period; Functional clock can be switched off.
+ − 93 0x2: L4 interface clock can be switched off; Functional clock is maintained during wake-up period.
+ − 94 0x3: L4 interface and Functional clocks are maintained during wake-up period.
+ − 95 */
+ − 96 class T_CLOCKACTIVITY : public TBitField<8, 2>
+ − 97 {
+ − 98 public :
+ − 99 enum TConstants
+ − 100 {
+ − 101 KMaintainNeither = TConstVal<0>::KValue,
+ − 102 KMaintainIfClock = TConstVal<1>::KValue,
+ − 103 KMaintainFuncClock = TConstVal<2>::KValue,
+ − 104 KMaintainBoth = TConstVal<3>::KValue
+ − 105 } ;
+ − 106 } ;
+ − 107
+ − 108 } ; // namespace TIOCP_CFG
+ − 109
+ − 110 namespace TISTAT
+ − 111 {
+ − 112 /**
+ − 113 0 RESETDONE Internal reset monitoring R 0
+ − 114 0x0: Internal module reset is ongoing.
+ − 115 0x1: Reset completed
+ − 116 */
+ − 117 typedef TSingleBitField<0> T_RESETDONE ;
+ − 118
+ − 119 } ; // namespace TISTAT
+ − 120
+ − 121 namespace TISR
+ − 122 {
+ − 123 /**
+ − 124 0 MAT_IT_FLAG Pending match interrupt status RW 0
+ − 125 Read 0x0: No match interrupt pending
+ − 126 Write 0x0: Status unchanged
+ − 127 Read 0x1: Match interrupt pending
+ − 128 Write 0x1: Status bit cleared
+ − 129 */
+ − 130 typedef TSingleBitField<0> T_MAT_IT_FLAG ;
+ − 131
+ − 132 /**
+ − 133 1 OVF_IT_FLAG Pending overflow interrupt status RW 0
+ − 134 Read 0x0: No overflow interrupt pending
+ − 135 Write 0x0: Status unchanged
+ − 136 Read 0x1: Overflow interrupt pending
+ − 137 Write 0x1: Status bit cleared
+ − 138 */
+ − 139 typedef TSingleBitField<1> T_OVF_IT_FLAG ;
+ − 140
+ − 141 /**
+ − 142 2 TCAR_IT_FLAG Pending capture interrupt status RW 0
+ − 143 Read 0x0: No capture interrupt event pending
+ − 144 Write 0x0: Status unchanged
+ − 145 Read 0x1: Capture interrupt event pending
+ − 146 Write 0x1: Status bit cleared
+ − 147 */
+ − 148 typedef TSingleBitField<2> T_TCAR_IT_FLAG ;
+ − 149
+ − 150 } ; // namespace TISR
+ − 151
+ − 152 namespace TIER
+ − 153 {
+ − 154 /**
+ − 155 0 MAT_IT_ENA Enable match interrupt RW 0
+ − 156 0x0: Disable match interrupt.
+ − 157 0x1: Enable match interrupt.
+ − 158 */
+ − 159 typedef TSingleBitField<0> T_MAT_IT_ENA ;
+ − 160
+ − 161 /**
+ − 162 1 OVF_IT_ENA Enable overflow interrupt RW 0
+ − 163 0x0: Disable overflow interrupt.
+ − 164 0x1: Enable overflow interrupt.
+ − 165 */
+ − 166 typedef TSingleBitField<1> T_OVF_IT_ENA ;
+ − 167
+ − 168 /**
+ − 169 2 TCAR_IT_ENA Enable capture interrupt RW 0
+ − 170 0x0: Disable capture interrupt.
+ − 171 0x1: Enable capture interrupt.
+ − 172 */
+ − 173 typedef TSingleBitField<2> T_TCAR_IT_ENA ;
+ − 174
+ − 175 } ; // namespace TIER
+ − 176
+ − 177 namespace TWER
+ − 178 {
+ − 179 /**
+ − 180 0 MAT_WUP_ENA Enable match wake-up RW 0
+ − 181 0x0: Disable match wake-up.
+ − 182 0x1: Enable match wake-up.
+ − 183 */
+ − 184 typedef TSingleBitField<0> T_MAT_WUP_ENA ;
+ − 185
+ − 186 /**
+ − 187 1 OVF_WUP_ENA Enable overflow wake-up RW 0
+ − 188 0x0: Disable overflow wake-up.
+ − 189 0x1: Enable overflow wake-up.
+ − 190 */
+ − 191 typedef TSingleBitField<1> T_OVF_WUP_ENA ;
+ − 192
+ − 193 /**
+ − 194 2 TCAR_WUP_ENA Enable capture wake-up RW 0
+ − 195 0x0: Disable capture wake-up.
+ − 196 0x1: Enable capture wake-up.
+ − 197 */
+ − 198 typedef TSingleBitField<2> T_TCAR_WUP_ENA ;
+ − 199
+ − 200 } ; // namespace TWER
+ − 201
+ − 202 namespace TCLR
+ − 203 {
+ − 204 /**
+ − 205 0 ST Start/stop timer control RW 0
+ − 206 0x0: Stop the timer
+ − 207 0x1: Start the timer
+ − 208 */
+ − 209 typedef TSingleBitField<0> T_ST ;
+ − 210
+ − 211 /**
+ − 212 1 AR Autoreload mode RW 0
+ − 213 0x0: One-shot mode overflow
+ − 214 0x1: Autoreload mode overflow
+ − 215 */
+ − 216 typedef TSingleBitField<1> T_AR ;
+ − 217
+ − 218 /**
+ − 219 4:2 PTV Trigger output mode
+ − 220 0x0: The timer counter is prescaled with the value: RW 0x0
+ − 221 2(PTV+1). Example: PTV = 3, counter increases value (if started) after 16 functional clock periods.
+ − 222 */
+ − 223 class T_PTV : public TBitField<2, 3>
+ − 224 {
+ − 225 public :
+ − 226 enum TConstants
+ − 227 {
+ − 228 KPS_2 = TConstVal<0>::KValue,
+ − 229 KPS_4 = TConstVal<1>::KValue,
+ − 230 KPS_8 = TConstVal<2>::KValue,
+ − 231 KPS_16 = TConstVal<3>::KValue,
+ − 232 KPS_32 = TConstVal<4>::KValue,
+ − 233 KPS_64 = TConstVal<5>::KValue,
+ − 234 KPS_128 = TConstVal<6>::KValue,
+ − 235 KPS_256 = TConstVal<7>::KValue
+ − 236 } ;
+ − 237 } ;
+ − 238
+ − 239 /**
+ − 240 5 PRE Prescaler enable RW 0
+ − 241 0x0: Prescaler disabled
+ − 242 0x1: Prescaler enabled
+ − 243 */
+ − 244 typedef TSingleBitField<5> T_PRE ;
+ − 245
+ − 246 /**
+ − 247 6 CE Compare enable RW 0
+ − 248 0x0: Compare disabled
+ − 249 0x1: Compare enabled
+ − 250 */
+ − 251 typedef TSingleBitField<6> T_CE ;
+ − 252
+ − 253 /**
+ − 254 7 SCPWM Pulse-width-modulation output pin default setting when RW 0
+ − 255 counter is stopped or trigger output mode is set to no trigger.
+ − 256 0x0: Default value of PWM_out output: 0
+ − 257 0x1: Default value of PWM_out output: 1
+ − 258 */
+ − 259 typedef TSingleBitField<7> T_SCPWM ;
+ − 260
+ − 261 /**
+ − 262 9:8 TCM Transition capture mode RW 0x0
+ − 263 0x0: No capture
+ − 264 0x1: Capture on rising edges of EVENT_CAPTURE pin.
+ − 265 0x2: Capture on falling edges of EVENT_CAPTURE pin.
+ − 266 0x3: Capture on both edges of EVENT_CAPTURE pin.
+ − 267 */
+ − 268 class T_TCM : public TBitField<8, 2>
+ − 269 {
+ − 270 public :
+ − 271 enum TConstants
+ − 272 {
+ − 273 KNoCapture = TConstVal<0>::KValue,
+ − 274 KRisingEdge = TConstVal<1>::KValue,
+ − 275 KFallingEdge = TConstVal<2>::KValue,
+ − 276 KBothEdges = TConstVal<3>::KValue
+ − 277 } ;
+ − 278 } ;
+ − 279
+ − 280 /**
+ − 281 11:10 TRG Trigger output mode RW 0x0
+ − 282 0x0: No trigger
+ − 283 0x1: Overflow trigger
+ − 284 0x2: Overflow and match trigger
+ − 285 0x3: Reserved
+ − 286 */
+ − 287 class T_IDLEMODE : public TBitField<10, 2>
+ − 288 {
+ − 289 public :
+ − 290 enum TConstants
+ − 291 {
+ − 292 KNoTrigger = TConstVal<0>::KValue,
+ − 293 KOverflow = TConstVal<1>::KValue,
+ − 294 KOverflowAndMatch = TConstVal<2>::KValue
+ − 295 } ;
+ − 296 } ;
+ − 297
+ − 298 /**
+ − 299 12 PT Pulse or toggle select bit RW 0
+ − 300 0x0: Pulse modulation
+ − 301 0x1: Toggle modulation
+ − 302 */
+ − 303 typedef TSingleBitField<12> T_PT ;
+ − 304
+ − 305 /**
+ − 306 13 CAPT_MODE Capture mode select bit (first/second) RW 0
+ − 307 0x0: Capture the first enabled capture event in TCAR1.
+ − 308 0x1: Capture the second enabled capture event in TCAR2.
+ − 309 */
+ − 310 typedef TSingleBitField<13> T_CAPT_MODE ;
+ − 311
+ − 312 /**
+ − 313 14 GPO_CFG PWM output/event detection input pin direction control: RW 0
+ − 314 0x0: Configures the pin as an output (needed when PWM mode is required)
+ − 315 0x1: Configures the pin as an input (needed when capture mode is required)
+ − 316 */
+ − 317 typedef TSingleBitField<14> T_GPO_CFG ;
+ − 318
+ − 319 } ; // namespace TCLR
+ − 320
+ − 321 namespace TWPS
+ − 322 {
+ − 323 /**
+ − 324 0 W_PEND_TCLR Write pending for register GPT_TCLR R 0
+ − 325 0x0: Control register write not pending
+ − 326 0x1: Control register write pending
+ − 327 */
+ − 328 typedef TSingleBitField<0> T_W_PEND_TCLR ;
+ − 329
+ − 330 /**
+ − 331 1 W_PEND_TCRR Write pending for register GPT_TCRR R 0
+ − 332 0x0: Counter register write not pending
+ − 333 0x1: Counter register write pending
+ − 334 */
+ − 335 typedef TSingleBitField<1> T_W_PEND_TCRR ;
+ − 336
+ − 337 /**
+ − 338 2 W_PEND_TLDR Write pending for register GPT_TLDR R 0
+ − 339 0x0: Load register write not pending
+ − 340 0x1: Load register write pending
+ − 341 */
+ − 342 typedef TSingleBitField<2> T_W_PEND_TLDR ;
+ − 343
+ − 344 /**
+ − 345 3 W_PEND_TTGR Write pending for register GPT_TTGR R 0
+ − 346 0x0: Trigger register write not pending
+ − 347 0x1: Trigger register write pending
+ − 348 */
+ − 349 typedef TSingleBitField<3> T_W_PEND_TTGR ;
+ − 350
+ − 351 /**
+ − 352 4 W_PEND_TMAR Write pending for register GPT_TMAR R 0
+ − 353 0x0: Match register write not pending
+ − 354 0x1: Match register write pending
+ − 355 */
+ − 356 typedef TSingleBitField<4> T_W_PEND_TMAR;
+ − 357
+ − 358 /**
+ − 359 5 W_PEND_TPIR Write pending for register GPT_TPIR R 0
+ − 360 Reserved for instances 3, 4, 5, 6, 7, 8, 9, 11, 12 Read returns reset value. R 0
+ − 361 0x0: Positive increment register write not pending
+ − 362 0x1: Positive increment register write pending
+ − 363 */
+ − 364 typedef TSingleBitField<5> T_W_PEND_TPIR ;
+ − 365
+ − 366 /**
+ − 367 6 W_PEND_TNIR Write pending for register GPT_TNIR R 0
+ − 368 0x0: Negative increment register write not pending
+ − 369 0x1: Negative increment register write pending
+ − 370 Reserved for instances 3, 4, 5, 6, 7, 8, 9, 11, 12 Read returns reset value. R 0
+ − 371 */
+ − 372 typedef TSingleBitField<6> T_W_PEND_TNIR ;
+ − 373
+ − 374 /**
+ − 375 7 W_PEND_TCVR Write pending for register GPT_TCVR R 0
+ − 376 0x0: Counter value register write not pending
+ − 377 0x1: Counter value register write pending
+ − 378 Reserved for instances 3, 4, 5, 6, 7, 8, 9, 11, 12 Read returns reset value. R 0
+ − 379 */
+ − 380 typedef TSingleBitField<7> T_W_PEND_TCVR ;
+ − 381
+ − 382 /**
+ − 383 8 W_PEND_TOCR Write pending for register GPT_TOCR R 0
+ − 384 0x0: Overflow counter register write not pending
+ − 385 0x1: Overflow counter register write pending
+ − 386 Reserved for instances 3, 4, 5, 6, 7, 8, 9, 11, 12 Read returns reset value. R 0
+ − 387 */
+ − 388 typedef TSingleBitField<8> T_W_PEND_TOCR ;
+ − 389
+ − 390 /**
+ − 391 9 W_PEND_TOWR Write pending for register GPT_TOWR R 0
+ − 392 0x0: Overflow wrapping register write not pending
+ − 393 0x1: Overflow wrapping register write pending
+ − 394 Reserved for instances 3, 4, 5, 6, 7, 8, 9, 11, 12 Read returns reset value. R 0
+ − 395 */
+ − 396 typedef TSingleBitField<9> T_W_PEND_TOWR ;
+ − 397
+ − 398 } ; // namespace TWPS
+ − 399
+ − 400 namespace TSICR
+ − 401 {
+ − 402 /**
+ − 403 1 SFT Reset software functional registers. This bit is automatically reset RW 0
+ − 404 by the hardware. During reads, it always returns 0.
+ − 405 0x0: Normal functional mode
+ − 406 0x1: The functional registers are reset.
+ − 407 */
+ − 408 typedef TSingleBitField<1> T_SFT ;
+ − 409
+ − 410 /**
+ − 411 2 POSTED Posted mode selection RW 1
+ − 412 0x0: Non-posted mode selected
+ − 413 0x1: Posted mode selected
+ − 414 */
+ − 415 typedef TSingleBitField<2> T_POSTED ;
+ − 416
+ − 417 } ; // namespace TSICR
+ − 418
+ − 419 namespace TOCR
+ − 420 {
+ − 421 /**
+ − 422 23:0 OVF_COUNTER_VALUE The number of overflow events. RW 0x00000000
+ − 423 */
+ − 424 class T_OVF_COUNTER_VALUE : public TBitField<0, 24>
+ − 425 {
+ − 426 public :
+ − 427 enum TConstants
+ − 428 {
+ − 429 } ;
+ − 430 } ;
+ − 431
+ − 432 } ; // namespace TOCR
+ − 433
+ − 434 namespace TOWR
+ − 435 {
+ − 436 /**
+ − 437 23:0 OVF_WRAPPING_VALUE The number of masked interrupts. RW 0x00000000
+ − 438 */
+ − 439 class T_OVF_WRAPPING_VALUE : public TBitField<0, 24>
+ − 440 {
+ − 441 public :
+ − 442 enum TConstants
+ − 443 {
+ − 444 } ;
+ − 445 } ;
+ − 446
+ − 447 } ; // namespace TOWR
+ − 448
+ − 449 enum TBaseAddress
+ − 450 {
+ − 451 KGPTIMER1_Base = TVirtual<0x48318000>::Value,
+ − 452 KGPTIMER2_Base = TVirtual<0x49032000>::Value,
+ − 453 KGPTIMER3_Base = TVirtual<0x49034000>::Value,
+ − 454 KGPTIMER4_Base = TVirtual<0x49036000>::Value,
+ − 455 KGPTIMER5_Base = TVirtual<0x49038000>::Value,
+ − 456 KGPTIMER6_Base = TVirtual<0x4903A000>::Value,
+ − 457 KGPTIMER7_Base = TVirtual<0x4903C000>::Value,
+ − 458 KGPTIMER8_Base = TVirtual<0x4903E000>::Value,
+ − 459 KGPTIMER9_Base = TVirtual<0x49040000>::Value,
+ − 460 KGPTIMER10_Base = TVirtual<0x48086000>::Value,
+ − 461 KGPTIMER11_Base = TVirtual<0x48088000>::Value,
+ − 462 KGPTIMER12_Base = TVirtual<0x48304000>::Value,
+ − 463 } ;
+ − 464
+ − 465 enum TTimerNumber
+ − 466 {
+ − 467 EGpTimer1,
+ − 468 EGpTimer2,
+ − 469 EGpTimer3,
+ − 470 EGpTimer4,
+ − 471 EGpTimer5,
+ − 472 EGpTimer6,
+ − 473 EGpTimer7,
+ − 474 EGpTimer8,
+ − 475 EGpTimer9,
+ − 476 EGpTimer10,
+ − 477 EGpTimer11,
+ − 478 EGpTimer12
+ − 479 };
+ − 480
+ − 481 typedef void (*TTimerIsr)(TAny*) ;
+ − 482
+ − 483 template<const TTimerNumber tImEr>
+ − 484 struct TTimerTraits
+ − 485 {
+ − 486 } ;
+ − 487
+ − 488 template<>
+ − 489 struct TTimerTraits<EGpTimer1>
+ − 490 {
+ − 491 enum TraitValues
+ − 492 {
+ − 493 KBaseAddress = KGPTIMER1_Base,
+ − 494 KIrq = EOmap3530_IRQ37_GPT1_IRQ,
+ − 495 KClockSelMask = TSingleBitField<7>::KMask,
+ − 496 KClockSelValue = TSingleBitField<7>::KOn,
+ − 497 } ;
+ − 498 } ;
+ − 499
+ − 500 template<>
+ − 501 struct TTimerTraits<EGpTimer2>
+ − 502 {
+ − 503 enum TraitValues
+ − 504 {
+ − 505 KBaseAddress = KGPTIMER2_Base,
+ − 506 KIrq = EOmap3530_IRQ38_GPT2_IRQ,
+ − 507 } ;
+ − 508 } ;
+ − 509
+ − 510 template<>
+ − 511 struct TTimerTraits<EGpTimer3>
+ − 512 {
+ − 513 enum TraitValues
+ − 514 {
+ − 515 KBaseAddress = KGPTIMER3_Base,
+ − 516 KIrq = EOmap3530_IRQ39_GPT3_IRQ,
+ − 517 } ;
+ − 518 } ;
+ − 519
+ − 520 template<>
+ − 521 struct TTimerTraits<EGpTimer4>
+ − 522 {
+ − 523 enum TraitValues
+ − 524 {
+ − 525 KBaseAddress = KGPTIMER4_Base,
+ − 526 KIrq = EOmap3530_IRQ40_GPT4_IRQ,
+ − 527 } ;
+ − 528 } ;
+ − 529
+ − 530 template<>
+ − 531 struct TTimerTraits<EGpTimer5>
+ − 532 {
+ − 533 enum TraitValues
+ − 534 {
+ − 535 KBaseAddress = KGPTIMER5_Base,
+ − 536 KIrq = EOmap3530_IRQ41_GPT5_IRQ,
+ − 537 } ;
+ − 538 } ;
+ − 539
+ − 540 template<>
+ − 541 struct TTimerTraits<EGpTimer6>
+ − 542 {
+ − 543 enum TraitValues
+ − 544 {
+ − 545 KBaseAddress = KGPTIMER6_Base,
+ − 546 KIrq = EOmap3530_IRQ42_GPT6_IRQ,
+ − 547 } ;
+ − 548 } ;
+ − 549
+ − 550 template<>
+ − 551 struct TTimerTraits<EGpTimer7>
+ − 552 {
+ − 553 enum TraitValues
+ − 554 {
+ − 555 KBaseAddress = KGPTIMER7_Base,
+ − 556 KIrq = EOmap3530_IRQ43_GPT7_IRQ,
+ − 557 } ;
+ − 558 } ;
+ − 559
+ − 560 template<>
+ − 561 struct TTimerTraits<EGpTimer8>
+ − 562 {
+ − 563 enum TraitValues
+ − 564 {
+ − 565 KBaseAddress = KGPTIMER8_Base,
+ − 566 KIrq = EOmap3530_IRQ44_GPT8_IRQ,
+ − 567 } ;
+ − 568 } ;
+ − 569
+ − 570 template<>
+ − 571 struct TTimerTraits<EGpTimer9>
+ − 572 {
+ − 573 enum TraitValues
+ − 574 {
+ − 575 KBaseAddress = KGPTIMER9_Base,
+ − 576 KIrq = EOmap3530_IRQ45_GPT9_IRQ,
+ − 577 } ;
+ − 578 } ;
+ − 579
+ − 580 template<>
+ − 581 struct TTimerTraits<EGpTimer10>
+ − 582 {
+ − 583 enum TraitValues
+ − 584 {
+ − 585 KBaseAddress = KGPTIMER10_Base,
+ − 586 KIrq = EOmap3530_IRQ46_GPT10_IRQ,
+ − 587 } ;
+ − 588 } ;
+ − 589
+ − 590 template<>
+ − 591 struct TTimerTraits<EGpTimer11>
+ − 592 {
+ − 593 enum TraitValues
+ − 594 {
+ − 595 KBaseAddress = KGPTIMER11_Base,
+ − 596 KIrq = EOmap3530_IRQ47_GPT11_IRQ,
+ − 597 } ;
+ − 598 } ;
+ − 599
+ − 600 template<>
+ − 601 struct TTimerTraits<EGpTimer12>
+ − 602 {
+ − 603 enum TraitValues
+ − 604 {
+ − 605 KBaseAddress = KGPTIMER12_Base,
+ − 606 KIrq = EOmap3530_IRQ95_GPT12_IRQ,
+ − 607 KClockSelReg = 0,
+ − 608 KClockSelMask = 0,
+ − 609 KClockSel32K = 0,
+ − 610 KClockSelSys = 0,
+ − 611 KClockSelValue = KClockSel32K
+ − 612 } ;
+ − 613 } ;
+ − 614
+ − 615 /**
+ − 616 An interface template for OMAP3530 General Purpose timer functionality.
+ − 617 */
+ − 618 template <const TTimerNumber tImEr>
+ − 619 class TGPT
+ − 620 {
+ − 621 protected :
+ − 622 enum TRegisterOffsets
+ − 623 {
+ − 624 KTIOCP_CFG_Offset = 0x010,
+ − 625 KTISTAT_Offset = 0x014,
+ − 626 KTISR_Offset = 0x018,
+ − 627 KTIER_Offset = 0x01C,
+ − 628 KTWER_Offset = 0x020,
+ − 629 KTCLR_Offset = 0x024,
+ − 630 KTCRR_Offset = 0x028,
+ − 631 KTLDR_Offset = 0x02C,
+ − 632 KTTGR_Offset = 0x030,
+ − 633 KTWPS_Offset = 0x034,
+ − 634 KTMAR_Offset = 0x038,
+ − 635 KTCAR1_Offset = 0x03C,
+ − 636 KTSICR_Offset = 0x040,
+ − 637 KTCAR2_Offset = 0x044
+ − 638 } ;
+ − 639 enum TConstants
+ − 640 {
+ − 641 KHz = 1000,
+ − 642 KClockInputFrequency = 32768,
+ − 643 } ;
+ − 644
+ − 645 public :
+ − 646 static inline TOmap3530_IRQ Irq()
+ − 647 {
+ − 648 return TOmap3530_IRQ(TTimerTraits<tImEr>::KIrq) ;
+ − 649 }
+ − 650 static inline TBool CanWriteTCLR()
+ − 651 {
+ − 652 return (0 == (iTWPS.Read() & TWPS::T_W_PEND_TCLR::KOn)) ;
+ − 653 }
+ − 654 static inline TBool CanWriteTCRR()
+ − 655 {
+ − 656 return (0 == (iTWPS.Read() & TWPS::T_W_PEND_TCRR::KOn)) ;
+ − 657 }
+ − 658 static inline TBool CanWriteTLDR()
+ − 659 {
+ − 660 return (0 == (iTWPS.Read() & TWPS::T_W_PEND_TLDR::KOn)) ;
+ − 661 }
+ − 662 static inline TBool CanWriteTTGR()
+ − 663 {
+ − 664 return (0 == (iTWPS.Read() & TWPS::T_W_PEND_TTGR::KOn)) ;
+ − 665 }
+ − 666 static inline TBool CanWriteTMAR()
+ − 667 {
+ − 668 return (0 == (iTWPS.Read() & TWPS::T_W_PEND_TMAR::KOn)) ;
+ − 669 }
+ − 670 static inline void Reset()
+ − 671 {
+ − 672 iTIOCP_CFG.Write(TIOCP_CFG::T_SOFTRESET::KOn) ;
+ − 673 }
+ − 674 static inline TBool ResetComplete()
+ − 675 {
+ − 676 return (TISTAT::T_RESETDONE::KOn & iTISTAT.Read()) ;
+ − 677 }
+ − 678 static inline TBool WriteOutstanding()
+ − 679 {
+ − 680 return (iTWPS.Read()) ;
+ − 681 }
+ − 682
+ − 683 public :
+ − 684 static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTIOCP_CFG_Offset)> iTIOCP_CFG ;
+ − 685 static TReg32_R<(TTimerTraits<tImEr>::KBaseAddress + KTISTAT_Offset)> iTISTAT ;
+ − 686 static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTISR_Offset)> iTISR ;
+ − 687 static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTIER_Offset)> iTIER ;
+ − 688 static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTWER_Offset)> iTWER ;
+ − 689 static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTCLR_Offset)> iTCLR ;
+ − 690 static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTCRR_Offset)> iTCRR ;
+ − 691 static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTLDR_Offset)> iTLDR ;
+ − 692 static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTTGR_Offset)> iTTGR ;
+ − 693 static TReg32_R<(TTimerTraits<tImEr>::KBaseAddress + KTWPS_Offset)> iTWPS ;
+ − 694 static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTMAR_Offset)> iTMAR ;
+ − 695 static TReg32_R<(TTimerTraits<tImEr>::KBaseAddress + KTCAR1_Offset)> iTCAR1 ;
+ − 696 static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTSICR_Offset)> iTSICR ;
+ − 697 static TReg32_R<(TTimerTraits<tImEr>::KBaseAddress + KTCAR2_Offset)> iTCAR2 ;
+ − 698 } ; // class TGPTi
+ − 699
+ − 700 /**
+ − 701
+ − 702 An interface template for OMAP3530 Microsecond aligned timer functionality.
+ − 703 Encapsulates the extra registers provided for timers 1, 2 and 10.
+ − 704 */
+ − 705 template <const TTimerNumber tImEr>
+ − 706 class TMsSyncTimer : public TGPT<tImEr>
+ − 707 {
+ − 708 using TGPT<tImEr>::iTWPS ;
+ − 709 using TGPT<tImEr>::iTLDR ;
+ − 710
+ − 711 protected :
+ − 712 enum TRegisterOffsets
+ − 713 {
+ − 714 KTPIR_Offset = 0x048,
+ − 715 KTNIR_Offset = 0x04C,
+ − 716 KTCVR_Offset = 0x050,
+ − 717 KTOCR_Offset = 0x054,
+ − 718 KTOWR_Offset = 0x058
+ − 719 } ;
+ − 720
+ − 721 public :
+ − 722 enum TRegisterValues
+ − 723 {
+ − 724 KInitialLoad = 0xFFFFFFE0,
+ − 725 KInitialPIR = 0x38A40,
+ − 726 KInitialNIR = 0xFFF44800
+ − 727 } ;
+ − 728
+ − 729 static inline TBool CanWriteTPIR()
+ − 730 {
+ − 731 return (0 == (iTWPS.Read() & TWPS::T_W_PEND_TPIR::KOn)) ;
+ − 732 }
+ − 733 static inline TBool CanWriteTNIR()
+ − 734 {
+ − 735 return (0 == (iTWPS.Read() & TWPS::T_W_PEND_TNIR::KOn)) ;
+ − 736 }
+ − 737 static inline TBool CanWriteTCVR()
+ − 738 {
+ − 739 return (0 == (iTWPS.Read() & TWPS::T_W_PEND_TCVR::KOn)) ;
+ − 740 }
+ − 741 static inline TBool CanWriteTOCR()
+ − 742 {
+ − 743 return (0 == (iTWPS.Read() & TWPS::T_W_PEND_TOCR::KOn)) ;
+ − 744 }
+ − 745 static inline TBool CanWriteTOWR()
+ − 746 {
+ − 747 return (0 == (iTWPS.Read() & TWPS::T_W_PEND_TOWR::KOn)) ;
+ − 748 }
+ − 749
+ − 750 static inline void ConfigureFor1Ms()
+ − 751 {
+ − 752 iTLDR.Write( KInitialLoad );
+ − 753 iTPIR.Write( KInitialPIR );
+ − 754 iTNIR.Write( KInitialNIR );
+ − 755 }
+ − 756
+ − 757 public :
+ − 758 static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTPIR_Offset)> iTPIR ;
+ − 759 static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTNIR_Offset)> iTNIR ;
+ − 760 static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTCVR_Offset)> iTCVR ;
+ − 761 static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTOCR_Offset)> iTOCR ;
+ − 762 static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTOWR_Offset)> iTOWR ;
+ − 763 } ; // class TMsSyncTimer
+ − 764
+ − 765
+ − 766 } // namespage GPTimer
+ − 767
+ − 768 typedef GPTimer::TMsSyncTimer<GPTimer::EGpTimer1> TGpTimer1 ;
+ − 769 typedef GPTimer::TMsSyncTimer<GPTimer::EGpTimer2> TGpTimer2 ;
+ − 770 typedef GPTimer::TGPT<GPTimer::EGpTimer3> TGpTimer3 ;
+ − 771 typedef GPTimer::TGPT<GPTimer::EGpTimer4> TGpTimer4 ;
+ − 772 typedef GPTimer::TGPT<GPTimer::EGpTimer5> TGpTimer5 ;
+ − 773 typedef GPTimer::TGPT<GPTimer::EGpTimer6> TGpTimer6 ;
+ − 774 typedef GPTimer::TGPT<GPTimer::EGpTimer7> TGpTimer7 ;
+ − 775 typedef GPTimer::TGPT<GPTimer::EGpTimer8> TGpTimer8 ;
+ − 776 typedef GPTimer::TGPT<GPTimer::EGpTimer9> TGpTimer9 ;
+ − 777 typedef GPTimer::TMsSyncTimer<GPTimer::EGpTimer10> TGpTimer10 ;
+ − 778 typedef GPTimer::TGPT<GPTimer::EGpTimer11> TGpTimer11 ;
+ − 779 typedef GPTimer::TGPT<GPTimer::EGpTimer12> TGpTimer12 ;
+ − 780
+ − 781
+ − 782 /**
+ − 783 An interface template for OMAP3530 32-KHz aligned timer functionality.
+ − 784 */
+ − 785 class T32KhzSyncTimer
+ − 786 {
+ − 787 protected :
+ − 788 enum TRegisterAddress
+ − 789 {
+ − 790 KREG_32KSYNCNT_SYSCONFIG = TVirtual<0x48320004>::Value,
+ − 791 KREG_32KSYNCNT_CR = TVirtual<0x48320010>::Value
+ − 792 } ;
+ − 793
+ − 794 public :
+ − 795 static TReg32_RW<KREG_32KSYNCNT_SYSCONFIG> iSysConfig ;
+ − 796 static TReg32_R<KREG_32KSYNCNT_CR> iCR ;
+ − 797
+ − 798 private :
+ − 799 } ; // class TMsSyncTimer
+ − 800
+ − 801 } // namespace Omap3530
+ − 802
+ − 803 } // namespace TexasInstruments
+ − 804
+ − 805
+ − 806 // **** TEST CODE ****
+ − 807 //# define HEADER_OMAP3530_TIMER_H_DO_COMPILE_TIME_CHECK_TESTS 1
+ − 808 # ifdef HEADER_OMAP3530_TIMER_H_DO_COMPILE_TIME_CHECK_TESTS
+ − 809 inline void CompileTimeChecks(void)
+ − 810 {
+ − 811 __ASSERT_COMPILE((TI::Omap3530::GPTimer::TIOCP_CFG::T_IDLEMODE::KSmartIdle == (2 << 3))) ;
+ − 812 __ASSERT_COMPILE((TI::Omap3530::GPTimer::TIOCP_CFG::T_CLOCKACTIVITY::KMaintainIfClock == (1 << 8))) ;
+ − 813 __ASSERT_COMPILE((TI::Omap3530::GPTimer::KGPTIMER1_Base == (0xC6318000))) ;
+ − 814 __ASSERT_COMPILE((0)) ; // Prove that testing is happening
+ − 815 }
+ − 816 # endif
+ − 817 #endif /* ndef HEADER_OMAP3530_TIMER_H_INCLUDED */