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// Copyright (c) 1994-2009 Nokia Corporation and/or its subsidiary(-ies).
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// All rights reserved.
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// This component and the accompanying materials are made available
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// under the terms of the License "Eclipse Public License v1.0"
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// which accompanies this distribution, and is available
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// at the URL "http://www.eclipse.org/legal/epl-v10.html".
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//
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// Initial Contributors:
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// Nokia Corporation - initial contribution.
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//
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// Contributors:
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//
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// Description:
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// omap3530/omap3530_drivers/gpio/gpio.cpp
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//
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#include <kern_priv.h>
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#include <assp/omap3530_assp/omap3530_gpio.h>
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#include <assp/omap3530_assp/omap3530_hardware_base.h>
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#include <assp/omap3530_assp/omap3530_irqmap.h>
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#include <assp.h>
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//#include <nkern.h>
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#include <assp/omap3530_assp/gpio.h>
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GLREF_C TInt InitGpioInterrupts();
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TSpinLock GPIOModeLock(/*TSpinLock::EOrderNone*/);
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TSpinLock GPIOWakeLock(/*TSpinLock::EOrderNone*/);
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TSpinLock GPIOLevelLock(/*TSpinLock::EOrderNone*/);
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GPIO::TGpioMode ThePinMode[ KHwGpioPinMax ];
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TUint32 ThePinIsEnabled[ KHwGpioBanks ];
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__ASSERT_COMPILE( KHwGpioPinsPerBank <= 32 );
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#if 0
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static void dumpGpioBank(TUint aBankAddr)
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{
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Kern::Printf("GPIO_SYSCONFIG at %x is %x",aBankAddr +KGPIO_SYSCONFIG,AsspRegister::Read32(aBankAddr +KGPIO_SYSCONFIG) );
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Kern::Printf("GPIO_SYSSTATUS at %x is %x",aBankAddr +KGPIO_SYSSTATUS,AsspRegister::Read32(aBankAddr +KGPIO_SYSSTATUS));
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Kern::Printf("GPIO_IRQSTATUS1 at %x is %x",aBankAddr +KGPIO_IRQSTATUS1,AsspRegister::Read32(aBankAddr +KGPIO_IRQSTATUS1) );
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Kern::Printf("GPIO_IRQENABLE1 at %x is %x",aBankAddr +KGPIO_IRQENABLE1,AsspRegister::Read32(aBankAddr +KGPIO_IRQENABLE1) );
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Kern::Printf("GPIO_WAKEUPENABLE at %x is %x",aBankAddr +KGPIO_WAKEUPENABLE,AsspRegister::Read32(aBankAddr +KGPIO_WAKEUPENABLE) );
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Kern::Printf("GPIO_CTRL at %x is %x",aBankAddr +KGPIO_CTRL,AsspRegister::Read32(aBankAddr +KGPIO_CTRL) );
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Kern::Printf("GPIO_OE at %x is %x",aBankAddr +KGPIO_CTRL,AsspRegister::Read32(aBankAddr +KGPIO_OE) );
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}
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#endif
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EXPORT_C TInt GPIO::SetPinMode(TInt aId, TGpioMode aMode)
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{
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TInt irq = __SPIN_LOCK_IRQSAVE(GPIOModeLock);
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if(ThePinMode[ aId ] != aMode)
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{
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ThePinMode[ aId ] = aMode;
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TUint bank = GPIO_PIN_BANK( aId );
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TUint pinMask = 1 << GPIO_PIN_OFFSET( aId );
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if( aMode == GPIO::EEnabled)
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{
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if( 0 == ThePinIsEnabled[ bank ] )
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{
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// First enabled pin in bank
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AsspRegister::Modify32(GPIO_BASE_ADDRESS( aId ) +KGPIO_CTRL,KClearNone,0x1);
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}
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ThePinIsEnabled[ bank ] |= pinMask;
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}
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else
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{
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ThePinIsEnabled[ bank ] &= ~pinMask;
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if( 0 == ThePinIsEnabled[ bank ] )
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{
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// Bank can be disabled
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AsspRegister::Modify32(GPIO_BASE_ADDRESS( aId ) +KGPIO_CTRL,0x1, KSetNone);
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}
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}
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}
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__SPIN_UNLOCK_IRQRESTORE(GPIOModeLock,irq);
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return KErrNone;
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}
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EXPORT_C TInt GPIO::GetPinMode(TInt aId, TGpioMode & aMode)
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{
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aMode = ThePinMode[ aId ];
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return KErrNone;
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}
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EXPORT_C TInt GPIO::SetPinDirection(TInt aId, TGpioDirection aDirection)
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{
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__ASSERT_ALWAYS(GPIO_PIN_BOUNDS(aId),Kern::Fault(" GPIO::SetPinBias OOB ",KErrArgument));
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if (aDirection == ETriStated)
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{
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return KErrNotSupported;
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}
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if (aDirection == EInput)
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{
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AsspRegister::Modify32(GPIO_BASE_ADDRESS(aId)+KGPIO_OE, KClearNone, GPIO_PIN_OFFSET(aId));
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}
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else
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{
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AsspRegister::Modify32(GPIO_BASE_ADDRESS(aId)+KGPIO_OE, GPIO_PIN_OFFSET(aId), KSetNone);
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}
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return KErrNone;
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}
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EXPORT_C TInt GPIO::GetPinDirection(TInt aId, TGpioDirection& aDirection)
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{
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__ASSERT_ALWAYS(GPIO_PIN_BOUNDS(aId),Kern::Fault(" GPIO::GetPinDirection OOB ",KErrArgument));
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if(AsspRegister::Read32(GPIO_BASE_ADDRESS(aId)+KGPIO_OE) & GPIO_PIN_OFFSET(aId))
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aDirection=EInput;
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else
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aDirection=EOutput;
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return KErrNone;
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}
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EXPORT_C TInt GPIO::SetPinBias(TInt aId, TGpioBias aBias)
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{
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__ASSERT_ALWAYS(GPIO_PIN_BOUNDS(aId),Kern::Fault(" GPIO::SetPinBias OOB ",KErrArgument));
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return KErrNotSupported;
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}
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EXPORT_C TInt GPIO::GetPinBias(TInt aId, TGpioBias& aBias)
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{
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__ASSERT_ALWAYS(GPIO_PIN_BOUNDS(aId),Kern::Fault(" GPIO::GetPinBias OOB ",KErrArgument));
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return KErrNotSupported;
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}
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EXPORT_C TInt GPIO::SetPinIdleConfigurationAndState(TInt aId, TInt /*aConf*/)
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{
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__ASSERT_ALWAYS(GPIO_PIN_BOUNDS(aId),Kern::Fault(" GPIO::SetPinIdleConfigurationAndState OOB ",KErrArgument));
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return KErrNotSupported;
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}
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EXPORT_C TInt GPIO::GetPinIdleConfigurationAndState(TInt aId, TInt& aBias)
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{
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__ASSERT_ALWAYS(GPIO_PIN_BOUNDS(aId),Kern::Fault(" GPIO::GetPinIdleConfigurationAndState OOB ",KErrArgument));
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return KErrNotSupported;
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}
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EXPORT_C TInt GPIO::BindInterrupt(TInt aId, TGpioIsr aIsr, TAny* aPtr)
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{
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return Interrupt::Bind( EGPIOIRQ_FIRST + aId,aIsr,aPtr);
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}
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EXPORT_C TInt GPIO::UnbindInterrupt(TInt aId)
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{
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return Interrupt::Unbind( EGPIOIRQ_FIRST + aId );
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}
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EXPORT_C TInt GPIO::EnableInterrupt(TInt aId)
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{
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return Interrupt::Enable( EGPIOIRQ_FIRST + aId );
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}
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EXPORT_C TInt GPIO::DisableInterrupt(TInt aId)
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{
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return Interrupt::Disable( EGPIOIRQ_FIRST + aId );
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}
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EXPORT_C TInt GPIO::ClearInterrupt(TInt aId)
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{
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return Interrupt::Clear( EGPIOIRQ_FIRST + aId );
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}
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EXPORT_C TInt GPIO::IsInterruptEnabled(TInt aId, TBool& aEnable)
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{
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aEnable = AsspRegister::Read32(GPIO_BASE_ADDRESS( aId ) + KGPIO_IRQENABLE1) & GPIO_PIN_OFFSET(aId);
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return KErrNone;
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}
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EXPORT_C TInt GPIO::GetMaskedInterruptState(TInt aId, TBool& aActive)
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{
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__ASSERT_ALWAYS(GPIO_PIN_BOUNDS(aId),Kern::Fault(" GPIO::GetMaskedInterruptState OOB ",KErrArgument));
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aActive = AsspRegister::Read32(GPIO_BASE_ADDRESS(aId)+KGPIO_IRQSTATUS1) & GPIO_PIN_OFFSET(aId);
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return KErrNone;
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}
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EXPORT_C TInt GPIO::GetRawInterruptState(TInt aId, TBool& aActive)
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{
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__ASSERT_ALWAYS(GPIO_PIN_BOUNDS(aId),Kern::Fault(" GPIO::GetRawInterruptState OOB ",KErrArgument));
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aActive = AsspRegister::Read32(GPIO_BASE_ADDRESS(aId)+KGPIO_IRQSTATUS1) & GPIO_PIN_OFFSET(aId);
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return KErrNone;
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}
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EXPORT_C TInt GPIO::SetInterruptTrigger(TInt aId, TGpioDetectionTrigger aTrigger)
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{
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__ASSERT_ALWAYS(GPIO_PIN_BOUNDS(aId),Kern::Fault(" GPIO::SetInterruptTrigger OOB ",KErrArgument));
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TInt baseAddr = GPIO_BASE_ADDRESS(aId);
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TUint irqFlags=0;
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//first we clear the current trigger(s)
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//then set the new for each case
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switch (aTrigger)
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{
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case ELevelLow:
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irqFlags = NKern::DisableAllInterrupts();//__SPIN_LOCK_IRQSAVE_W(GPIOLevelSpinLock);
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AsspRegister::Modify32(baseAddr+KGPIO_LEVELDETECT1, GPIO_PIN_OFFSET(aId),KSetNone);
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AsspRegister::Modify32(baseAddr+KGPIO_FALLINGDETECT, GPIO_PIN_OFFSET(aId),KSetNone);
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AsspRegister::Modify32(baseAddr+KGPIO_RISINGDETECT, GPIO_PIN_OFFSET(aId),KSetNone);
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AsspRegister::Modify32(baseAddr+KGPIO_LEVELDETECT0, KClearNone, GPIO_PIN_OFFSET(aId));
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NKern::RestoreInterrupts(irqFlags);//__SPIN_UNLOCK_IRQRESTORE_W(GPIOLevelSpinLock,irqFlags);
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break;
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case ELevelHigh:
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irqFlags = NKern::DisableAllInterrupts();//__SPIN_LOCK_IRQSAVE_W(GPIOLevelSpinLock);
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AsspRegister::Modify32(baseAddr+KGPIO_LEVELDETECT0, GPIO_PIN_OFFSET(aId),KSetNone);
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AsspRegister::Modify32(baseAddr+KGPIO_FALLINGDETECT, GPIO_PIN_OFFSET(aId),KSetNone);
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AsspRegister::Modify32(baseAddr+KGPIO_RISINGDETECT, GPIO_PIN_OFFSET(aId),KSetNone);
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AsspRegister::Modify32(baseAddr+KGPIO_LEVELDETECT1, KClearNone, GPIO_PIN_OFFSET(aId));
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NKern::RestoreInterrupts(irqFlags);//__SPIN_UNLOCK_IRQRESTORE_W(GPIOLevelSpinLock,irqFlags);
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break;
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case EEdgeFalling:
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irqFlags = NKern::DisableAllInterrupts();//__SPIN_LOCK_IRQSAVE_W(GPIOLevelSpinLock);
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AsspRegister::Modify32(baseAddr+KGPIO_LEVELDETECT0, GPIO_PIN_OFFSET(aId),KSetNone);
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AsspRegister::Modify32(baseAddr+KGPIO_LEVELDETECT1, GPIO_PIN_OFFSET(aId),KSetNone);
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AsspRegister::Modify32(baseAddr+KGPIO_RISINGDETECT, GPIO_PIN_OFFSET(aId),KSetNone);
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AsspRegister::Modify32(baseAddr+KGPIO_FALLINGDETECT, KClearNone, GPIO_PIN_OFFSET(aId));
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NKern::RestoreInterrupts(irqFlags);//__SPIN_UNLOCK_IRQRESTORE_W(GPIOLevelSpinLock,irqFlags);
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break;
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case EEdgeRising:
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irqFlags = NKern::DisableAllInterrupts();//__SPIN_LOCK_IRQSAVE_W(GPIOLevelSpinLock);
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AsspRegister::Modify32(baseAddr+KGPIO_LEVELDETECT0, GPIO_PIN_OFFSET(aId),KSetNone);
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AsspRegister::Modify32(baseAddr+KGPIO_LEVELDETECT1, GPIO_PIN_OFFSET(aId),KSetNone);
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AsspRegister::Modify32(baseAddr+KGPIO_FALLINGDETECT, GPIO_PIN_OFFSET(aId),KSetNone);
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AsspRegister::Modify32(baseAddr+KGPIO_RISINGDETECT, KClearNone, GPIO_PIN_OFFSET(aId));
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NKern::RestoreInterrupts(irqFlags);//__SPIN_UNLOCK_IRQRESTORE_W(GPIOLevelSpinLock,irqFlags);
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break;
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case EEdgeBoth:
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irqFlags = NKern::DisableAllInterrupts();//__SPIN_LOCK_IRQSAVE_W(GPIOLevelSpinLock);
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AsspRegister::Modify32(baseAddr+KGPIO_LEVELDETECT0, GPIO_PIN_OFFSET(aId),KSetNone);
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AsspRegister::Modify32(baseAddr+KGPIO_LEVELDETECT1, GPIO_PIN_OFFSET(aId),KSetNone);
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AsspRegister::Modify32(baseAddr+KGPIO_FALLINGDETECT, KClearNone, GPIO_PIN_OFFSET(aId));
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AsspRegister::Modify32(baseAddr+KGPIO_RISINGDETECT, KClearNone, GPIO_PIN_OFFSET(aId));
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NKern::RestoreInterrupts(irqFlags);//__SPIN_UNLOCK_IRQRESTORE_W(GPIOLevelSpinLock,irqFlags);
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break;
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default:
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return KErrArgument;
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}
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return KErrNone;
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}
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EXPORT_C TInt GPIO::EnableWakeup(TInt aId)
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{
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__ASSERT_ALWAYS(GPIO_PIN_BOUNDS(aId),Kern::Fault(" GPIO::EnableWakeup OOB ",KErrArgument));
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TInt baseAddr = GPIO_BASE_ADDRESS(aId);
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TInt irq = __SPIN_LOCK_IRQSAVE(GPIOWakeLock);
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AsspRegister::Modify32(baseAddr+KGPIO_SYSCONFIG,KClearNone, 1 << 2 );
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AsspRegister::Modify32(baseAddr+KGPIO_SETWKUENA,KClearNone ,GPIO_PIN_OFFSET(aId));
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__SPIN_UNLOCK_IRQRESTORE(GPIOWakeLock,irq);
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return KErrNone;
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}
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EXPORT_C TInt GPIO::DisableWakeup(TInt aId)
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{
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__ASSERT_ALWAYS(GPIO_PIN_BOUNDS(aId),Kern::Fault(" GPIO::DisableWakeup OOB ",KErrArgument));
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TInt baseAddr = GPIO_BASE_ADDRESS(aId);
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TInt irq = __SPIN_LOCK_IRQSAVE(GPIOWakeLock);
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AsspRegister::Modify32(baseAddr+KGPIO_SYSCONFIG,1 << 2 ,KSetNone);
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AsspRegister::Modify32(baseAddr+KGPIO_CLEARWKUENA,KClearNone,GPIO_PIN_OFFSET(aId));
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__SPIN_UNLOCK_IRQRESTORE(GPIOWakeLock,irq);
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return KErrNone;
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}
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EXPORT_C TInt GPIO::IsWakeupEnabled(TInt aId, TBool& aEnable)
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{
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__ASSERT_ALWAYS(GPIO_PIN_BOUNDS(aId),Kern::Fault(" GPIO::IsWakeupEnabled OOB ",KErrArgument));
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aEnable = AsspRegister::Read32(GPIO_BASE_ADDRESS(aId)+KGPIO_WAKEUPENABLE) & GPIO_PIN_OFFSET(aId);
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return KErrNone;
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}
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EXPORT_C TInt GPIO::SetWakeupTrigger(TInt aId, TGpioDetectionTrigger aTrigger)
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{
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__ASSERT_ALWAYS(GPIO_PIN_BOUNDS(aId),Kern::Fault(" GPIO::SetWakeupTrigger OOB ",KErrArgument));
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return KErrNotSupported;
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}
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// WARNING: Changing debouncing time will change it for all pins in the bank
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EXPORT_C TInt GPIO::SetDebounceTime(TInt aId, TInt aTime)
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{
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TGpioDirection direction;
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GetPinDirection(aId, direction);
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if(direction==EOutput)
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{
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// The pin must be configured as input.
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return KErrNotSupported;
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}
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//convert the Ms input time into units of 31us
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TInt timeSteps = aTime / 31;
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if(timeSteps>127)
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{
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#ifdef _DEBUG
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Kern::Printf("Warning: Tried to set the GPIO debounce time to %dus, \
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which is greater than the maximum supported 3937us.", aTime);
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#endif
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timeSteps=127; // The maximum debounce value.
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}
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TInt baseAddr = GPIO_BASE_ADDRESS(aId);
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TUint irqFlags = __SPIN_LOCK_IRQSAVE(gpio::GPIODebounceSpinLock);
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AsspRegister::Write32(baseAddr+KGPIO_DEBOUNCINGTIME, timeSteps & KGPIO_DEBOUNCE_TIME_MASK);
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AsspRegister::Modify32(baseAddr+KGPIO_DEBOUNCENABLE, KClearNone, GPIO_PIN_OFFSET(aId));
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__SPIN_UNLOCK_IRQRESTORE(gpio::GPIODebounceSpinLock,irqFlags);
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return KErrNone;
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}
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EXPORT_C TInt GPIO::GetDebounceTime(TInt aId, TInt& aTime)
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{
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__ASSERT_ALWAYS(GPIO_PIN_BOUNDS(aId),Kern::Fault(" GPIO::GetDebounceTime OOB ",KErrArgument));
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aTime=AsspRegister::Read32(GPIO_BASE_ADDRESS(aId)+KGPIO_DEBOUNCINGTIME); // The time in in multiples of 31 microseconds. We should probably use a nicer unit..
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return KErrNone;
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}
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347 |
EXPORT_C TInt GPIO::SetOutputState(TInt aId, TGpioState aState)
|
|
348 |
{
|
|
349 |
if(aState==GPIO::ELow)
|
|
350 |
{
|
|
351 |
AsspRegister::Modify32(GPIO_BASE_ADDRESS(aId) + KGPIO_DATAOUT, GPIO_PIN_OFFSET(aId), KSetNone);
|
|
352 |
}
|
|
353 |
else
|
|
354 |
{
|
|
355 |
AsspRegister::Modify32(GPIO_BASE_ADDRESS(aId) + KGPIO_DATAOUT, KClearNone, GPIO_PIN_OFFSET(aId));
|
|
356 |
}
|
|
357 |
return KErrNone;
|
|
358 |
}
|
|
359 |
|
|
360 |
EXPORT_C TInt GPIO::GetInputState(TInt aId, TGpioState& aState)
|
|
361 |
{
|
|
362 |
__ASSERT_ALWAYS(GPIO_PIN_BOUNDS(aId),Kern::Fault(" GPIO::GetInputState OOB ",KErrArgument));
|
|
363 |
|
|
364 |
aState= ( AsspRegister::Read32(GPIO_BASE_ADDRESS(aId) + KGPIO_DATAIN) & GPIO_PIN_OFFSET(aId) ?
|
|
365 |
GPIO::EHigh:
|
|
366 |
GPIO::ELow);
|
|
367 |
|
|
368 |
return KErrNone;
|
|
369 |
}
|
|
370 |
|
|
371 |
EXPORT_C TInt GPIO::GetOutputState(TInt aId, TGpioState& aState)
|
|
372 |
{
|
|
373 |
__ASSERT_ALWAYS(GPIO_PIN_BOUNDS(aId),Kern::Fault(" GPIO::GetOutputState OOB ",KErrArgument));
|
|
374 |
|
|
375 |
aState = (AsspRegister::Read32(GPIO_BASE_ADDRESS(aId)+KGPIO_DATAOUT)& GPIO_PIN_OFFSET(aId) ?
|
|
376 |
aState=GPIO::EHigh:
|
|
377 |
aState=GPIO::ELow);
|
|
378 |
return KErrNone;
|
|
379 |
}
|
|
380 |
|
|
381 |
EXPORT_C TInt GPIO::GetInputState(TInt aId, TGpioCallback* /*aCb*/)
|
|
382 |
{
|
|
383 |
return KErrNotSupported;
|
|
384 |
}
|
|
385 |
|
|
386 |
EXPORT_C TInt GPIO::SetOutputState(TInt aId, TGpioState aState, TGpioCallback* /*aCb*/)
|
|
387 |
{
|
|
388 |
return KErrNotSupported;
|
|
389 |
}
|
|
390 |
|
|
391 |
|
|
392 |
DECLARE_STANDARD_EXTENSION()
|
|
393 |
{
|
|
394 |
|
|
395 |
TInt i=0;
|
|
396 |
for(;i<KHwGpioBanks;i++)
|
|
397 |
{
|
|
398 |
//spins here
|
|
399 |
AsspRegister::Write32(GPIO_BASE_ADDRESS(i*KHwGpioPinsPerBank)+KGPIO_SYSCONFIG,0x01 | 1 <<2);
|
|
400 |
AsspRegister::Write32(GPIO_BASE_ADDRESS(i*KHwGpioPinsPerBank)+KGPIO_CTRL,0x00);
|
|
401 |
ThePinIsEnabled[i]=0;
|
|
402 |
}
|
|
403 |
|
|
404 |
for(i=0; i<KHwGpioPinMax; i++)
|
|
405 |
{
|
|
406 |
//ThePinMode[ i ]=GPIO::EIdle;
|
|
407 |
}
|
|
408 |
return InitGpioInterrupts();
|
|
409 |
}
|