// Copyright (c) 1994-2009 Nokia Corporation and/or its subsidiary(-ies).

// All rights reserved.

// This component and the accompanying materials are made available

// under the terms of the License "Eclipse Public License v1.0"

// which accompanies this distribution, and is available

// at the URL "http://www.eclipse.org/legal/epl-v10.html".

//

// Initial Contributors:

// Nokia Corporation - initial contribution.

//

// Contributors:

//

// Description:

// omap3530/beagle_drivers/wb/cyashalbeagleboard_spi.cpp

//

#include <kern_priv.h>

#include <beagle/beagle_gpio.h>

#include <beagle/variant.h>

#include <assp/omap3530_assp/omap3530_assp_priv.h>

#include <assp/omap3530_assp/omap3530_irqmap.h> // GPIO interrupts

#include <assp/omap3530_assp/omap3530_gpio.h>

#include <assp.h> // Required for definition of TIsr

#include <cyasregs.h> // Astoria register definitions

#ifdef __CY_ASTORIA_BEAGLEBOARD_SPI__HAL__

#include "cyashalbeagleboard_spi.h"

#include "cyaserr.h"

#include "cyasregs.h"

#include "cyasdma.h"

#include "cyasintr.h"

#ifdef FIRMWARE_NOPPORT

#ifdef OVERCLOCK_SD

#include "cyastfw_sd_mmc_rel_nopport_Ast121_68.h"

#else

#include "cyastfw_sd_mmc_rel_nopport.h"

#endif

#else

#ifdef OVERCLOCK_SD

#include "cyastfw_sd_mmc_rel_silicon_Ast121_68.h"

#else

#include "cyastfw_sd_mmc_rel_silicon.h"

#endif

#endif

#include "cyasusbinit.h"

/*

 * For performance reasons, we handle storage endpoint transfers upto 4 KB

 * within the HAL itself.

 */

#define CYASSTORAGE_WRITE_EP_NUM	(4)

#define CYASSTORAGE_READ_EP_NUM		(8)

#define CYASSTORAGE_MAX_XFER_SIZE	(2*32768)

/*#define MONITOR_THREAD 1*/

#define INT_DE 1

/* DFC queue */

TDfc* gpDfc;

/*

 * The type of DMA operation, per endpoint

 */

typedef enum CyAsHalDmaType

{

    CyAsHalRead,

    CyAsHalWrite,

    CyAsHalNone

} CyAsHalDmaType ;

typedef struct CyAsHalEndpointDma

{

    CyBool buffer_valid ;

    uint16_t *data_p ;

    uint32_t size ;

    /*struct scatterlist* sg_p ;

    uint16_t scatter_index ;*/

    uint32_t bytes_xfered ;

    uint16_t transfer_cnt ;

    CyAsHalDmaType type ;

    CyBool pending ;

} CyAsHalEndpointDma ;

/*

 * The list of OMAP devices (should be one)

 */

static CyAsOmapDevKernel *m_omap_list_p = 0 ;

/*

 * The callback to call after DMA operations are complete

 */

static CyAsHalDmaCompleteCallback callback = 0 ;

/*

 * Pending data size for the endpoints

 */

static CyAsHalEndpointDma EndPoints[16] ;

/* Forward declaration */

static void CyHandleDRQInterrupt(CyAsOmapDevKernel *dev_p) ;

static volatile uint32_t Intr_Disabled = 0 ;

static volatile CyAsHalDeviceTag gDevTag = 0 ;

#define CYAS_INT_MASK (CY_AS_MEM_P0_INTR_REG_MCUINT | CY_AS_MEM_P0_INTR_REG_MBINT | \

                       CY_AS_MEM_P0_INTR_REG_PMINT | CY_AS_MEM_P0_INTR_REG_PLLLOCKINT)

#define CYAS_DRQ_MASK (CY_AS_MEM_P0_INTR_REG_DRQINT)

static void

CyAstoriaISR (

    void *dev_id)

{

#ifdef SPI_DEBUG_LOG

	Kern::Printf("CyAstoriaISR...");

#endif

	gpDfc->Add();

#ifdef SPI_DEBUG_LOG

	Kern::Printf("Disable interrupt");

#endif

	/* Disable Interrupt Here, it will be re-enabled by DFCs */

	GPIO::DisableInterrupt(KGPIO_INT) ;

}

static void

CyAstoriaIntHandler_DFC (

    TAny *aPtr)

{

    CyAsOmapDevKernel *dev_p = (CyAsOmapDevKernel *)aPtr ;

    uint16_t          read_val = 0 ;

#ifdef SPI_DEBUG_LOG

	Kern::Printf("CyAstoriaIntHandler called...");

#endif

    {

		read_val = CyAsHalReadRegister((CyAsHalDeviceTag)dev_p, CY_AS_MEM_P0_INTR_REG) ;

		if (read_val & CYAS_INT_MASK)

		{

			CyAsIntrServiceInterrupt((CyAsHalDeviceTag)dev_p) ;

		}

		if (read_val & CYAS_DRQ_MASK)

		{

			CyHandleDRQInterrupt(dev_p) ;

		}

    }

	GPIO::EnableInterrupt(KGPIO_INT) ;

#ifdef SPI_DEBUG_LOG

	Kern::Printf("Enable interrupt\n");

#endif

}

extern TmtpAstDev * g_pAstDevice ;

static int

CyAsHalConfigureInterrupts (

    void *dev_p,

	void *handler)

{

    return CyAsHalBeagleBoard__SetupISR(handler, dev_p) ;

}

//nxz-debug

void

MyOmapStartIntr(CyAsHalDeviceTag tag)

{

    CyAsOmapDevKernel *dev_p = (CyAsOmapDevKernel *)tag ;

	int ret ;

    const uint16_t mask = CY_AS_MEM_P0_INTR_REG_DRQINT | CY_AS_MEM_P0_INTR_REG_MBINT ;

	/* Setup DFC */

	gpDfc = new TDfc( CyAstoriaIntHandler_DFC, tag, Kern::DfcQue0(), 1 ) ;

    /* Register for interrupts */

    ret = CyAsHalConfigureInterrupts (dev_p,(void*)CyAstoriaISR) ;

	if ( ret != 0 )

		Kern::Printf("ERROR: CyAsHalConfigureInterrupts failed\n");

    /* enable only MBox & DRQ interrupts for now */

    CyAsHalWriteRegister((CyAsHalDeviceTag)dev_p, CY_AS_MEM_P0_INT_MASK_REG, mask) ;

}

volatile CyBool interrupt_fired = CyFalse;

//This is the Diagnostics Interrupt Handler

void

MyIntTestHandler(

	void *dev_id)

{

    CyAsOmapDevKernel * dev_tag = (CyAsOmapDevKernel*) dev_id ;

	Kern::Printf("Diag: CyAsDiagIntHandler called\n");

	if(interrupt_fired == CyFalse)

	{

			Kern::Printf("Diag: CyAsDiagIntHandler, first instance of INT# \n");

			interrupt_fired = CyTrue;

			//return INT to high state, only called for override testing

			CyAsHalWriteRegister(dev_tag, CY_AS_MEM_P0_VM_SET, 0x0745);

	}

	//return INT to high state, only called for override testing

	CyAsHalWriteRegister(dev_tag, CY_AS_MEM_P0_VM_SET, 0x0745);

}

/*

* These are the functions that are not part of the HAL layer, but are required to be called

* for this HAL.

*/

int StartOMAPKernel(const char *pgm, CyAsHalDeviceTag *tag, CyBool debug)

{

    CyAsOmapDevKernel *dev_p ;

    CyAsHalSleepChannel channel ;

    int i;

    (void)debug ; /* No debug mode support as of now */

    Kern::Printf ("<1>startOMAPKernel called\n");

    /*

     * Initialize the HAL level endpoint DMA data.

     */

    for(i = 0 ; i < sizeof(EndPoints)/sizeof(EndPoints[0]) ; i++)

    {

        EndPoints[i].data_p = 0 ;

        EndPoints[i].pending = CyFalse ;

        EndPoints[i].size = 0 ;

        EndPoints[i].type = CyAsHalNone ;

		EndPoints[i].bytes_xfered = 0 ;

		EndPoints[i].transfer_cnt = 0 ;

    }

    dev_p = (CyAsOmapDevKernel *)CyAsHalAlloc(sizeof(CyAsOmapDevKernel)) ;

    if (dev_p == 0)

    {

		Kern::Printf("<1>%s: out of memory allocating OMAP device structure\n", pgm) ;

		return 0 ;

    }

    dev_p->m_sig = CY_AS_OMAP_KERNEL_HAL_SIG ;

    dev_p->m_addr_base = 0 ;

    CyAsHalBeagleBoard__ConfigureSPI();

#ifdef HW_TEST

{

    uint16_t readVal = 0 ;

	uint16_t timeOutCounter = 0 ;

	uint16_t errCnt = 0 ;

	Kern::Printf( "<1> Regsiter Test ------------->\n") ;

	readVal = CyAsHalReadRegister(dev_p, CY_AS_MEM_CM_WB_CFG_ID) ;

	Kern::Printf("ID reg 0x%04x\n",readVal);

        if ( readVal != 0xa200 )

	{

		Kern::Printf("ERROR: Wrong Antioch ID reg value\n");

		Kern::Printf("ERROR: Exp:  0x%04x\n",0xa200);

		Kern::Printf("ERROR: Act:  0x%04x\n",readVal);

		errCnt++;

	}

	readVal = CyAsHalReadRegister(dev_p, CY_AS_MEM_P0_VM_SET) ;

	Kern::Printf("P0_VM_SET 0x%04x\n",readVal);

	if ( readVal != 0x45 )

	{

		Kern::Printf("ERROR: Wrong Antioch P0_VM_SET reg value\n");

		Kern::Printf("ERROR: Exp:  0x%04x\n",0x45);

		Kern::Printf("ERROR: Act:  0x%04x\n",readVal);

		errCnt++;

	}

	readVal = CyAsHalReadRegister(dev_p, CY_AS_MEM_P0_RSE_ALLOCATE) ;

	Kern::Printf("P0_RSE_ALLOCATE 0x%04x\n",readVal);

	if ( readVal != 0x26 )

	{

		Kern::Printf("ERROR: Wrong Antioch P0_RSE_ALLOCATE reg value\n");

		Kern::Printf("ERROR: Exp:  0x%04x\n",0x26);

		Kern::Printf("ERROR: Act:  0x%04x\n",readVal);

		errCnt++;

	}

	CyAsHalWriteRegister(dev_p, CY_AS_MEM_MCU_MAILBOX0, 0x0);

	CyAsHalWriteRegister(dev_p, CY_AS_MEM_MCU_MAILBOX1, 0xFFFF);

	CyAsHalWriteRegister(dev_p, CY_AS_MEM_MCU_MAILBOX2, 0xAAAA);

	CyAsHalWriteRegister(dev_p, CY_AS_MEM_MCU_MAILBOX3, 0x5555);

	readVal = CyAsHalReadRegister(dev_p, CY_AS_MEM_MCU_MAILBOX0) ;

	Kern::Printf("mailbox0 0x%04x\n",readVal);

	if ( readVal != 0x0 )

	{

		Kern::Printf("ERROR: Wrong Antioch MAILBOX0 reg value\n");

		Kern::Printf("ERROR: Exp:  0x%04x\n",0x0);

		Kern::Printf("ERROR: Act:  0x%04x\n",readVal);

		errCnt++;

	}

	readVal = CyAsHalReadRegister(dev_p, CY_AS_MEM_MCU_MAILBOX1) ;

	Kern::Printf("mailbox1 0x%04x\n",readVal);

	if ( readVal != 0xffff )

	{

		Kern::Printf("ERROR: Wrong Antioch MAILBOX1 reg value\n");

		Kern::Printf("ERROR: Exp:  0x%04x\n",0xffff);

		Kern::Printf("ERROR: Act:  0x%04x\n",readVal);

		errCnt++;

	}

	readVal = CyAsHalReadRegister(dev_p, CY_AS_MEM_MCU_MAILBOX2) ;

    Kern::Printf("mailbox2 0x%04x\n",readVal);

	if ( readVal != 0xaaaa )

	{

		Kern::Printf("ERROR: Wrong Antioch MAILBOX2 reg value\n");

		Kern::Printf("ERROR: Exp:  0x%04x\n",0xaaaa);

		Kern::Printf("ERROR: Act:  0x%04x\n",readVal);

		errCnt++;

	}

	readVal = CyAsHalReadRegister(dev_p, CY_AS_MEM_MCU_MAILBOX3) ;

    Kern::Printf("mailbox3 0x%04x\n",readVal);

	if ( readVal != 0x5555 )

	{

		Kern::Printf("ERROR: Wrong Antioch MAILBOX3 reg value\n");

		Kern::Printf("ERROR: Exp:  0x%04x\n",0x5555);

		Kern::Printf("ERROR: Act:  0x%04x\n",readVal);

		errCnt++;

	}

	Kern::Printf( "<1> Interrupt Test ------------->\n") ;

	Kern::Printf("Checking that INT# can execute Procesor ISR:\n");

	CyAsHalConfigureInterrupts (dev_p,(void*)MyIntTestHandler) ;

	//overrid default INT# value, cause Astoria to assert INT#

	CyAsHalWriteRegister(dev_p, CY_AS_MEM_P0_VM_SET, 0x0545);

	do {

		timeOutCounter++;

	}while((interrupt_fired == CyFalse) && (timeOutCounter < 255));

	if(interrupt_fired == CyTrue)

	{

		Kern::Printf("INT# fired Processor ISR\n");

	}

	else

	{

		Kern::Printf("ERROR: INT# did not fire processor ISR %i\n", interrupt_fired);

		errCnt++;

	}

	if ( errCnt == 0 )

	{

		Kern::Printf("HW test passed!!\n") ;

	}

	else

		Kern::Printf("HW test failed (%d)\n",errCnt) ;

	Kern::Printf("Reset Astoria\n") ;

	CyAsHalWriteRegister(dev_p, CY_AS_MEM_RST_CTRL_REG, CY_AS_MEM_RST_CTRL_REG_HARD) ;

	return 0 ;

}

#endif

    /*

     * Now perform a hard reset of the device to have the new settings take

     * effect

     */

    Kern::Printf("<1>West Bridge Device Enters hard reset\n") ;

    CyAsHalWriteRegister(dev_p, CY_AS_MEM_RST_CTRL_REG, CY_AS_MEM_RST_CTRL_REG_HARD) ;

    /*

     * Sleep for 100 ms to be sure reset is complete.

     */

    Kern::Printf("<1>Sleep 100ms\n") ;

    CyAsHalCreateSleepChannel (&channel) ;

    CyAsHalSleepOn(&channel, 100) ;

    CyAsHalDestroySleepChannel(&channel) ;

	Kern::Printf("<1>MyOmapStartIntr\n") ;

    MyOmapStartIntr(dev_p);

    dev_p->m_next_p = m_omap_list_p ;

    m_omap_list_p = dev_p ;

    *tag = dev_p ;

    gDevTag = dev_p ;

    return 1 ;

}

int StopOMAPKernel(const char *pgm, CyAsHalDeviceTag tag)

{

    CyAsOmapDevKernel *dev_p = (CyAsOmapDevKernel *)tag ;

    if (0 == dev_p)

		return 1 ;

    Kern::Printf ("<1>StopOMAPKernel called\n");

    if (dev_p->m_sig != CY_AS_OMAP_KERNEL_HAL_SIG)

    {

		Kern::Printf("<1>%s: %s: bad TAG parameter passed to function\n", pgm, __FUNCTION__) ;

		return 1 ;

    }

    Kern::Printf ("<1>West Bridge OMAP Kernel: Done cleaning thread\n") ;

	/* TODO: */

    CyAsHalFree(dev_p) ;

    return 1 ;

}

/*************************************************************************************************

*

* Below are the functions that communicate with the West Bridge device.  These are system dependent

* and must be defined by the HAL layer for a given system.

*

*************************************************************************************************/

void

CyAsHalWriteEP(CyAsHalDeviceTag tag, uint16_t addr, uint8_t* data, uint16_t size)

{

    CyAsOmapDevKernel *dev_p = (CyAsOmapDevKernel *)tag ;

GPIO::DisableInterrupt(KGPIO_INT) ;

    /* Do additional error checks while in debug mode. */

    if (dev_p->m_sig != CY_AS_OMAP_KERNEL_HAL_SIG)

    {

		Kern::Printf("<1>%s: bad TAG parameter passed to function\n",  __FUNCTION__) ;

		return ;

    }

    if (addr & 0x80)

    {

		Kern::Printf ("<1>West Bridge write EP address 0x%x out of range\n", addr);

		return ;

    }

	CyAsHalBeagleBoardMcSPI4Ch0_WriteEP(addr, data, size) ;

GPIO::EnableInterrupt(KGPIO_INT) ;

    return ;

}

void

CyAsHalReadEP(CyAsHalDeviceTag tag, uint16_t addr, uint8_t* data, uint16_t size)

{

    CyAsOmapDevKernel *dev_p = (CyAsOmapDevKernel *)tag ;

GPIO::DisableInterrupt(KGPIO_INT) ;

    /* Do additional error checks while in debug mode. */

    if (dev_p->m_sig != CY_AS_OMAP_KERNEL_HAL_SIG)

    {

		Kern::Printf("<1>%s: bad TAG parameter passed to function\n",  __FUNCTION__) ;

		return ;

    }

    if (addr & 0x80)

    {

		Kern::Printf ("<1>West Bridge write EP address 0x%x out of range\n", addr);

		return ;

    }

	CyAsHalBeagleBoardMcSPI4Ch0_ReadEP(addr, data, size) ;

GPIO::EnableInterrupt(KGPIO_INT) ;

    return ;

}

/*

* This function must be defined to write a register within the West Bridge

* device.  The addr value is the address of the register to write with

* respect to the base address of the West Bridge device.

*/

void

CyAsHalWriteRegister(CyAsHalDeviceTag tag, uint16_t addr, uint16_t data)

{

    CyAsOmapDevKernel *dev_p = (CyAsOmapDevKernel *)tag ;

GPIO::DisableInterrupt(KGPIO_INT) ;

    /* Do additional error checks while in debug mode. */

    if (dev_p->m_sig != CY_AS_OMAP_KERNEL_HAL_SIG)

    {

		Kern::Printf("<1>%s: bad TAG parameter passed to function\n",  __FUNCTION__) ;

		return ;

    }

    if (addr > CYAS_DEV_MAX_ADDR)

    {

		Kern::Printf ("<1>West Bridge write address 0x%x out of range\n", addr);

		return ;

    }

	CyAsHalBeagleBoardMcSPI4Ch0_WriteReg((TUint32) addr, (TUint16) data) ;

#ifdef SPI_DEBUG_LOG

	Kern::Printf("CyAsHalWriteRegister(0x%02x,0x%04x)\n",addr,data) ;

#endif

GPIO::EnableInterrupt(KGPIO_INT) ;

    return ;

}

/*

* This function must be defined to read a register from the West Bridge

* device.  The addr value is the address of the register to read with

* respect to the base address of the West Bridge device.

*/

uint16_t

CyAsHalReadRegister(CyAsHalDeviceTag tag, uint16_t addr)

{

    uint16_t data  = 0 ;

    CyAsOmapDevKernel *dev_p = (CyAsOmapDevKernel *)tag ;

GPIO::DisableInterrupt(KGPIO_INT) ;

    if (dev_p->m_sig != CY_AS_OMAP_KERNEL_HAL_SIG)

    {

		Kern::Printf("<1>%s: bad TAG parameter passed to function\n",  __FUNCTION__) ;

		return 0 ;

    }