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// Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies).
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// All rights reserved.
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// This component and the accompanying materials are made available
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// under the terms of the License "Eclipse Public License v1.0"
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// which accompanies this distribution, and is available
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// at the URL "http://www.eclipse.org/legal/epl-v10.html".
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//
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// Initial Contributors:
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// Nokia Corporation - initial contribution.
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//
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// Contributors:
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//
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// Description:
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// omap3530/omap3530_drivers/uart/uart.cpp
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// This file is part of the Beagle Base port
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//
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#include <e32cmn.h>
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#include <assp/omap3530_assp/omap3530_uart.h>
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LOCAL_C void ClientPanic( TInt aLine )
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{
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_LIT( KString, "uart.cpp" );
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Kern::PanicCurrentThread( KString, aLine );
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}
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namespace Omap3530Uart
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{
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struct THwInfo
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{
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TUint32 iBaseAddress;
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TInt iInterruptId;
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Prcm::TClock iInterfaceClock : 16;
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Prcm::TClock iFunctionClock : 16;
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// Omap3530Prm::TPrmId iPrmInterfaceClock : 16;
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// Omap3530Prm::TPrmId iPrmFunctionClock : 16;
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};
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static const THwInfo KHwInfo[3] =
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{
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{ // EUart0
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TUartTraits< EUart0 >::KBaseAddress,
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TUartTraits< EUart0 >::KInterruptId,
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TUartTraits< EUart0 >::KInterfaceClock,
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TUartTraits< EUart0 >::KFunctionClock,
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// TUartTraits< EUart0 >::KPrmInterfaceClock,
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// TUartTraits< EUart0 >::KPrmFunctionClock
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},
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{ // EUart1
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TUartTraits< EUart1 >::KBaseAddress,
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TUartTraits< EUart1 >::KInterruptId,
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TUartTraits< EUart1 >::KInterfaceClock,
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TUartTraits< EUart1 >::KFunctionClock,
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// TUartTraits< EUart1 >::KPrmInterfaceClock,
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// TUartTraits< EUart1 >::KPrmFunctionClock
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},
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{ // EUart2
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TUartTraits< EUart2 >::KBaseAddress,
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TUartTraits< EUart2 >::KInterruptId,
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TUartTraits< EUart2 >::KInterfaceClock,
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TUartTraits< EUart2 >::KFunctionClock,
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// TUartTraits< EUart2 >::KPrmInterfaceClock,
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// TUartTraits< EUart2 >::KPrmFunctionClock
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},
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};
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// Baud lookup table, indexed by [ TBaud, TUartMode ].
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// Values obtained from 3530 datasheet
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struct TBaudInfo
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{
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TUint8 iDlh;
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TUint8 iDll;
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TUint8 iMultiplier; // Multiplier selection for UART16x/13x mode
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};
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static const TBaudInfo KBaudControl[ TUart::KSupportedBaudCount ][ TUart::KSupportedUartModes ] =
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{
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// EUart EUartAutoBaud ESIR EMIR EFIR ECIR
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/*1200*/ { {0x09, 0xC4, 16 }, {0x09, 0xC4, 16 }, {0x09, 0xC4, 16 }, {0x00, 0x02, 1 }, {0x00, 0x0, 1 }, {0x09, 0xC4, 16 } },
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/*2400*/ { {0x04, 0xE2, 16 }, {0x04, 0xE2, 16 }, {0x04, 0xE2, 16 }, {0x00, 0x02, 1 }, {0x00, 0x0, 1 }, {0x09, 0xC4, 16 } },
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/*4800*/ { {0x02, 0x71, 16 }, {0x02, 0x71, 16 }, {0x02, 0x71, 16 }, {0x00, 0x02, 1 }, {0x00, 0x0, 1 }, {0x09, 0xC4, 16 } },
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/*9600*/ { {0x01, 0x38, 16 }, {0x01, 0x38, 16 }, {0x01, 0x38, 16 }, {0x00, 0x02, 1 }, {0x00, 0x0, 1 }, {0x09, 0xC4, 16 } },
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/*14400*/ { {0x00, 0xD0, 16 }, {0x00, 0xD0, 16 }, {0x00, 0xD0, 16 }, {0x00, 0x02, 1 }, {0x00, 0x0, 1 }, {0x09, 0xC4, 16 } },
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/*19200*/ { {0x00, 0x9C, 16 }, {0x00, 0x9C, 16 }, {0x00, 0x9C, 16 }, {0x00, 0x02, 1 }, {0x00, 0x0, 1 }, {0x09, 0xC4, 16 } },
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/*28800*/ { {0x00, 0x68, 16 }, {0x00, 0x68, 16 }, {0x00, 0x68, 16 }, {0x00, 0x02, 1 }, {0x00, 0x0, 1 }, {0x09, 0xC4, 16 } },
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/*38400*/ { {0x00, 0x4E, 16 }, {0x00, 0x4E, 16 }, {0x00, 0x4E, 16 }, {0x00, 0x02, 1 }, {0x00, 0x0, 1 }, {0x09, 0xC4, 16 } },
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/*57600*/ { {0x00, 0x34, 16 }, {0x00, 0x34, 16 }, {0x00, 0x34, 16 }, {0x00, 0x02, 1 }, {0x00, 0x0, 1 }, {0x09, 0xC4, 16 } },
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/*115200*/ { {0x00, 0x1A, 16 }, {0x00, 0x1A, 16 }, {0x00, 0x1A, 16 }, {0x00, 0x01, 1 }, {0x00, 0x0, 1 }, {0x09, 0xC4, 16 } },
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/*230400*/ { {0x00, 0x0D, 16 }, {0x09, 0xC4, 16 }, {0x00, 0x1A, 16 }, {0x00, 0x01, 1 }, {0x00, 0x0, 1 }, {0x09, 0xC4, 16 } },
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/*460800*/ { {0x00, 0x08, 13 }, {0x09, 0xC4, 13 }, {0x00, 0x1A, 16 }, {0x00, 0x01, 1 }, {0x00, 0x0, 1 }, {0x09, 0xC4, 13 } },
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/*921600*/ { {0x00, 0x04, 13 }, {0x09, 0xC4, 13 }, {0x00, 0x1A, 16 }, {0x00, 0x01, 1 }, {0x00, 0x0, 1 }, {0x09, 0xC4, 13 } },
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/*1843000*/ { {0x00, 0x02, 13 }, {0x09, 0xC4, 13 }, {0x00, 0x1A, 16 }, {0x00, 0x01, 1 }, {0x00, 0x0, 1 }, {0x09, 0xC4, 13 } },
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/*3688400*/ { {0x00, 0x01, 13 }, {0x09, 0xC4, 13 }, {0x00, 0x1A, 16 }, {0x00, 0x01, 1 }, {0x00, 0x0, 1 }, {0x09, 0xC4, 13 } },
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/*4000000*/ { {0x00, 0x01, 13 }, {0x09, 0xC4, 13 }, {0x00, 0x1A, 16 }, {0x00, 0x01, 1 }, {0x00, 0x0, 1 }, {0x09, 0xC4, 13 } }
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};
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/** Default mode to target mode conversion */
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static const MDR1::MODE_SELECT::TMode KDefaultTargetMode[ TUart::KSupportedUartModes ] =
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{
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MDR1::MODE_SELECT::EUart16x, // EUart
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MDR1::MODE_SELECT::EUart16xAutoBaud, // EUartAutoBaud
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MDR1::MODE_SELECT::ESIR, // ESIR
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MDR1::MODE_SELECT::EMIR, // EMIR
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MDR1::MODE_SELECT::EFIR, // EFIR
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MDR1::MODE_SELECT::ECIR, // ECIR
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};
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/** Conversion table from parity mode to LCR bit settings */
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static const TUint8 KParitySelectTable[ 5 ] =
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{
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LCR::PARITY_TYPE2::KOff bitor LCR::PARITY_TYPE1::KOff bitor LCR::PARITY_EN::KOff, // ENone,
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LCR::PARITY_TYPE2::KOff bitor LCR::PARITY_TYPE1::KOff bitor LCR::PARITY_EN::KOn, // EOdd,
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LCR::PARITY_TYPE2::KOff bitor LCR::PARITY_TYPE1::KOn bitor LCR::PARITY_EN::KOn, // EEven,
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LCR::PARITY_TYPE2::KOn bitor LCR::PARITY_TYPE1::KOff bitor LCR::PARITY_EN::KOn, // EMark,
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LCR::PARITY_TYPE2::KOn bitor LCR::PARITY_TYPE1::KOn bitor LCR::PARITY_EN::KOn, // ESpace
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};
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static const TUint8 KRxFifoTrigTable[] =
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{
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FCR::RX_FIFO_TRIG::K8Char, // EFifoTrigger8,
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FCR::RX_FIFO_TRIG::K16Char, // EFifoTrigger16,
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FCR::RX_FIFO_TRIG::K16Char, // EFifoTrigger32,
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FCR::RX_FIFO_TRIG::K56Char, // EFifoTrigger56,
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FCR::RX_FIFO_TRIG::K60Char, // EFifoTrigger60
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};
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static const TUint8 KTxFifoTrigTable[] =
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{
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FCR::TX_FIFO_TRIG::K8Char, // EFifoTrigger8,
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FCR::TX_FIFO_TRIG::K16Char, // EFifoTrigger16,
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FCR::TX_FIFO_TRIG::K32Char, // EFifoTrigger32,
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FCR::TX_FIFO_TRIG::K56Char, // EFifoTrigger56,
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FCR::TX_FIFO_TRIG::K56Char, // EFifoTrigger60
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};
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// RAII for entering and leaving mode B with enhanced enabled
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class TRaiiEnhancedModeB
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{
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public:
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TRaiiEnhancedModeB( TUart& aUart );
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~TRaiiEnhancedModeB();
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private:
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TRaiiEnhancedModeB();
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private:
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TUart& iUart;
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TUint8 iOldLcr;
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TUint8 iOldEnhanced;
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};
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TRaiiEnhancedModeB::TRaiiEnhancedModeB( TUart& aUart )
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: iUart( aUart )
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{
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iOldLcr = LCR::iMem.Read( aUart );
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LCR::iMem.Write( aUart, LCR::KConfigModeB );
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iOldEnhanced = EFR::iMem.Read( aUart ) bitand EFR::ENHANCED_EN::KMask;
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EFR::iMem.Modify( aUart, KClearNone, EFR::ENHANCED_EN::KOn );
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}
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TRaiiEnhancedModeB::~TRaiiEnhancedModeB()
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{
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LCR::iMem.Write( iUart, LCR::KConfigModeB );
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EFR::iMem.Modify( iUart, EFR::ENHANCED_EN::KMask, iOldEnhanced );
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LCR::iMem.Write( iUart, iOldLcr );
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}
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EXPORT_C void TUart::Init()
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{
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// Perfom a UART soft reset
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SYSC::iMem.Write( *this, SYSC::SOFTRESET::KOn );
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while( 0 == (SYSS::iMem.Read( *this ) bitand SYSS::RESETDONE::KMask) );
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LCR::iMem.Write( *this, LCR::KConfigModeB );
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EFR::iMem.Modify( *this, KClearNone, EFR::ENHANCED_EN::KOn );
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LCR::iMem.Write( *this, LCR::KConfigModeA );
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MCR::iMem.Modify( *this, KClearNone, MCR::TCR_TLR::KOn );
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FCR::iMem.Write( *this, FCR::FIFO_EN::KOn
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bitor FCR::RX_FIFO_CLEAR::KOn
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bitor FCR::TX_FIFO_CLEAR::KOn );
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LCR::iMem.Write( *this, LCR::KConfigModeB );
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EFR::iMem.Modify( *this, EFR::ENHANCED_EN::KOn, KSetNone );
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LCR::iMem.Write( *this, LCR::KConfigModeA );
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MCR::iMem.Modify( *this, MCR::TCR_TLR::KOn, KSetNone );
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LCR::iMem.Write( *this, LCR::KConfigModeOperational );
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}
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EXPORT_C TInt TUart::InterruptId() const
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{
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return KHwInfo[ iUartNumber ].iInterruptId;
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}
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EXPORT_C Prcm::TClock TUart::PrcmInterfaceClk() const
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{
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return KHwInfo[ iUartNumber ].iInterfaceClock;
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}
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EXPORT_C Prcm::TClock TUart::PrcmFunctionClk() const
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{
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return KHwInfo[ iUartNumber ].iFunctionClock;
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}
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/*PORT_C TInt TUart::PrmInterfaceClk() const
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{
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return KHwInfo[ iUartNumber ].iPrmInterfaceClock;
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}
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EXPORT_C TInt TUart::PrmFunctionClk() const
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{
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return KHwInfo[ iUartNumber ].iPrmFunctionClock;
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}
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*/
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EXPORT_C void TUart::DefineMode( const TUartMode aMode )
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{
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__ASSERT_DEBUG( (TUint)aMode <= KSupportedUartModes, ClientPanic( __LINE__ ) );
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iMode = aMode;
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iTargetMode = KDefaultTargetMode[ aMode ];
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}
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EXPORT_C void TUart::Enable()
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{
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// UART won't be enabled if a read-write cycle is done to MDR1
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// So just write the mode into MDR1 and clear anythis already in register
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// MDR1::iMem.Modify( *this, MDR1::MODE_SELECT::KFieldMask, iTargetMode );
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MDR1::iMem.Write( *this, iTargetMode );
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}
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EXPORT_C void TUart::Disable()
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{
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MDR1::iMem.Modify( *this, MDR1::MODE_SELECT::KFieldMask, MDR1::MODE_SELECT::EDisable );
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}
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EXPORT_C void TUart::SetBaud( const TBaud aBaud )
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{
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__ASSERT_DEBUG( (TUint)aBaud < KSupportedBaudCount, ClientPanic( __LINE__ ) );
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const TUint dlh = KBaudControl[ aBaud ][ iMode ].iDlh;
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const TUint dll = KBaudControl[ aBaud ][ iMode ].iDll;
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{
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TRaiiEnhancedModeB enhanced_mode_b_in_current_scope( *this );
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LCR::iMem.Write( *this, LCR::KConfigModeOperational );
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const TUint8 ier = IER::iMem.Read( *this );
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IER::iMem.Write( *this, 0 );
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LCR::iMem.Write( *this, LCR::KConfigModeB );
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DLL::iMem.Write( *this, dll );
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DLH::iMem.Write( *this, dlh );
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LCR::iMem.Write( *this, LCR::KConfigModeOperational );
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IER::iMem.Write( *this, ier );
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LCR::iMem.Write( *this, LCR::KConfigModeB );
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}
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// Update target mode if a multipler change is required
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if( EUart == iMode )
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{
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const TUint m = KBaudControl[ aBaud ][ iMode ].iMultiplier;
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if( 13 == m )
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{
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iTargetMode = MDR1::MODE_SELECT::EUart13x;
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}
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else
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{
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iTargetMode = MDR1::MODE_SELECT::EUart16x;
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}
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}
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}
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EXPORT_C void TUart::SetDataFormat( const TDataBits aDataBits, const TStopBits aStopBits, const TParity aParity )
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{
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__ASSERT_DEBUG( (TUint)aDataBits <= E8Data, ClientPanic( __LINE__ ) );
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__ASSERT_DEBUG( (TUint)aStopBits <= E2Stop, ClientPanic( __LINE__ ) );
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__ASSERT_DEBUG( (TUint)aParity <= ESpace, ClientPanic( __LINE__ ) );
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const TRegValue8 lcrSet = aDataBits bitor aStopBits bitor KParitySelectTable[ aParity ];
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const TRegValue8 KClearMask = LCR::PARITY_TYPE2::KFieldMask
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bitor LCR::PARITY_TYPE1::KFieldMask
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bitor LCR::PARITY_EN::KFieldMask
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bitor LCR::NB_STOP::KFieldMask
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bitor LCR::CHAR_LENGTH::KFieldMask;
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LCR::iMem.Modify( *this, KClearMask, lcrSet );
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}
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EXPORT_C void TUart::EnableFifo( const TEnableState aState, const TFifoTrigger aRxTrigger, const TFifoTrigger aTxTrigger )
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{
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TRaiiEnhancedModeB enhanced_mode_b_in_current_scope( *this );
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const TUint8 dll = DLL::iMem.Read( *this );
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const TUint8 dlh = DLH::iMem.Read( *this );
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DLL::iMem.Write( *this, 0 );
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DLH::iMem.Write( *this, 0 );
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const TUint8 rx_trig = ((TUint)aRxTrigger >= ETriggerUnchanged)
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? 0
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: KRxFifoTrigTable[ aRxTrigger ];
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const TUint8 tx_trig = ((TUint)aTxTrigger >= ETriggerUnchanged)
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? 0
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: KTxFifoTrigTable[ aTxTrigger ];
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const TUint8 KClearMask = TUint8(Omap3530Uart::FCR::RX_FIFO_TRIG::KFieldMask bitor Omap3530Uart::FCR::TX_FIFO_TRIG::KFieldMask);
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if( EEnabled == aState )
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{
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FCR::iMem.Modify( *this,
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KClearMask,
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rx_trig bitor tx_trig bitor FCR::FIFO_EN::KOn );
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}
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else
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{
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FCR::iMem.Modify( *this, FCR::FIFO_EN::KOn, KSetNone );
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320 |
}
|
|
321 |
|
|
322 |
DLL::iMem.Write( *this, dll );
|
|
323 |
DLH::iMem.Write( *this, dlh );
|
|
324 |
}
|
|
325 |
|
|
326 |
|
|
327 |
LOCAL_C void ModifyIER( TUart& aUart, TUint8 aClearMask, TUint8 aSetMask )
|
|
328 |
{
|
|
329 |
TRaiiEnhancedModeB enhanced_mode_b_in_current_scope( aUart );
|
|
330 |
|
|
331 |
LCR::iMem.Write( aUart, Omap3530Uart::LCR::KConfigModeOperational );
|
|
332 |
IER::iMem.Modify( aUart, aClearMask, aSetMask );
|
|
333 |
LCR::iMem.Write( aUart, LCR::KConfigModeB );
|
|
334 |
}
|
|
335 |
|
|
336 |
inline void EnableDisableInterrupt( TUart& aUart, TBool aEnable, TUart::TInterrupt aWhich )
|
|
337 |
{
|
|
338 |
ModifyIER( aUart,
|
|
339 |
(aEnable ? KClearNone : (TUint8)1 << aWhich),
|
|
340 |
(aEnable ? (TUint8)1 << aWhich : KSetNone) );
|
|
341 |
}
|
|
342 |
|
|
343 |
EXPORT_C void TUart::EnableInterrupt( const TInterrupt aWhich )
|
|
344 |
{
|
|
345 |
EnableDisableInterrupt( *this, ETrue, aWhich );
|
|
346 |
}
|
|
347 |
|
|
348 |
EXPORT_C void TUart::DisableInterrupt( const TInterrupt aWhich )
|
|
349 |
{
|
|
350 |
EnableDisableInterrupt( *this, EFalse, aWhich );
|
|
351 |
}
|
|
352 |
|
|
353 |
|
|
354 |
EXPORT_C void TUart::DisableAllInterrupts()
|
|
355 |
{
|
|
356 |
ModifyIER( *this, (TUint8)KClearAll, KSetNone );
|
|
357 |
}
|
|
358 |
|
|
359 |
|
|
360 |
} // namespace Omap3530Uart
|
|
361 |
|
|
362 |
|
|
363 |
DECLARE_STANDARD_EXTENSION()
|
|
364 |
{
|
|
365 |
return KErrNone;
|
|
366 |
}
|
|
367 |
|