// Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies).

// All rights reserved.

// This component and the accompanying materials are made available

// under the terms of the License "Eclipse Public License v1.0"

// which accompanies this distribution, and is available

// at the URL "http://www.eclipse.org/legal/epl-v10.html".

//

// Initial Contributors:

// Nokia Corporation - initial contribution.

//

// Contributors:

//

// Description:

// \omap3530\omap3530_assp\prcm.h

//

#ifndef PRCM_H_

#define PRCM_H_

// Dummy location for redirecting writes which have no effect on a particular clock

// More efficient than having to test for it in code

TUint32 __dummypoke;

#define	KDummy	(TUint32)&__dummypoke

// PLL modes

const TUint32 KPllModeStop	= 0x1;

const TUint32 KPllModeBypass = 0x5;

const TUint32 KPllModeFastRelock = 0x6;

const TUint32 KPllModeLock = 0x7;

const TUint32 KPllModeMask = 0x7;

const TUint32 KPllAutoOff = 0x0;

const TUint32 KPllAutoOn = 0x1;

const TUint32 KPllAutoMask = 0x7;

#ifdef _DEBUG	// to stop warings about unused definitions

const TUint	KPllMaximumDivider		= 127;

const TUint	KPllMaximumMultiplier	= 2047;

#endif

const TUint	KPllDividerMask		= 127;

const TUint	KPllMultiplierMask	= 2047;

const TUint	KPllFreqRangeMask	= 15;

const TUint	KPllRampMask		= 3;

const TUint KPllLpModeMaximumFrequency = 600000000;

// TPll to TClock lookup table

static const Prcm::TClock KPllToClock [] =

	{

	Prcm::EClkMpu,

	Prcm::EClkIva2Pll,

	Prcm::EClkCore,

	Prcm::EClkPeriph,

	Prcm::EClkPeriph2

	};

// struct of info on how to configure each PLL

// this doesn't include settings which are the same for all PLLs

struct TPllControlInfo

	{

	TUint32	iConfigRegister;		// register containing configuration settings

	TUint32	iMulDivRegister;		// register containing multiplier and divider setting

	TUint32	iStatusRegister;		// register containing PLL status

	TUint	iMultShift;				// shift to move multiplier into position

	TUint	iDivShift;				// shift to move divider into position

	TUint	iFreqSelShift;			// shift to move frequency range selection into position

	TUint	iRampShift;				// shift to move ramp bits into position

	TUint	iDriftShift;			// shift to move driftsel into position

	TUint	iLpShift;				// shift to move LP bit into position

	TUint	iLockBit;				// bit number of lock flag in iStatusRegister

	};

static const TPllControlInfo KPllControlInfo[ Prcm::KSupportedPllCount ] =

	{

	//	ConfReg				MulDivReg			StatusReg				MulShift	DivShift	FreqShift	RampShift	DriftShift	LpShift	LockBit

		{ KCM_CLKEN_PLL_MPU,  KCM_CLKSEL1_PLL_MPU,	KCM_IDLEST_PLL_MPU,		8,		0,			4,			8,			3,			10,		0 },		// DPLL1 (mpu)

		{ KCM_CLKEN_PLL_IVA2, KCM_CLKSEL1_PLL_IVA2,	KCM_IDLEST_PLL_IVA2,	8,		0,			4,			8,			3,			10,		0 },		// DPLL2 (iva2)

		{ KCM_CLKEN_PLL,	KCM_CLKSEL1_PLL,		KCM_IDLEST_CKGEN,		16,		8,			4,			8,			3,			10,		0 },		// DPLL3 (core)

		{ KCM_CLKEN_PLL,	KCM_CLKSEL2_PLL,		KCM_IDLEST_CKGEN,		8,		0,			20,			24,			19,			26,		1 },		// DPLL4 (periph)

		{ KCM_CLKEN2_PLL,	KCM_CLKSEL4_PLL,		KCM_IDLEST2_CKGEN,		8,		0,			4,			8,			3,			10,		0 }		// DPLL5 (periph2)

	};

__ASSERT_COMPILE( (sizeof(KPllControlInfo) / sizeof( KPllControlInfo[0] )) == Prcm::KSupportedPllCount );

struct TPllModeInfo

	{

	TUint32		iModeRegister;

	TUint32		iAutoRegister;

	TUint8		iModeShift;

	TUint8		iAutoShift;

	TUint8		_spare[2];

	};

static const TPllModeInfo KPllMode[] =

	{

		// iModeRegister		iAutoRegister			iModeShift	iAutoShift

		{ KCM_CLKEN_PLL_MPU,	KCM_AUTOIDLE_PLL_MPU,	0,			0 },

		{ KCM_CLKEN_PLL_IVA2,	KCM_AUTOIDLE_PLL_IVA2,	0,			0 },

		{ KCM_CLKEN_PLL,		KCM_AUTOIDLE_PLL,		0,			0 },

		{ KCM_CLKEN_PLL,		KCM_AUTOIDLE_PLL,		16,			3 },

		{ KCM_CLKEN2_PLL,		KCM_AUTOIDLE2_PLL,		0,			3 }

	};

__ASSERT_COMPILE( (sizeof(KPllMode) / sizeof( KPllMode[0] )) == Prcm::KSupportedPllCount );

// All dividers in the PRCM fall into one of these classes

// Some are unique to a particular peripheral but some

// are used by multiple peripherals so we can share that implementation

enum TDivType

	{

	EDivNotSupported,

	EDiv_1_2,

	EDivCore_1_2_4,

	EDivCore_3_4_6_96M,

	EDivPll_1_To_16,

	EDivPll_1_To_31,

	EDivUsimClk,

	EDivClkOut_1_2_4_8_16,

	};

struct TDividerInfo

	{

	TUint32		iRegister;

	TUint32		iMask;			// mask of bits to modify in register

	TDivType	iDivType : 8;

	TUint8		iShift;			// number of bits to shift to move divide value into position

	};

static const TDividerInfo KDividerInfo[] =

	{

		{ KCM_CLKSEL2_PLL_MPU,		0x1F,							EDivPll_1_To_16,	0 },	// EClkMpu,		///< DPLL1

		{ KCM_CLKSEL2_PLL_IVA2,		0x1F,							EDivPll_1_To_16,	0 },

		{ KCM_CLKSEL1_PLL,			0x1FU << 27,					EDivPll_1_To_31,	27 },	// EClkCore,		///< DPLL3

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkPeriph,		///< DPLL4

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkPeriph2,	///< DPLL5

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkPrcmInterface,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkEmu,		///< Emulation clock

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkNeon,

		{ KCM_CLKSEL_CORE,			KBit0 | KBit1,					EDiv_1_2,			0 },	// EClkL3Domain,

		{ KCM_CLKSEL_CORE,			KBit2 | KBit3,					EDiv_1_2,			2 },	// EClkL4Domain,

		{ KCM_CLKSEL1_PLL_MPU,		KBit19 | KBit20 | KBit21,		EDivCore_1_2_4,		19 },	// EClkMpuPll_Bypass,	///< DPLL1 bypass frequency

		{ KCM_CLKSEL1_PLL_IVA2,		KBit19 | KBit20 | KBit21,		EDivCore_1_2_4,		19 },	// EClkIva2Pll_Bypass,	///< DPLL2 bypass frequency

		{ KCM_CLKSEL_WKUP,			KBit1 | KBit2,					EDiv_1_2,			1 },	// EClkRM_F,	///< Reset manager functional clock

		{ KCM_CLKSEL3_PLL,			0x1F,							EDivPll_1_To_16,	0 },	// EClk96M		///< 96MHz clock

		{ KCM_CLKSEL5_PLL,			0x1F,							EDivPll_1_To_16,	0 },	// EClk120M		///< 120MHz clock

		{ KCM_CLKOUT_CTRL,			KBit3 | KBit4 | KBit5,			EDivClkOut_1_2_4_8_16,	3 },	// EClkSysOut

		// Functional clocks

		{ KCM_CLKSEL_DSS,			0x1FU << 8,						EDivPll_1_To_16,	8 },	// EClkTv_F,

		{ KCM_CLKSEL_DSS,			0x1F,							EDivPll_1_To_16,	0 },	// EClkDss1_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkDss2_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkCsi2_F,

		{ KCM_CLKSEL_CAM,			0x1F,							EDivPll_1_To_16,	0 },	// EClkCam_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkIva2_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMmc1_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMmc2_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMmc3_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMsPro_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkHdq_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMcBsp1_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMcBsp2_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMcBsp3_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMcBsp4_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMcBsp5_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMcSpi1_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMcSpi2_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMcSpi3_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMcSpi4_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkI2c1_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkI2c2_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkI2c3_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkUart1_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkUart2_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkUart3_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpt1_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpt2_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpt3_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpt4_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpt5_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpt6_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpt7_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpt8_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpt9_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpt10_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpt11_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkUsbTll_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkTs_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkCpeFuse_F,

		{ KCM_CLKSEL_SGX,	KBit0 | KBit1 | KBit2,					EDivCore_3_4_6_96M, 0 },	// EClkSgx_F,

		{ KCM_CLKSEL_WKUP,	KBit3 | KBit4 | KBit5 | KBit6,			EDivUsimClk,		3 },	// EClkUsim_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkSmartReflex2_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkSmartReflex1_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkWdt2_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkWdt3_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpio1_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpio2_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpio3_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpio4_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpio5_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpio6_F,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkUsb120_F,		///< USB host 120MHz functional clock

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkUsb48_F,		///< USB host 48MHz functional clock

	// Interface clocks

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkDss_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkCam_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkIcr_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMmc1_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMmc2_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMmc3_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMsPro_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkHdq_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkAes1_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkAes2_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkSha11_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkSha12_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkDes1_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkDes2_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMcBsp1_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMcBsp2_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMcBsp3_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMcBsp4_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMcBsp5_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkI2c1_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkI2c2_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkI2c3_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkUart1_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkUart2_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkUart3_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMcSpi1_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMcSpi2_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMcSpi3_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMcSpi4_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpt1_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpt2_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpt3_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpt4_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpt5_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpt6_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpt7_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpt8_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpt9_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpt10_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpt11_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpt12_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkMailboxes_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkOmapSCM_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkHsUsbOtg_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkSdrc_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkPka_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkRng_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkUsbTll_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkSgx_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkUsim_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkWdt1_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkWdt2_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkWdt3_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpio1_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpio2_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpio3_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpio4_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpio5_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkGpio6_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClk32Sync_I,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkUsb_I,			///< USB host interface clock

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClk48M

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClk12M

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkSysClk,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkAltClk,

		{ KDummy,					0,								EDivNotSupported,	0 },	// EClkSysClk32k,

	};

__ASSERT_COMPILE( (sizeof(KDividerInfo) / sizeof( KDividerInfo[0] )) == Prcm::KSupportedClockCount );

// Special case divider and mux info for USIM

struct TUsimDivMuxInfo

	{

	Prcm::TClock	iClock : 8;		// source clock

	TUint8			iDivider;		// divider factor

	};

static const TUsimDivMuxInfo UsimDivMuxInfo[16] =

	{

		{ Prcm::EClkSysClk,		1 },	// 0x0

		{ Prcm::EClkSysClk,		1 },	// 0x1

		{ Prcm::EClkSysClk,		2 },	// 0x2

		{ Prcm::EClk96M,		2 },	// 0x3

		{ Prcm::EClk96M,		4 },	// 0x4

		{ Prcm::EClk96M,		8 },	// 0x5

		{ Prcm::EClk96M,		10 },	// 0x6

		{ Prcm::EClk120M,		4 },	// 0x7

		{ Prcm::EClk120M,		8 },	// 0x8

		{ Prcm::EClk120M,		16 },	// 0x9

		{ Prcm::EClk120M,		20 },	// 0xA

		{ Prcm::EClkSysClk,		1 },	// 0xB

		{ Prcm::EClkSysClk,		1 },	// 0xC

		{ Prcm::EClkSysClk,		1 },	// 0xD

		{ Prcm::EClkSysClk,		1 },	// 0xE

		{ Prcm::EClkSysClk,		1 }		// 0xF

	};

// Structure representing a register, mask and enable/disable values

struct TRegisterBitDef

	{

	TUint32	iRegister;

	TUint32	iMask;

	TUint32	iEnablePattern;

	TUint32	iDisablePattern;

	};

// Structure for holding information on clock enable and auto mode

struct TClockEnableAutoInfo

	{

	TRegisterBitDef	iGate;

	TRegisterBitDef	iAuto;

	};

const TUint32 KDummyReadAsDisabled = 1;

const TUint32 KDummyReadAsEnabled = 0;

const TUint32 KBit012	= KBit0 | KBit1 | KBit2;

const TUint32 KBit345	= KBit3 | KBit4 | KBit5;

const TUint32 KBit16_17_18 = KBit16 | KBit17 | KBit18;

// Table of bits to set to enable each clock

// Note where a function doesn't exist, use { KDummy, 0, V, 0 } which will cause a write to harmlessly write

// to __dummypoke and a read to find that the item is disabled if V==KDummyReadAsDisabled and enabled if V=KDummyReadAsEnabled

static const TClockEnableAutoInfo KClockControlTable[] =

	{

		{ { KDummy, 0, 0, 0 },						{ KCM_AUTOIDLE_PLL_MPU, KBit012, 1, 0 } },					// EClkMpu,

		{ { KCM_CLKEN_PLL_IVA2, KBit012, 7, 1 },	{ KCM_AUTOIDLE_PLL_IVA2, KBit0, 1, 0 } },					// EClkIva2Pll,

		{ { KCM_CLKEN_PLL, KBit012, 0x7, 0x5 },						{ KCM_AUTOIDLE_PLL, KBit012, 1, 0 } },		// EClkCore,		///< DPLL3

		{ { KCM_CLKEN_PLL, KBit16_17_18, KBit16_17_18, KBit16 },	{ KCM_AUTOIDLE_PLL, KBit345, KBit3, 0 } },	// EClkPeriph,		///< DPLL4

		{ { KCM_CLKEN2_PLL, KBit012, 0x7, 0x1 },					{ KCM_AUTOIDLE2_PLL, KBit012, 1, 0 } },		// EClkPeriph2,	///< DPLL5

		{ { KDummy, 0, 0, 0 },							{ KDummy, 0, KDummyReadAsEnabled, 0 } },		// EClkPrcmInterface,

		{ { KDummy, 0, 0, 0 },							{ KCM_CLKSTCTRL_EMU, KBit0 | KBit1, 3, 2 } },		// EClkEmu,		///< Emulation clock

		{ { KCM_IDLEST_NEON, KBit0, 0, 1 },				{ KCM_CLKSTCTRL_NEON, KBit0 | KBit1, 3, 2 } },		// EClkNeon,

		{ { KDummy, 0, 0, 0 },							{ KCM_CLKSTCTRL_CORE, KBit0 | KBit1, KBit0 | KBit1, 0 } },		// EClkL3Domain,

		{ { KDummy, 0, 0, 0 },							{ KCM_CLKSTCTRL_CORE, KBit2 | KBit3, KBit2 | KBit3, 0 } },	// EClkL4Domain,

		{ { KDummy, 0, 0, 0 },							{ KDummy, 0, KDummyReadAsEnabled, 0 } },		// EClkMpuPll_Bypass,	///< DPLL1 bypass frequency

		{ { KDummy, 0, 0, 0 },							{ KDummy, 0, KDummyReadAsEnabled, 0 } },		// EClkIva2Pll_Bypass,	///< DPLL2 bypass frequency

		{ { KDummy, 0, 0, 0 },							{ KDummy, 0, KDummyReadAsEnabled, 0 } },		// EClkRM_F,			///< Reset manager functional clock

		{ { KDummy, 0, 0, 0 },							{ KDummy, 0, KDummyReadAsEnabled, 0 } },		// EClk96M,			///< 96MHz clock

		{ { KDummy, 0, 0, 0 },							{ KDummy, 0, KDummyReadAsEnabled, 0 } },		// EClk120M,			///< 120MHz clock

		{ { KDummy, 0, 0, 0 },							{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkSysOut,

	// Functional clocks

		{ { KCM_FCLKEN_DSS, KBit2, KBit2, 0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkTv_F,

		{ { KCM_FCLKEN_DSS, KBit0, KBit0, 0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkDss1_F,

		{ { KCM_FCLKEN_DSS, KBit1, KBit1, 0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkDss2_F,

		{ { KCM_FCLKEN_CAM, KBit1, KBit1, 0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkCsi2_F,

		{ { KCM_FCLKEN_CAM, KBit0, KBit0, 0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkCam_F,

		{ { KCM_FCLKEN_IVA2, KBit0, KBit0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkIva2_F,

		{ { KCM_FCLKEN1_CORE, KBit24, KBit24, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkMmc1_F,

		{ { KCM_FCLKEN1_CORE, KBit25, KBit25, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkMmc2_F,

		{ { KCM_FCLKEN1_CORE, KBit30, KBit30, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkMmc3_F,

		{ { KCM_FCLKEN1_CORE, KBit23, KBit23, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkMsPro_F,

		{ { KCM_FCLKEN1_CORE, KBit22, KBit22, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkHdq_F,

		{ { KCM_FCLKEN1_CORE, KBit9, KBit9, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkMcBSP1_F,

		{ { KCM_FCLKEN_PER, KBit0, KBit0, 0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkMcBSP2_F,

		{ { KCM_FCLKEN_PER, KBit1, KBit1, 0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkMcBSP3_F,

		{ { KCM_FCLKEN_PER, KBit2, KBit2, 0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkMcBSP4_F,

		{ { KCM_FCLKEN1_CORE, KBit10, KBit10, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkMcBSP5_F,

		{ { KCM_FCLKEN1_CORE, KBit18, KBit18, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkMcSpi1_F,

		{ { KCM_FCLKEN1_CORE, KBit19, KBit19, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkMcSpi2_F,

		{ { KCM_FCLKEN1_CORE, KBit20, KBit20, 0 },	{ KDummy, 0, KDummyReadAsEnabled, 0 } },		// EClkMcSpi3_F,

		{ { KCM_FCLKEN1_CORE, KBit21, KBit21, 0 },	{ KDummy, 0, KDummyReadAsEnabled, 0 } },		// EClkMcSpi4_F,

		{ { KCM_FCLKEN1_CORE, KBit15, KBit15, 0},	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkI2c1_F,

		{ { KCM_FCLKEN1_CORE, KBit16, KBit16, 0},	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkI2c2_F,

		{ { KCM_FCLKEN1_CORE, KBit17, KBit17, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkI2c3_F,

		{ { KCM_FCLKEN1_CORE, KBit13, KBit13, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkUart1_F,

		{ { KCM_FCLKEN1_CORE, KBit14, KBit14, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkUart2_F,

		{ { KCM_FCLKEN_PER, KBit11, KBit11, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkUart3_F,

		{ { KCM_FCLKEN_WKUP, KBit0, KBit0, 0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkGpt1_F,

		{ { KCM_FCLKEN_PER, KBit3, KBit3, 0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkGpt2_F,

		{ { KCM_FCLKEN_PER, KBit4, KBit4, 0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkGpt3_F,

		{ { KCM_FCLKEN_PER, KBit5, KBit5, 0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkGpt4_F,

		{ { KCM_FCLKEN_PER, KBit6, KBit6, 0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkGpt5_F,

		{ { KCM_FCLKEN_PER, KBit7, KBit7, 0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkGpt6_F,

		{ { KCM_FCLKEN_PER, KBit8, KBit8, 0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkGpt7_F,

		{ { KCM_FCLKEN_PER, KBit9, KBit9, 0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkGpt8_F,

		{ { KCM_FCLKEN_PER, KBit10, KBit10, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkGpt9_F,

		{ { KCM_FCLKEN1_CORE, KBit11, KBit11, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkGpt10_F,

		{ { KCM_FCLKEN1_CORE, KBit12, KBit12, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkGpt11_F,

		{ { KCM_FCLKEN3_CORE, KBit2, KBit2, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkUsbTll_F,

		{ { KCM_FCLKEN3_CORE, KBit1, KBit1, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkTs_F,

		{ { KCM_FCLKEN3_CORE, KBit0, KBit0, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkCpeFuse_F,

		{ { KCM_FCLKEN_SGX, KBit1, KBit1, 0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkSgx_F,

		{ { KCM_FCLKEN_WKUP, KBit9, KBit9, 0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkUsim_F,

		{ { KCM_FCLKEN_WKUP, KBit7, KBit7, 0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkSmartReflex2_F,

		{ { KCM_FCLKEN_WKUP, KBit6, KBit6, 0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkSmartReflex1_F,

		{ { KCM_FCLKEN_WKUP, KBit5, KBit5, 0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkWdt2_F,

		{ { KCM_FCLKEN_PER, KBit12, KBit12, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkWdt3_F,

		{ { KCM_FCLKEN_WKUP, KBit3, KBit3, 0 },		{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkGpio1_F,

		{ { KCM_FCLKEN_PER, KBit13, KBit13, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkGpio2_F,

		{ { KCM_FCLKEN_PER, KBit14, KBit14, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkGpio3_F,

		{ { KCM_FCLKEN_PER, KBit15, KBit15, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkGpio4_F,

		{ { KCM_FCLKEN_PER, KBit16, KBit16, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkGpio5_F,

		{ { KCM_FCLKEN_PER, KBit17, KBit17, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkGpio6_F,

		{ { KCM_FCLKEN_USBHOST, KBit1, KBit1, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkUsb120_F,

		{ { KCM_FCLKEN_USBHOST, KBit0, KBit0, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },		// EClkUsb48_F,

	// Interface clocks

		{ { KCM_ICLKEN_DSS, KBit0, KBit0, 0 },		{ KCM_AUTOIDLE_DSS, KBit0, KBit0, 0 } },		// EClkDss_I,

		{ { KCM_ICLKEN_CAM, KBit0,KBit0, 0 },		{ KCM_AUTOIDLE_CAM, KBit0, KBit0, 0 } },		// EClkCam_I,

		{ { KCM_ICLKEN1_CORE, KBit29, KBit29, 0 },	{ KCM_AUTOIDLE1_CORE, KBit29, KBit29, 0 } },	// EClkIcr_I,

		{ { KCM_ICLKEN1_CORE, KBit24, KBit24, 0 },	{ KCM_AUTOIDLE1_CORE, KBit24, KBit24, 0 } },	// EClkMmc1_I,

		{ { KCM_ICLKEN1_CORE, KBit25, KBit25, 0 },	{ KCM_AUTOIDLE1_CORE, KBit25, KBit25, 0 } },	// EClkMmc2_I,

		{ { KCM_ICLKEN1_CORE, KBit30, KBit30, 0 },	{ KCM_AUTOIDLE1_CORE, KBit30, KBit30, 0 } },	// EClkMmc3_I,

		{ { KCM_ICLKEN1_CORE, KBit23, KBit23, 0 },	{ KCM_AUTOIDLE1_CORE, KBit23, KBit23, 0 } },	// EClkMsPro_I,

		{ { KCM_ICLKEN1_CORE, KBit22, KBit22, 0 },	{ KCM_AUTOIDLE1_CORE, KBit22, KBit22, 0 } },	// EClkHdq_I,

		{ { KCM_ICLKEN2_CORE, KBit3, KBit3, 0 },	{ KCM_AUTOIDLE2_CORE, KBit3, KBit3, 0 } },		// EClkAes1_I,

		{ { KCM_ICLKEN1_CORE, KBit28, KBit28, 0 },	{ KCM_AUTOIDLE1_CORE, KBit28, KBit28, 0 } },	// EClkAes2_I,

		{ { KCM_ICLKEN2_CORE, KBit1, KBit1, 0 },	{ KCM_AUTOIDLE2_CORE, KBit1, KBit1, 0 } },		// EClkSha11_I,

		{ { KCM_ICLKEN1_CORE, KBit28, KBit27, 0 },	{ KCM_AUTOIDLE1_CORE, KBit27, KBit27, 0 } },	// EClkSha12_I,

		{ { KCM_ICLKEN2_CORE, KBit0, KBit0, 0 },	{ KCM_AUTOIDLE2_CORE, KBit0, KBit0, 0 } },		// EClkDes1_I,

		{ { KCM_ICLKEN1_CORE, KBit26, KBit26, 0 },	{ KCM_AUTOIDLE1_CORE, KBit26, KBit26, 0 } },	// EClkDes2_I,

		{ { KCM_ICLKEN1_CORE, KBit9, KBit9, 0 },	{ KCM_AUTOIDLE1_CORE, KBit9, KBit9, 0 } },		// EClkMcBSP1_I,

		{ { KCM_ICLKEN_PER, KBit0, KBit0, 0},		{ KCM_AUTOIDLE_PER, KBit0, KBit0, 0 } },		// EClkMcBSP2_I,

		{ { KCM_ICLKEN_PER, KBit1, KBit1, 0 },		{ KCM_AUTOIDLE_PER, KBit1, KBit1, 0 } },		// EClkMcBSP3_I,

		{ { KCM_ICLKEN_PER, KBit2, KBit2, 0 },		{ KCM_AUTOIDLE_PER, KBit2, KBit2, 0 } },		// EClkMcBSP4_I,

		{ { KCM_ICLKEN1_CORE, KBit10, KBit10, 0 },	{ KCM_AUTOIDLE1_CORE, KBit10, KBit10, 0 } },	// EClkMcBSP5_I,

		{ { KCM_ICLKEN1_CORE, KBit15, KBit15, 0 },	{ KCM_AUTOIDLE1_CORE, KBit15, KBit15, 0 } },	// EClkI2c1_I,

		{ { KCM_ICLKEN1_CORE, KBit16, KBit16, 0 },	{ KCM_AUTOIDLE1_CORE, KBit16, KBit16, 0 } },	// EClkI2c2_I,

		{ { KCM_ICLKEN1_CORE, KBit17, KBit17, 0 },	{ KCM_AUTOIDLE1_CORE, KBit17, KBit17, 0 } },	// EClkI2c3_I,

		{ { KCM_ICLKEN1_CORE, KBit13, KBit13, 0 },	{ KCM_AUTOIDLE1_CORE, KBit13, KBit13, 0 } },	// EClkUart1_I,

		{ { KCM_ICLKEN1_CORE, KBit14, KBit14, 0 },	{ KCM_AUTOIDLE1_CORE, KBit14, KBit14, 0 } },	// EClkUart2_I,

		{ { KCM_ICLKEN_PER, KBit11, KBit11, 0 },	{ KCM_AUTOIDLE_PER, KBit11, KBit11, 0 } },		// EClkUart3_I,

		{ { KCM_ICLKEN1_CORE, KBit18, KBit18, 0 },	{ KCM_AUTOIDLE1_CORE, KBit18, KBit18, 0 } },	// EClkMcSpi1_I,

		{ { KCM_ICLKEN1_CORE, KBit19, KBit19, 0 },	{ KCM_AUTOIDLE1_CORE, KBit19, KBit19, 0 } },	// EClkMcSpi2_I,

		{ { KCM_ICLKEN1_CORE, KBit20, KBit20, 0 },	{ KCM_AUTOIDLE1_CORE, KBit20, KBit20, 0 } },	// EClkMcSpi3_I,

		{ { KCM_ICLKEN1_CORE, KBit21, KBit21, 0 },	{ KCM_AUTOIDLE1_CORE, KBit21, KBit21, 0 } },	// EClkMcSpi4_I,

		{ { KCM_ICLKEN_WKUP, KBit0, KBit0, 0 },		{ KCM_AUTOIDLE_WKUP, KBit0, KBit0, 0 } },		// EClkGpt1_I,

		{ { KCM_ICLKEN_PER, KBit3, KBit3, 0 },		{ KCM_AUTOIDLE_PER, KBit3, KBit3, 0 } },		// EClkGpt2_I,

		{ { KCM_ICLKEN_PER, KBit4, KBit4, 0 },		{ KCM_AUTOIDLE_PER, KBit4, KBit4, 0 } },		// EClkGpt3_I,

		{ { KCM_ICLKEN_PER, KBit5, KBit5, 0 },		{ KCM_AUTOIDLE_PER, KBit5, KBit5, 0 } },		// EClkGpt4_I,

		{ { KCM_ICLKEN_PER, KBit6, KBit6, 0 },		{ KCM_AUTOIDLE_PER, KBit6, KBit6, 0 } },		// EClkGpt5_I,

		{ { KCM_ICLKEN_PER, KBit7, KBit7, 0 },		{ KCM_AUTOIDLE_PER, KBit7, KBit7, 0 } },		// EClkGpt6_I,

		{ { KCM_ICLKEN_PER, KBit8, KBit8, 0 },		{ KCM_AUTOIDLE_PER, KBit8, KBit8, 0 } },		// EClkGpt7_I,

		{ { KCM_ICLKEN_PER, KBit9, KBit9, 0 },		{ KCM_AUTOIDLE_PER, KBit9, KBit9, 0 } },		// EClkGpt8_I,

		{ { KCM_ICLKEN_PER, KBit10, KBit10, 0 },	{ KCM_AUTOIDLE_PER, KBit10, KBit10, 0 } },		// EClkGpt9_I,

		{ { KCM_ICLKEN1_CORE, KBit11, KBit11, 0 },	{ KCM_AUTOIDLE1_CORE, KBit11, KBit11, 0 } },	// EClkGpt10_I,

		{ { KCM_ICLKEN1_CORE, KBit12, KBit12, 0 },	{ KCM_AUTOIDLE1_CORE, KBit12, KBit12, 0 } },	// EClkGpt11_I,

		{ { KDummy, 0, 0, 0 },						{ KDummy, 0, KDummyReadAsDisabled, 0 } },							// EClkGpt12_I,

		{ { KCM_ICLKEN1_CORE, KBit7, KBit7, 0 },	{ KCM_AUTOIDLE1_CORE, KBit7, KBit7, 0 } },		// EClkMailboxes_I,

		{ { KCM_ICLKEN1_CORE, KBit6, KBit6, 0 },	{ KCM_AUTOIDLE1_CORE, KBit6, KBit6, 0 } },		// EClkOmapSCM_I,

		{ { KCM_ICLKEN1_CORE, KBit4, KBit4, 0 },	{ KCM_AUTOIDLE1_CORE, KBit4, KBit4, 0 } },		// EClkHsUsbOtg_I,

		{ { KCM_ICLKEN1_CORE, KBit1, KBit1, 0 },	{ KDummy, 0, KDummyReadAsDisabled, 0 } },			// EClkSdrc_I,

		{ { KCM_ICLKEN2_CORE, KBit4, KBit4, 0 },	{ KCM_AUTOIDLE2_CORE, KBit4, KBit4, 0 } },		// EClkPka_I,

		{ { KCM_ICLKEN2_CORE, KBit2, KBit2, 0 },	{ KCM_AUTOIDLE2_CORE, KBit2, KBit2, 0 } },		// EClkRng_I,

		{ { KCM_ICLKEN3_CORE, KBit2, KBit2, 0 },	{ KCM_AUTOIDLE3_CORE, KBit2, KBit2, 0 } },		// EClkUsbTll_I,

		{ { KCM_ICLKEN_SGX, KBit0, KBit0, 0 },		{ KCM_CLKSTCTRL_SGX, KBit0 | KBit1, 0x3, 0x0 } },	// EClkSgx_I,

		{ { KCM_ICLKEN_WKUP, KBit9, KBit9, 0 },		{ KCM_AUTOIDLE_WKUP, KBit9, KBit9, 0 } },		// EClkUsim_I,

		{ { KCM_ICLKEN_WKUP, KBit4, KBit4, 0 },		{ KCM_AUTOIDLE_WKUP, KBit4, KBit4, 0 } },		// EClkWdt1_I,

		{ { KCM_ICLKEN_WKUP, KBit5, KBit5, 0 },		{ KCM_AUTOIDLE_WKUP, KBit5, KBit5, 0 } },		// EClkWdt2_I,

		{ { KCM_ICLKEN_PER, KBit12, KBit12, 0 },	{ KCM_AUTOIDLE_PER, KBit12, KBit12, 0 } },		// EClkWdt3_I,

		{ { KCM_ICLKEN_WKUP, KBit3, KBit3, 0 },		{ KCM_AUTOIDLE_WKUP, KBit3, KBit3, 0 } },		// EClkGpio1_I,

		{ { KCM_ICLKEN_PER, KBit13, KBit13, 0 },	{ KCM_AUTOIDLE_PER, KBit13, KBit13, 0 } },		// EClkGpio2_I,

		{ { KCM_ICLKEN_PER, KBit14, KBit14, 0 },	{ KCM_AUTOIDLE_PER, KBit14, KBit14, 0 } },		// EClkGpio3_I,

		{ { KCM_ICLKEN_PER, KBit15, KBit15, 0 },	{ KCM_AUTOIDLE_PER, KBit15, KBit15, 0 } },		// EClkGpio4_I,

		{ { KCM_ICLKEN_PER, KBit16, KBit16, 0 },	{ KCM_AUTOIDLE_PER, KBit16, KBit16, 0 } },		// EClkGpio5_I,

		{ { KCM_ICLKEN_PER, KBit17, KBit17, 0 },	{ KCM_AUTOIDLE_PER, KBit17, KBit17, 0 } },		// EClkGpio6_I,

		{ { KCM_ICLKEN_WKUP, KBit2, KBit2, 0 },		{ KCM_AUTOIDLE_WKUP, KBit2, KBit2, 0 } },		// EClk32Sync_I,

		{ { KCM_ICLKEN_USBHOST, KBit0, KBit0, 0 }, { KCM_AUTOIDLE_USBHOST, KBit0, KBit0, 0 } },		// EClkUsb_I,			///< USB host interface clock

		{ { KDummy, 0, 0, 0 },							{ KDummy, 0, KDummyReadAsEnabled, 0 } },		// EClk48M

		{ { KDummy, 0, 0, 0 },							{ KDummy, 0, KDummyReadAsEnabled, 0 } },		// EClk12M

		{ { KDummy, 0, 0, 0 },							{ KDummy, 0, KDummyReadAsEnabled, 0 } },		// EClkSysClk

		{ { KDummy, 0, 0, 0 },							{ KDummy, 0, KDummyReadAsEnabled, 0 } },		// EClkAltClk

		{ { KDummy, 0, 0, 0 },							{ KDummy, 0, KDummyReadAsEnabled, 0 } },		// EClkSysClk32k

	};

__ASSERT_COMPILE( (sizeof(KClockControlTable) / sizeof( KClockControlTable[0] )) == Prcm::KSupportedClockCount );

static const TRegisterBitDef KClockWakeupTable[] =

	{

		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkMpu,		///< DPLL1

		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkIva2Pll,	///< DPLL2

		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkCore,		///< DPLL3

		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkPeriph,		///< DPLL4

		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkPeriph2,	///< DPLL5

		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkPrcmInterface,

		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkEmu,		///< Emulation clock

		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkNeon,

		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkL3Domain,

		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkL4Domain,

		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkMpuPll_Bypass,	///< DPLL1 bypass frequency

		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkIva2Pll_Bypass,	///< DPLL2 bypass frequency

		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkRM_F,			///< Reset manager functional clock

		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClk96M,			///< 96MHz clock

		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClk120M,			///< 120MHz clock

		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkSysOut,

	// Functional clocks

	// NOTE - functional clocks aren't mapped to a wakeup event, these just clock the internals

	// Use the interface clocks to register a wakeup

		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkTv_F,

		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkDss1_F,

		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkDss2_F,

		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkCsi2_F,

		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkCam_F,

		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkIva2_F,

		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkMmc1_F,

		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkMmc2_F,

		{ KDummy, 0, KDummyReadAsDisabled, 0 },	// EClkMmc3_F,