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// Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies).
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// All rights reserved.
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// This component and the accompanying materials are made available
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// under the terms of the License "Eclipse Public License v1.0"
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// which accompanies this distribution, and is available
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// at the URL "http://www.eclipse.org/legal/epl-v10.html".
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//
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// Initial Contributors:
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// Nokia Corporation - initial contribution.
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//
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// Contributors:
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//
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// Description:
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// omap3530/omap3530_drivers/uart/omap3530_uart.h
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// This file is part of the Beagle Base port
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//
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#ifndef __OMAP3530_UART_H__
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#define __OMAP3530_UART_H__
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#include <assp/omap3530_assp/omap3530_hardware_base.h>
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#include <assp/omap3530_assp/omap3530_prcm.h>
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//#include "assp/omap3530_assp/omap3530_prm.h"
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#include <assp/omap3530_assp/omap3530_irqmap.h>
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//#include "omap3530_prm.h"
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namespace Omap3530Uart
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{
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using namespace TexasInstruments::Omap3530;
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enum TUartNumber
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{
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EUartNone = -1,
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EUart0 = 0,
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EUart1,
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EUart2
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};
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template< const TUartNumber aUartNumber >
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struct TUartTraits
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{
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};
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template<>
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struct TUartTraits< EUart0 >
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{
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static const TUint32 KBaseAddress = Omap3530HwBase::KL4_Core + 0x0006A000;
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static const TInt KInterruptId = EOmap3530_IRQ72_UART1_IRQ;
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static const Prcm::TClock KInterfaceClock = Prcm::EClkUart1_I;
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static const Prcm::TClock KFunctionClock = Prcm::EClkUart1_F;
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// static const Omap3530Prm::TPrmId KPrmInterfaceClock = Omap3530Prm::EPrmClkUart1_I;
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// static const Omap3530Prm::TPrmId KPrmFunctionClock = Omap3530Prm::EPrmClkUart1_F;
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};
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template<>
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struct TUartTraits< EUart1 >
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{
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static const TUint32 KBaseAddress = Omap3530HwBase::KL4_Core + 0x0006C000;
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static const TInt KInterruptId = EOmap3530_IRQ73_UART2_IRQ;
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static const Prcm::TClock KInterfaceClock = Prcm::EClkUart2_I;
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static const Prcm::TClock KFunctionClock = Prcm::EClkUart2_F;
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// static const Omap3530Prm::TPrmId KPrmInterfaceClock = Omap3530Prm::EPrmClkUart2_I;
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// static const Omap3530Prm::TPrmId KPrmFunctionClock = Omap3530Prm::EPrmClkUart2_F;
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};
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template<>
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struct TUartTraits< EUart2 >
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{
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static const TUint32 KBaseAddress = Omap3530HwBase::KL4_Per + 0x00020000;
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static const TInt KInterruptId = EOmap3530_IRQ74_UART3_IRQ;
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static const Prcm::TClock KInterfaceClock = Prcm::EClkUart3_I;
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static const Prcm::TClock KFunctionClock = Prcm::EClkUart3_F;
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// static const Omap3530Prm::TPrmId KPrmInterfaceClock = Omap3530Prm::EPrmClkUart3_I;
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// static const Omap3530Prm::TPrmId KPrmFunctionClock = Omap3530Prm::EPrmClkUart3_F;
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};
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// Forward declaration
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class TUart;
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/** Representation of general UART register set */
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struct DLL
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{
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static const TInt KOffset = 0x00;
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static TDynReg8_RW< TUart, KOffset > iMem;
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typedef TBitField<0,8> CLOCK_LSB;
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};
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struct RHR
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{
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static const TInt KOffset = 0x00;
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static TDynReg8_R< TUart, KOffset > iMem;
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typedef TBitField<0,8> Value;
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};
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struct THR
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{
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static const TInt KOffset = 0x00;
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static TDynReg8_W< TUart, KOffset > iMem;
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typedef TBitField<0,8> Value;
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};
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struct IER
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{
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static const TInt KOffset = 0x04;
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static TDynReg8_RW< TUart, KOffset > iMem;
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typedef TSingleBitField<7> CTS_IT;
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typedef TSingleBitField<6> RTS_IT;
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typedef TSingleBitField<5> XOFF_IT;
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typedef TSingleBitField<4> SLEEP_MODE;
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typedef TSingleBitField<3> MODEM_STS_IT;
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typedef TSingleBitField<2> LINE_STS_IT;
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typedef TSingleBitField<1> THR_IT;
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typedef TSingleBitField<0> RHR_IT;
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};
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struct IER_IRDA
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{
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static const TInt KOffset = 0x04;
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static TDynReg8_RW< TUart, KOffset > iMem;
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typedef TSingleBitField<7> EOF_IT;
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typedef TSingleBitField<6> LINE_STS_IT;
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typedef TSingleBitField<5> TX_STATUS_IT;
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typedef TSingleBitField<4> STS_FIFO_TRIG_IT;
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typedef TSingleBitField<3> RX_OVERRUN_IT;
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typedef TSingleBitField<2> LAST_RX_BYTE_IT;
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typedef TSingleBitField<1> THR_IT;
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typedef TSingleBitField<0> RHR_IT;
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};
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struct DLH
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{
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static const TInt KOffset = 0x04;
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static TDynReg8_RW< TUart, KOffset > iMem;
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typedef TBitField<0,6> CLOCK_MSB;
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};
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struct FCR
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{
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static const TInt KOffset = 0x08;
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static TDynReg8_W< TUart, KOffset > iMem;
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typedef TSingleBitField<0> FIFO_EN;
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typedef TSingleBitField<1> RX_FIFO_CLEAR;
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typedef TSingleBitField<2> TX_FIFO_CLEAR;
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typedef TSingleBitField<3> DMA_MODE;
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struct TX_FIFO_TRIG : public TBitField<4,2>
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{
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enum TConstants
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{
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K8Char = 0 << KShift,
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K16Char = 1 << KShift,
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K32Char = 2 << KShift,
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K56Char = 3 << KShift
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};
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};
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struct RX_FIFO_TRIG : public TBitField<6,2>
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{
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static const TUint8 K8Char = 0 << KShift;
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static const TUint8 K16Char = 1 << KShift;
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static const TUint8 K56Char = 2 << KShift;
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static const TUint8 K60Char = 3 << KShift;
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};
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};
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struct IIR
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{
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static const TInt KOffset = 0x08;
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static TDynReg8_R< TUart, KOffset > iMem;
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typedef TBitField<6,2> FCR_MIRROR;
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struct IT_TYPE : public TBitField<1,5>
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{
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enum TConstants
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{
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EModem = 0 << KShift,
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ETHR = 1 << KShift,
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ERHR = 2 << KShift,
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ERxLineStatus = 3 << KShift,
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ERxTimeout = 6 << KShift,
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EXoff = 8 << KShift,
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ECtsRts = 16 << KShift
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};
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};
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typedef TSingleBitField<0> IT_PENDING;
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};
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struct EFR
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{
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static const TInt KOffset = 0x08;
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static TDynReg8_RW< TUart, KOffset > iMem;
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typedef TSingleBitField<7> AUTO_CTS_EN;
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typedef TSingleBitField<6> AUTO_RTS_EN;
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typedef TSingleBitField<5> SPEC_CHAR;
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typedef TSingleBitField<4> ENHANCED_EN;
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struct SW_FLOW_CONTROL : public TBitField<0,4>
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{
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enum TFlowControl
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{
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ENone = 0,
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EXonXoff1 = 8,
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EXonXoff2 = 4,
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EXonXoffBoth = 8 + 4,
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};
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};
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};
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struct LCR
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{
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static const TInt KOffset = 0x0c;
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static TDynReg8_RW< TUart, KOffset > iMem;
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typedef TSingleBitField<7> DIV_EN;
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typedef TSingleBitField<6> BREAK_EN;
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typedef TSingleBitField<5> PARITY_TYPE2;
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typedef TSingleBitField<4> PARITY_TYPE1;
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typedef TSingleBitField<3> PARITY_EN;
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struct NB_STOP : public TSingleBitField<2>
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{
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enum TConstants
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{
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E1Stop = 0 << KShift,
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E1_5Stop = 1 << KShift,
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E2Stop = 1 << KShift
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};
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};
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struct CHAR_LENGTH : public TBitField<0,2>
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{
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enum TConstants
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{
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E5Bits = 0,
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E6Bits = 1,
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E7Bits = 2,
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E8Bits = 3
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};
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};
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/** Special magic number to enter MODEA */
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static const TUint8 KConfigModeA = 0x80;
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/** Special magic number to enter MODEB */
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static const TUint8 KConfigModeB = 0xBF;
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/** Special magic number to enter operational mode */
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static const TUint8 KConfigModeOperational = 0x00;
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};
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struct MCR
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{
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static const TInt KOffset = 0x10;
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static TDynReg8_RW< TUart, KOffset > iMem;
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typedef TSingleBitField<6> TCR_TLR;
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typedef TSingleBitField<5> XON_EN;
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typedef TSingleBitField<4> LOOPBACK_EN;
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typedef TSingleBitField<3> CD_STS_CH;
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typedef TSingleBitField<2> RI_STS_CH;
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typedef TSingleBitField<1> RTS;
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typedef TSingleBitField<0> DTR;
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};
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struct XON1_ADDR1
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{
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static const TInt KOffset = 0x10;
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static TDynReg8_RW< TUart, KOffset > iMem;
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typedef TBitField<0,8> Value;
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};
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struct LSR
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{
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static const TInt KOffset = 0x14;
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static TDynReg8_R< TUart, KOffset > iMem;
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typedef TSingleBitField<7> RX_FIFO_STS;
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typedef TSingleBitField<6> TX_SR_E;
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typedef TSingleBitField<5> TX_FIFO_E;
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typedef TSingleBitField<4> RX_BI;
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typedef TSingleBitField<3> RX_FE;
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typedef TSingleBitField<2> RX_PE;
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typedef TSingleBitField<1> RX_OE;
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typedef TSingleBitField<0> RX_FIFO_E;
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};
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struct XON2_ADDR2
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{
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static const TInt KOffset = 0x14;
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static TDynReg8_RW< TUart, KOffset > iMem;
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typedef TBitField<0,8> Value;
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};
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struct XOFF1
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{
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static const TInt KOffset = 0x18;
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static TDynReg8_RW< TUart, KOffset > iMem;
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typedef TBitField<0,8> Value;
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};
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struct TCR
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{
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static const TInt KOffset = 0x18;
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static TDynReg8_RW< TUart, KOffset > iMem;
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typedef TBitField<4,4> RX_FIFO_TRIG_START;
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typedef TBitField<0,4> RX_FIFO_TRIG_HALT;
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};
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struct MSR
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{
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static const TInt KOffset = 0x18;
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static TDynReg8_R< TUart, KOffset > iMem;
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typedef TSingleBitField<7> NCD_STS;
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typedef TSingleBitField<6> NRI_STS;
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typedef TSingleBitField<5> NDSR_STS;
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typedef TSingleBitField<4> NCTS_STS;
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typedef TSingleBitField<3> DCD_STS;
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typedef TSingleBitField<2> RI_STS;
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typedef TSingleBitField<1> DSR_STS;
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typedef TSingleBitField<0> CTS_STS;
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};
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struct SPR
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{
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static const TInt KOffset = 0x1c;
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static TDynReg8_RW< TUart, KOffset > iMem;
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typedef TBitField<0,8> SPR_WORD;
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};
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struct XOFF2
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{
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static const TInt KOffset = 0x1c;
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static TDynReg8_RW< TUart, KOffset > iMem;
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typedef TBitField<0,8> Value;
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};
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struct TLR
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{
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static const TInt KOffset = 0x1c;
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static TDynReg8_RW< TUart, KOffset > iMem;
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typedef TBitField<4,4> RX_FIFO_TRIG_DMA;
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typedef TBitField<0,4> TX_FIFO_TRIG_DMA;
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};
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struct MDR1
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{
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static const TInt KOffset = 0x20;
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static TDynReg8_RW< TUart, KOffset > iMem;
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typedef TSingleBitField<7> FRAME_END_MODE;
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typedef TSingleBitField<6> SIP_MODE;
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typedef TSingleBitField<5> SCT;
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typedef TSingleBitField<4> SET_TXIR;
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|
347 |
typedef TSingleBitField<3> IR_SLEEP;
|
|
|
348 |
struct MODE_SELECT : public TBitField<0,3>
|
|
|
349 |
{
|
|
|
350 |
enum TMode
|
|
|
351 |
{
|
|
|
352 |
EUart16x = 0,
|
|
|
353 |
ESIR = 1,
|
|
|
354 |
EUart16xAutoBaud = 2,
|
|
|
355 |
EUart13x = 3,
|
|
|
356 |
EMIR = 4,
|
|
|
357 |
EFIR = 5,
|
|
|
358 |
ECIR = 6,
|
|
|
359 |
EDisable = 7
|
|
|
360 |
};
|
|
|
361 |
};
|
|
|
362 |
};
|
|
|
363 |
|
|
|
364 |
struct MDR2
|
|
|
365 |
{
|
|
|
366 |
static const TInt KOffset = 0x24;
|
|
|
367 |
static TDynReg8_RW< TUart, KOffset > iMem;
|
|
|
368 |
typedef TSingleBitField<6> IRRXINVERT;
|
|
|
369 |
struct CIR_PULSE_MODE : public TBitField<4,2>
|
|
|
370 |
{
|
|
|
371 |
enum TConstants
|
|
|
372 |
{
|
|
|
373 |
EPw3 = 0 << KShift,
|
|
|
374 |
EPw4 = 1 << KShift,
|
|
|
375 |
EPw5 = 2 << KShift,
|
|
|
376 |
EPw6 = 3 << KShift
|
|
|
377 |
};
|
|
|
378 |
};
|
|
|
379 |
typedef TSingleBitField<3> UART_PULSE;
|
|
|
380 |
struct STS_FIFO_TRIG : public TBitField<1,2>
|
|
|
381 |
{
|
|
|
382 |
enum TConstants
|
|
|
383 |
{
|
|
|
384 |
E1Entry = 0 << KShift,
|
|
|
385 |
E4Entry = 1 << KShift,
|
|
|
386 |
E7Entry = 2 << KShift,
|
|
|
387 |
E8Entry = 3 << KShift
|
|
|
388 |
};
|
|
|
389 |
};
|
|
|
390 |
typedef TSingleBitField<0> IRTX_UNDERRUN;
|
|
|
391 |
};
|
|
|
392 |
|
|
|
393 |
struct TXFLL
|
|
|
394 |
{
|
|
|
395 |
static const TInt KOffset = 0x28;
|
|
|
396 |
static TDynReg8_W< TUart, KOffset > iMem;
|
|
|
397 |
typedef TBitField<0,8> TX_FLL;
|
|
|
398 |
};
|
|
|
399 |
|
|
|
400 |
struct SFLSR
|
|
|
401 |
{
|
|
|
402 |
static const TInt KOffset = 0x28;
|
|
|
403 |
static TDynReg8_R< TUart, KOffset > iMem;
|
|
|
404 |
typedef TSingleBitField<4> OE_ERROR;
|
|
|
405 |
typedef TSingleBitField<3> FTL_ERROR;
|
|
|
406 |
typedef TSingleBitField<2> ABORT_DETECT;
|
|
|
407 |
typedef TSingleBitField<1> CRC_ERROR;
|
|
|
408 |
};
|
|
|
409 |
|
|
|
410 |
struct RESUME
|
|
|
411 |
{
|
|
|
412 |
static const TInt KOffset = 0x2c;
|
|
|
413 |
static TDynReg8_R< TUart, KOffset > iMem;
|
|
|
414 |
typedef TBitField<0,8> Value;
|
|
|
415 |
};
|
|
|
416 |
|
|
|
417 |
struct TXFLH
|
|
|
418 |
{
|
|
|
419 |
static const TInt KOffset = 0x2c;
|
|
|
420 |
static TDynReg8_W< TUart, KOffset > iMem;
|
|
|
421 |
typedef TBitField<0,5> TX_FLH;
|
|
|
422 |
};
|
|
|
423 |
|
|
|
424 |
struct RXFLL
|
|
|
425 |
{
|
|
|
426 |
static const TInt KOffset = 0x30;
|
|
|
427 |
static TDynReg8_W< TUart, KOffset > iMem;
|
|
|
428 |
typedef TBitField<0,8> RX_FLL;
|
|
|
429 |
};
|
|
|
430 |
|
|
|
431 |
struct SFREGL
|
|
|
432 |
{
|
|
|
433 |
static const TInt KOffset = 0x30;
|
|
|
434 |
static TDynReg8_R< TUart, KOffset > iMem;
|
|
|
435 |
typedef TBitField<0,8> Value;
|
|
|
436 |
};
|
|
|
437 |
|
|
|
438 |
struct SFREGH
|
|
|
439 |
{
|
|
|
440 |
static const TInt KOffset = 0x34;
|
|
|
441 |
static TDynReg8_R< TUart, KOffset > iMem;
|
|
|
442 |
typedef TBitField<0,4> Value;
|
|
|
443 |
};
|
|
|
444 |
|
|
|
445 |
struct RXFLH
|
|
|
446 |
{
|
|
|
447 |
static const TInt KOffset = 0x34;
|
|
|
448 |
static TDynReg8_W< TUart, KOffset > iMem;
|
|
|
449 |
typedef TBitField<0,4> RX_FLH;
|
|
|
450 |
};
|
|
|
451 |
|
|
|
452 |
struct BLR
|
|
|
453 |
{
|
|
|
454 |
typedef TSingleBitField<7> STS_FIFO_RESET;
|
|
|
455 |
typedef TSingleBitField<6> XBOF_TYPE;
|
|
|
456 |
};
|
|
|
457 |
|
|
|
458 |
struct UASR
|
|
|
459 |
{
|
|
|
460 |
static const TInt KOffset = 0x38;
|
|
|
461 |
static TDynReg8_R< TUart, KOffset > iMem;
|
|
|
462 |
struct PARITY_TYPE : public TBitField<6,2>
|
|
|
463 |
{
|
|
|
464 |
enum TConstants
|
|
|
465 |
{
|
|
|
466 |
ENone = 0 << KShift,
|
|
|
467 |
ESpace = 1 << KShift,
|
|
|
468 |
EEven = 2 << KShift,
|
|
|
469 |
EOdd = 3 << KShift
|
|
|
470 |
};
|
|
|
471 |
};
|
|
|
472 |
struct BIT_BY_CHAR : public TSingleBitField<5>
|
|
|
473 |
{
|
|
|
474 |
enum TConstants
|
|
|
475 |
{
|
|
|
476 |
E7Bit = 0 << KShift,
|
|
|
477 |
E8Bit = 1 << KShift
|
|
|
478 |
};
|
|
|
479 |
};
|
|
|
480 |
struct SPEED : public TBitField<0,5>
|
|
|
481 |
{
|
|
|
482 |
enum TBaud
|
|
|
483 |
{
|
|
|
484 |
EUnknown = 0,
|
|
|
485 |
E115200 = 1,
|
|
|
486 |
E57600 = 2,
|
|
|
487 |
E38400 = 3,
|
|
|
488 |
E28800 = 4,
|
|
|
489 |
E19200 = 5,
|
|
|
490 |
E14400 = 6,
|
|
|
491 |
E9600 = 7,
|
|
|
492 |
E4800 = 8,
|
|
|
493 |
E4800_2 = 9,
|
|
|
494 |
E1200 = 10
|
|
|
495 |
};
|
|
|
496 |
};
|
|
|
497 |
};
|
|
|
498 |
|
|
|
499 |
struct ACREG
|
|
|
500 |
{
|
|
|
501 |
static const TInt KOffset = 0x3c;
|
|
|
502 |
static TDynReg8_RW< TUart, KOffset > iMem;
|
|
|
503 |
typedef TSingleBitField<7> PULSE_TYPE;
|
|
|
504 |
typedef TSingleBitField<6> SID_MOD;
|
|
|
505 |
typedef TSingleBitField<5> DIS_IR_RX;
|
|
|
506 |
typedef TSingleBitField<4> DIS_TX_UNDERRUN;
|
|
|
507 |
typedef TSingleBitField<3> SEND_SIP;
|
|
|
508 |
typedef TSingleBitField<2> SCTX_EN;
|
|
|
509 |
typedef TSingleBitField<1> ABORT_EN;
|
|
|
510 |
typedef TSingleBitField<0> EOT_EN;
|
|
|
511 |
};
|
|
|
512 |
|
|
|
513 |
struct SCR
|
|
|
514 |
{
|
|
|
515 |
static const TInt KOffset = 0x40;
|
|
|
516 |
static TDynReg8_RW< TUart, KOffset > iMem;
|
|
|
517 |
typedef TSingleBitField<7> RX_TRIG_GRANU1;
|
|
|
518 |
typedef TSingleBitField<6> TX_TRIG_GRANU1;
|
|
|
519 |
typedef TSingleBitField<4> RX_CTS_WU_EN;
|
|
|
520 |
typedef TSingleBitField<3> TX_EMPTY_CTL_IT;
|
|
|
521 |
typedef TBitField<1,2> DMA_MODE2;
|
|
|
522 |
typedef TSingleBitField<0> DMA_MODE_CTL;
|
|
|
523 |
};
|
|
|
524 |
|
|
|
525 |
struct SSR
|
|
|
526 |
{
|
|
|
527 |
static const TInt KOffset = 0x44;
|
|
|
528 |
static TDynReg8_R< TUart, KOffset > iMem;
|
|
|
529 |
typedef TSingleBitField<1> RX_CTS_WU_STS;
|
|
|
530 |
typedef TSingleBitField<0> TX_FIFO_FULL;
|
|
|
531 |
};
|
|
|
532 |
|
|
|
533 |
struct EBLR
|
|
|
534 |
{
|
|
|
535 |
static const TInt KOffset = 0x48;
|
|
|
536 |
static TDynReg8_RW< TUart, KOffset > iMem;
|
|
|
537 |
typedef TBitField<0,8> Value;
|
|
|
538 |
};
|
|
|
539 |
|
|
|
540 |
struct SYSC
|
|
|
541 |
{
|
|
|
542 |
static const TInt KOffset = 0x54;
|
|
|
543 |
static TDynReg8_RW< TUart, KOffset > iMem;
|
|
|
544 |
struct IDLE_MODE : public TBitField<3,2>
|
|
|
545 |
{
|
|
|
546 |
enum TMode
|
|
|
547 |
{
|
|
|
548 |
EForceIdle = 0 << KShift,
|
|
|
549 |
ENoIdle = 1 << KShift,
|
|
|
550 |
ESmartIdle = 2 << KShift
|
|
|
551 |
};
|
|
|
552 |
};
|
|
|
553 |
typedef TSingleBitField<2> ENAWAKEUP;
|
|
|
554 |
typedef TSingleBitField<1> SOFTRESET;
|
|
|
555 |
typedef TSingleBitField<0> AUTOIDLE;
|
|
|
556 |
};
|
|
|
557 |
|
|
|
558 |
struct SYSS
|
|
|
559 |
{
|
|
|
560 |
static const TInt KOffset = 0x58;
|
|
|
561 |
static TDynReg8_R< TUart, KOffset > iMem;
|
|
|
562 |
typedef TSingleBitField<0> RESETDONE;
|
|
|
563 |
};
|
|
|
564 |
|
|
|
565 |
struct WER
|
|
|
566 |
{
|
|
|
567 |
static const TInt KOffset = 0x5c;
|
|
|
568 |
static TDynReg8_RW< TUart, KOffset > iMem;
|
|
|
569 |
typedef TSingleBitField<6> EVENT_6_RLS_INTERRUPT;
|
|
|
570 |
typedef TSingleBitField<5> EVENT_5_RHR_INTERRUPT;
|
|
|
571 |
typedef TSingleBitField<4> EVENT_4_RX_ACTIVITY;
|
|
|
572 |
typedef TSingleBitField<2> EVENT_2_RI_ACTIVITY;
|
|
|
573 |
typedef TSingleBitField<0> EVENT_0_CTS_ACTIVITY;
|
|
|
574 |
};
|
|
|
575 |
|
|
|
576 |
struct CFPS
|
|
|
577 |
{
|
|
|
578 |
static const TInt KOffset = 0x60;
|
|
|
579 |
static TDynReg8_RW< TUart, KOffset > iMem;
|
|
|
580 |
typedef TBitField<0,8> Value;
|
|
|
581 |
};
|
|
|
582 |
|
|
|
583 |
|
|
|
584 |
class TUart
|
|
|
585 |
{
|
|
|
586 |
public:
|
|
|
587 |
enum TBaud
|
|
|
588 |
{
|
|
|
589 |
E1200,
|
|
|
590 |
E2400,
|
|
|
591 |
E4800,
|
|
|
592 |
E9600,
|
|
|
593 |
E14400,
|
|
|
594 |
E19200,
|
|
|
595 |
E28800,
|
|
|
596 |
E38400,
|
|
|
597 |
E57600,
|
|
|
598 |
E115200,
|
|
|
599 |
E230400,
|
|
|
600 |
E460800,
|
|
|
601 |
E921600,
|
|
|
602 |
E1843000,
|
|
|
603 |
E3688400,
|
|
|
604 |
E4000000, // FIR
|
|
|
605 |
|
|
|
606 |
KSupportedBaudCount
|
|
|
607 |
};
|
|
|
608 |
|
|
|
609 |
enum TParity
|
|
|
610 |
{
|
|
|
611 |
ENone,
|
|
|
612 |
EOdd,
|
|
|
613 |
EEven,
|
|
|
614 |
EMark,
|
|
|
615 |
ESpace
|
|
|
616 |
};
|
|
|
617 |
|
|
|
618 |
enum TDataBits
|
|
|
619 |
{
|
|
|
620 |
E5Data = ::Omap3530Uart::LCR::CHAR_LENGTH::E5Bits,
|
|
|
621 |
E6Data = ::Omap3530Uart::LCR::CHAR_LENGTH::E6Bits,
|
|
|
622 |
E7Data = ::Omap3530Uart::LCR::CHAR_LENGTH::E7Bits,
|
|
|
623 |
E8Data = ::Omap3530Uart::LCR::CHAR_LENGTH::E8Bits,
|
|
|
624 |
};
|
|
|
625 |
|
|
|
626 |
enum TStopBits
|
|
|
627 |
{
|
|
|
628 |
E1Stop = ::Omap3530Uart::LCR::NB_STOP::E1Stop,
|
|
|
629 |
E1_5Stop = ::Omap3530Uart::LCR::NB_STOP::E1_5Stop,
|
|
|
630 |
E2Stop = ::Omap3530Uart::LCR::NB_STOP::E2Stop,
|
|
|
631 |
};
|
|
|
632 |
|
|
|
633 |
enum TUartMode
|
|
|
634 |
{
|
|
|
635 |
EUart,
|
|
|
636 |
EUartAutoBaud,
|
|
|
637 |
ESIR,
|
|
|
638 |
EMIR,
|
|
|
639 |
EFIR,
|
|
|
640 |
ECIR,
|
|
|
641 |
|
|
|
642 |
KSupportedUartModes
|
|
|
643 |
};
|
|
|
644 |
|
|
|
645 |
enum TFifoTrigger
|
|
|
646 |
{
|
|
|
647 |
ETrigger8,
|
|
|
648 |
ETrigger16,
|
|
|
649 |
ETrigger32,
|
|
|
650 |
ETrigger56,
|
|
|
651 |
ETrigger60,
|
|
|
652 |
ETriggerUnchanged
|
|
|
653 |
};
|
|
|
654 |
|
|
|
655 |
enum TEnableState
|
|
|
656 |
{
|
|
|
657 |
EDisabled,
|
|
|
658 |
EEnabled
|
|
|
659 |
};
|
|
|
660 |
|
|
|
661 |
enum TInterrupt
|
|
|
662 |
{
|
|
|
663 |
EIntRhr = 0,
|
|
|
664 |
EIntThr = 1,
|
|
|
665 |
EIntLineStatus = 2,
|
|
|
666 |
EIntModemStatus = 3,
|
|
|
667 |
EIntXoff = 5,
|
|
|
668 |
EIntRts = 6,
|
|
|
669 |
EIntCts = 7
|
|
|
670 |
};
|
|
|
671 |
|
|
|
672 |
public:
|
|
|
673 |
inline TUart( const TUartNumber aUartNumber )
|
|
|
674 |
: iBase( (aUartNumber == EUart0 ) ? TUartTraits<EUart0>::KBaseAddress
|
|
|
675 |
: (aUartNumber == EUart1 ) ? TUartTraits<EUart1>::KBaseAddress
|
|
|
676 |
: (aUartNumber == EUart2 ) ? TUartTraits<EUart2>::KBaseAddress
|
|
|
677 |
: 0 ),
|
|
|
678 |
iUartNumber( aUartNumber )
|
|
|
679 |
{}
|
|
|
680 |
|
|
|
681 |
FORCE_INLINE TLinAddr Base() const
|
|
|
682 |
{ return iBase; }
|
|
|
683 |
|
|
|
684 |
IMPORT_C TInt InterruptId() const;
|
|
|
685 |
|
|
|
686 |
IMPORT_C Prcm::TClock PrcmInterfaceClk() const;
|
|
|
687 |
|
|
|
688 |
IMPORT_C Prcm::TClock PrcmFunctionClk() const;
|
|
|
689 |
|
|
|
690 |
// IMPORT_C TInt PrmInterfaceClk() const;
|
|
|
691 |
|
|
|
692 |
// IMPORT_C TInt PrmFunctionClk() const;
|
|
|
693 |
|
|
|
694 |
/** Reset and initialize the UART
|
|
|
695 |
* On return the UART will be in disable mode */
|
|
|
696 |
IMPORT_C void Init();
|
|
|
697 |
|
|
|
698 |
/** Defines which mode the UART will run in when enabled, but does not configure that mode
|
|
|
699 |
* You must call this before calling SetBaud to ensure that correct baud rate multiplier is used */
|
|
|
700 |
IMPORT_C void DefineMode( const TUartMode aMode );
|
|
|
701 |
|
|
|
702 |
/** Enabled the UART in the defined mode
|
|
|
703 |
* You must call DefineMode() and SetBaud() before calling Enable()
|
|
|
704 |
*/
|
|
|
705 |
IMPORT_C void Enable();
|
|
|
706 |
|
|
|
707 |
/** Disables the UART */
|
|
|
708 |
IMPORT_C void Disable();
|
|
|
709 |
|
|
|
710 |
/** Set the baud rate
|
|
|
711 |
* Do not call this while the UART is enabled
|
|
|
712 |
* You must have previously called DefineMode()
|
|
|
713 |
*/
|
|
|
714 |
IMPORT_C void SetBaud( const TBaud aBaud );
|
|
|
715 |
|
|
|
716 |
/** Set the data length, parity and stop bits */
|
|
|
717 |
IMPORT_C void SetDataFormat( const TDataBits aDataBits, const TStopBits aStopBits, const TParity aParity );
|
|
|
718 |
|
|
|
719 |
/** Setup the FIFO configuration */
|
|
|
720 |
IMPORT_C void EnableFifo( const TEnableState aState, const TFifoTrigger aRxTrigger = ETriggerUnchanged, const TFifoTrigger aTxTrigger = ETriggerUnchanged );
|
|
|
721 |
|
|
|
722 |
/** Enable a particular interrupt source */
|
|
|
723 |
IMPORT_C void EnableInterrupt( const TInterrupt aWhich );
|
|
|
724 |
|
|
|
725 |
/** Disable a particular interrupt source */
|
|
|
726 |
IMPORT_C void DisableInterrupt( const TInterrupt aWhich );
|
|
|
727 |
|
|
|
728 |
/** Disable all interrupts */
|
|
|
729 |
IMPORT_C void DisableAllInterrupts();
|
|
|
730 |
|
|
|
731 |
inline TBool TxFifoFull()
|
|
|
732 |
{ return SSR::iMem.Read(*this) bitand SSR::TX_FIFO_FULL::KMask; }
|
|
|
733 |
|
|
|
734 |
inline TBool TxFifoEmpty()
|
|
|
735 |
{ return LSR::iMem.Read(*this) bitand LSR::TX_FIFO_E::KMask; }
|
|
|
736 |
|
|
|
737 |
inline TBool RxFifoEmpty()
|
|
|
738 |
{ return !(LSR::iMem.Read(*this) bitand LSR::RX_FIFO_E::KMask); }
|
|
|
739 |
|
|
|
740 |
inline void Write( TUint8 aByte )
|
|
|
741 |
{ THR::iMem.Write( *this, aByte ); }
|
|
|
742 |
|
|
|
743 |
inline TUint8 Read()
|
|
|
744 |
{ return RHR::iMem.Read( *this ); }
|
|
|
745 |
|
|
|
746 |
private:
|
|
|
747 |
TUart();
|
|
|
748 |
|
|
|
749 |
public:
|
|
|
750 |
const TLinAddr iBase;
|
|
|
751 |
const TUartNumber iUartNumber : 8;
|
|
|
752 |
TUartMode iMode : 8;
|
|
|
753 |
::Omap3530Uart::MDR1::MODE_SELECT::TMode iTargetMode : 8;
|
|
|
754 |
};
|
|
|
755 |
|
|
|
756 |
|
|
|
757 |
} // Omap3530Uart
|
|
|
758 |
|
|
|
759 |
#endif // ndef __OMAP3530_UART_H__
|
|
|
760 |
|