author | Mike Kinghan <mikek@symbian.org> |
Wed, 17 Nov 2010 11:02:10 +0000 | |
branch | GCC_SURGE |
changeset 110 | c1bfa2b1009b |
parent 28 | cf0489a7a8b1 |
permissions | -rwxr-xr-x |
0 | 1 |
// Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies). |
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// All rights reserved. |
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// This component and the accompanying materials are made available |
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// under the terms of the License "Eclipse Public License v1.0" |
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// which accompanies this distribution, and is available |
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// at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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// |
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// Initial Contributors: |
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// Nokia Corporation - initial contribution. |
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// |
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// Contributors: |
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// |
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// Description: |
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// omap3530/assp/inc/omap3530_hardware_base.h |
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// Linear base addresses for hardware peripherals on the beagle board. |
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// This file is part of the Beagle Base port |
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// |
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#ifndef OMAP3530_HARDWARE_BASE_H__ |
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# define OMAP3530_HARDWARE_BASE_H__ |
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#include <assp.h> // for TPhysAddr, AsspRegister |
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#include <assp/omap3530_assp/omap3530_asspreg.h> |
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namespace TexasInstruments |
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{ |
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namespace Omap3530 |
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{ |
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/** |
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Define constants for the various physical address blocks used on the OMAP3530 |
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*/ |
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enum TPhysicalAddresses |
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{ |
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KKiloByte = 1024, |
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KMegaByte = (1024 * KKiloByte), |
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KL4_Core_PhysicalBase = 0x48000000, |
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KL4_Core_PhysicalSize = (4 * KMegaByte), |
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KL4_Core_PhysicalEnd = (KL4_Core_PhysicalBase + KL4_Core_PhysicalSize), |
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KL4_WakeUp_PhysicalBase = 0x48300000, |
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KL4_WakeUp_PhysicalSize = (256 * KKiloByte ), |
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KL4_WakeUp_PhysicalEnd = (KL4_WakeUp_PhysicalBase + KL4_WakeUp_PhysicalSize), |
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KL4_Per_PhysicalBase = 0x49000000, |
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KL4_Per_PhysicalSize = (1 * KMegaByte), |
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KL4_Per_PhysicalEnd = (KL4_Per_PhysicalBase + KL4_Per_PhysicalSize), |
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KL4_Sgx_PhysicalBase = 0x50000000, |
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KL4_Sgx_PhysicalSize = (64 * KKiloByte), |
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KL4_Sgx_PhysicalEnd = (KL4_Sgx_PhysicalBase + KL4_Sgx_PhysicalSize), |
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KL4_Emu_PhysicalBase = 0x54000000, |
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KL4_Emu_PhysicalSize = (8 * KMegaByte), |
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KL4_Emu_PhysicalEnd = (KL4_Emu_PhysicalBase + KL4_Emu_PhysicalSize), |
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KL3_Control_PhysicalBase = 0x68000000, |
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KL3_Control_PhysicalSize = (1 * KMegaByte), |
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KL3_Control_PhysicalEnd = (KL3_Control_PhysicalBase + KL3_Control_PhysicalSize), |
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KL3_Gpmc_PhysicalBase = 0x6e000000, |
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KL3_Gpmc_PhysicalSize = (1 * KMegaByte), |
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KL3_Gpmc_PhysicalEnd = (KL3_Gpmc_PhysicalBase + KL3_Gpmc_PhysicalSize) |
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} ; |
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/** |
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Define constants for the virtual address mappings used on the OMAP3530 |
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*/ |
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enum TLinearAddresses |
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{ |
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KL4_Core_LinearBase = 0xC6000000, |
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KL4_Core_LinearSize = KL4_Core_PhysicalSize, |
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KL4_Core_LinearEnd = (KL4_Core_LinearBase + KL4_Core_LinearSize), |
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KL4_WakeUp_LinearBase = (KL4_Core_LinearBase + (KL4_WakeUp_PhysicalBase - KL4_Core_PhysicalBase)), |
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KL4_WakeUp_LinearSize = KL4_WakeUp_PhysicalSize, |
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KL4_WakeUp_LinearEnd = (KL4_WakeUp_LinearBase + KL4_WakeUp_LinearSize), |
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KL4_Per_LinearBase = KL4_Core_LinearEnd, |
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KL4_Per_LinearSize = KL4_Per_PhysicalSize, |
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KL4_Per_LinearEnd = (KL4_Per_LinearBase + KL4_Per_LinearSize), |
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KL4_Sgx_LinearBase = KL4_Per_LinearEnd, |
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KL4_Sgx_LinearSize = KL4_Sgx_PhysicalSize, |
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KL4_Sgx_LinearEnd = (KL4_Sgx_LinearBase + KL4_Sgx_LinearSize), |
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KL4_Emu_LinearBase = KL4_Sgx_LinearBase + KMegaByte, |
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KL4_Emu_LinearSize = KL4_Emu_PhysicalSize, |
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KL4_Emu_LinearEnd = (KL4_Emu_LinearBase + KL4_Emu_LinearSize), |
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KL3_Control_LinearBase = KL4_Emu_LinearEnd, |
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KL3_Control_LinearSize = KL3_Control_PhysicalSize, |
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KL3_Control_LinearEnd = (KL3_Control_LinearBase + KL3_Control_LinearSize), |
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KL3_Gpmc_LinearBase = KL3_Control_LinearEnd, |
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KL3_Gpmc_LinearSize = KL3_Gpmc_PhysicalSize, |
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KL3_Gpmc_LinearEnd = (KL3_Gpmc_LinearBase + KL3_Gpmc_LinearSize) |
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} ; |
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/** |
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A template to provide the virtual address of a given physical address. |
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@example |
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@code |
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enum TTimerBaseAddress |
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{ |
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KGPTIMER1_Base = Omap3530HwBase::TVirtual<0x48318000>::Value, |
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} ; |
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*/ |
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template<const TPhysAddr aDdReSs> |
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struct TVirtual |
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{ |
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enum TConstants |
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{ |
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KIsL4Core = ((aDdReSs >= KL4_Core_PhysicalBase) && (aDdReSs < KL4_Core_PhysicalEnd)), |
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KIsL4WakeUp = ((aDdReSs >= KL4_WakeUp_PhysicalBase) && (aDdReSs < KL4_WakeUp_PhysicalEnd)), // Subset of L4Core |
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KIsL4Per = ((aDdReSs >= KL4_Per_PhysicalBase) && (aDdReSs < KL4_Per_PhysicalEnd)), |
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KIsL4Sgx = ((aDdReSs >= KL4_Sgx_PhysicalBase) && (aDdReSs < KL4_Sgx_PhysicalEnd)), |
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KIsL4Emu = ((aDdReSs >= KL4_Emu_PhysicalBase) && (aDdReSs < KL4_Emu_PhysicalEnd)), |
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KIsL3Control = ((aDdReSs >= KL3_Control_PhysicalBase) && (aDdReSs < KL3_Control_PhysicalEnd)), |
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KIsL3Gpmc = ((aDdReSs >= KL3_Gpmc_PhysicalBase) && (aDdReSs < KL3_Gpmc_PhysicalEnd)), |
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KIsConvertable = (KIsL4Core || KIsL4Per || KIsL4Sgx || KIsL4Emu || KIsL3Control || KIsL3Gpmc), |
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KIsMapped = (KIsL4Core || KIsL4Per || KIsL4Sgx || KIsL4Emu || KIsL3Control || KIsL3Gpmc), |
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KOffset = ((KIsL4Core) ? (aDdReSs - KL4_Core_PhysicalBase) |
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: ((KIsL4Per) ? (aDdReSs - KL4_Per_PhysicalBase) |
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: ((KIsL4Sgx) ? (aDdReSs - KL4_Sgx_PhysicalBase) |
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: ((KIsL4Emu) ? (aDdReSs - KL4_Emu_PhysicalBase) |
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: ((KIsL3Control) ? (aDdReSs - KL3_Control_PhysicalBase) |
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: ((KIsL3Gpmc) ? (aDdReSs - KL3_Gpmc_PhysicalBase) |
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: (0))))))), |
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// TODO: Change to give compile time error if address not mapped |
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KLinearBase = ((KIsL4Core) ? (KL4_Core_LinearBase) |
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: ((KIsL4Per) ? (KL4_Per_LinearBase) |
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: ((KIsL4Sgx) ? (KL4_Sgx_LinearBase) |
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: ((KIsL4Emu) ? (KL4_Emu_LinearBase) |
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: ((KIsL3Control) ? (KL3_Control_LinearBase) |
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: ((KIsL3Gpmc) ? (KL3_Gpmc_LinearBase) |
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: (0))))))), |
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/** |
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Returns the Linear address mapping for a specific Physical address |
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*/ |
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Value = (KLinearBase + KOffset) |
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} ; |
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} ; |
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template<const TLinAddr aDdReSs> |
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struct TLinearCheck |
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{ |
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enum TConstants |
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{ |
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KIsL4Core = ((aDdReSs >= KL4_Core_LinearBase) && (aDdReSs < KL4_Core_LinearEnd)), |
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KIsL4Per = ((aDdReSs >= KL4_Per_LinearBase) && (aDdReSs < KL4_Per_LinearEnd)), |
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KIsL4Sgx = ((aDdReSs >= KL4_Sgx_LinearBase) && (aDdReSs < KL4_Sgx_LinearEnd)), |
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KIsL4Emu = ((aDdReSs >= KL4_Emu_LinearBase) && (aDdReSs < KL4_Emu_LinearEnd)), |
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KIsL3Control = ((aDdReSs >= KL3_Control_LinearBase) && (aDdReSs < KL3_Control_LinearBase)), |
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KIsL3Gpmc = ((aDdReSs >= KL3_Gpmc_LinearBase) && (aDdReSs < KL3_Gpmc_LinearBase)), |
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KIsMapped = (KIsL4Core || KIsL4Per || KIsL4Sgx || KIsL4Emu || KIsL3Control || KIsL3Gpmc) |
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} ; |
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} ; |
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# ifdef __MEMMODEL_MULTIPLE__ |
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const TUint KL4_Core = KL4_Core_LinearBase; // KPrimaryIOBase |
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const TUint KL4_Per = KL4_Per_LinearBase; |
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const TUint KSgx = KL4_Sgx_LinearBase; |
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const TUint KL4_Emu = KL4_Emu_LinearBase; |
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const TUint KL3_Control = KL3_Control_LinearBase; |
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const TUint KL3_Gpmc = KL3_Gpmc_LinearBase; |
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//const TUint KIva2_2Ss = KL4_Core + 0x01910000; |
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//const TUint KL3ControlRegisters = KL4_Core + 0x04910000; |
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//const TUint KSmsRegisters = KL4_Core + 0x05910000; |
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//const TUint KSdrcRegisters = KL4_Core + 0x06910000; |
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//const TUint KGpmcRegisters = KL4_Core + 0x07910000; |
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//#elif __MEMMODEL_FLEXIBLE__ |
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// define flexible memery model hw base addresses |
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# else // unknown memery model |
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# error hardware_base.h: Constants may need changing |
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# endif // memory model |
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// Register Access types. |
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typedef TUint32 TRegValue; |
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typedef TUint32 TRegValue32; |
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typedef TUint16 TRegValue16; |
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typedef TUint8 TRegValue8; |
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/** |
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An interface template for read-only registers. |
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*/ |
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template <TLinAddr aDdReSs> |
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class TReg32_R |
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{ |
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public : |
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static inline TRegValue Read() |
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{ |
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__ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ; |
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return AsspRegister::Read32(aDdReSs) ; |
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} |
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} ; |
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template <TLinAddr aDdReSs> |
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class TReg16_R |
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{ |
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public : |
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static inline TRegValue16 Read() |
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{ |
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__ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ; |
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return AsspRegister::Read16(aDdReSs) ; |
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} |
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} ; |
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template <TLinAddr aDdReSs> |
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class TReg8_R |
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{ |
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public : |
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static inline TRegValue8 Read() |
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{ |
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__ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ; |
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return AsspRegister::Read8(aDdReSs) ; |
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} |
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} ; |
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/** |
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An interface template for read-write registers. |
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*/ |
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template <TLinAddr aDdReSs> |
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class TReg32_RW : public TReg32_R<aDdReSs> |
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{ |
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public : |
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static inline void Write(const TRegValue aValue) |
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{ |
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__ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ; |
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AsspRegister::Write32(aDdReSs, aValue) ; |
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} |
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static inline void Modify(const TRegValue aClearMask, const TRegValue aSetMask) |
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{ |
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__ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ; |
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AsspRegister::Modify32(aDdReSs, aClearMask, aSetMask) ; |
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} |
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} ; |
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template <TLinAddr aDdReSs> |
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class TReg16_RW : public TReg16_R<aDdReSs> |
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{ |
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public : |
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static inline void Write(const TRegValue16 aValue) |
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{ |
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__ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ; |
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AsspRegister::Write16(aDdReSs, aValue) ; |
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} |
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static inline void Modify(const TRegValue16 aClearMask, const TRegValue16 aSetMask) |
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{ |
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__ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ; |
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AsspRegister::Modify16(aDdReSs, aClearMask, aSetMask) ; |
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} |
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} ; |
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template <TLinAddr aDdReSs> |
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class TReg8_RW : public TReg8_R<aDdReSs> |
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{ |
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public : |
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static inline void Write(const TRegValue8 aValue) |
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{ |
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__ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ; |
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AsspRegister::Write8(aDdReSs, aValue) ; |
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} |
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static inline void Modify(const TRegValue8 aClearMask, const TRegValue8 aSetMask) |
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{ |
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__ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ; |
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AsspRegister::Modify8(aDdReSs, aClearMask, aSetMask) ; |
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} |
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} ; |
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||
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/** |
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An interface template for write-only registers. |
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*/ |
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template <TLinAddr aDdReSs> |
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class TReg32_W |
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{ |
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public : |
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static inline void Write(const TRegValue aValue) |
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{ |
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__ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ; |
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AsspRegister::Write32(aDdReSs, aValue) ; |
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} |
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} ; |
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template <TLinAddr aDdReSs> |
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class TReg16_W |
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{ |
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public : |
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static inline void Write(const TRegValue16 aValue) |
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{ |
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__ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ; |
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AsspRegister::Write16(aDdReSs, aValue) ; |
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} |
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} ; |
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template <TLinAddr aDdReSs> |
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class TReg8_W |
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{ |
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public : |
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static inline void Write(const TRegValue8 aValue) |
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{ |
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__ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ; |
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AsspRegister::Write8(aDdReSs, aValue) ; |
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} |
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} ; |
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/** Class for registers that have dynamic base address */ |
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template <class T, TUint OfFsEt> |
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class TDynReg8_R |
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{ |
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public : |
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static inline TRegValue8 Read( const T& aOwner ) |
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{ |
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return AsspRegister::Read8( aOwner.Base() + OfFsEt ) ; |
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} |
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} ; |
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template <class T, TUint OfFsEt> |
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class TDynReg16_R |
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{ |
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public : |
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static inline TRegValue16 Read( const T& aOwner ) |
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{ |
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return AsspRegister::Read16( aOwner.Base() + OfFsEt ) ; |
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} |
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} ; |
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template <class T, TUint OfFsEt> |
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class TDynReg32_R |
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{ |
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public : |
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static inline TRegValue32 Read( const T& aOwner ) |
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{ |
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return AsspRegister::Read32( aOwner.Base() + OfFsEt ) ; |
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} |
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} ; |
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template <class T, TUint OfFsEt> |
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class TDynReg8_RW : public TDynReg8_R<T, OfFsEt> |
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{ |
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public : |
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static inline void Write( T& aOwner, const TRegValue8 aValue) |
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{ |
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AsspRegister::Write8( aOwner.Base() + OfFsEt, aValue) ; |
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} |
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static inline void Modify( T& aOwner, const TRegValue8 aClearMask, const TRegValue8 aSetMask) |
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{ |
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AsspRegister::Modify8( aOwner.Base() + OfFsEt, aClearMask, aSetMask) ; |
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} |
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} ; |
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template <class T, TUint OfFsEt> |
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class TDynReg16_RW : public TDynReg16_R<T, OfFsEt> |
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{ |
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public : |
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static inline void Write( T& aOwner, const TRegValue16 aValue) |
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{ |
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AsspRegister::Write16( aOwner.Base() + OfFsEt, aValue) ; |
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} |
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static inline void Modify( T& aOwner, const TRegValue16 aClearMask, const TRegValue16 aSetMask) |
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{ |
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AsspRegister::Modify16( aOwner.Base() + OfFsEt, aClearMask, aSetMask) ; |
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} |
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} ; |
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template <class T, TUint OfFsEt> |
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class TDynReg32_RW : public TDynReg32_R<T, OfFsEt> |
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{ |
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public : |
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static inline void Write( T& aOwner, const TRegValue32 aValue) |
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{ |
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AsspRegister::Write32( aOwner.Base() + OfFsEt, aValue) ; |
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} |
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static inline void Modify( T& aOwner, const TRegValue32 aClearMask, const TRegValue32 aSetMask) |
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{ |
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AsspRegister::Modify32( aOwner.Base() + OfFsEt, aClearMask, aSetMask) ; |
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} |
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} ; |
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template <class T, TUint OfFsEt> |
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class TDynReg8_W |
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{ |
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public : |
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static inline void Write( T& aOwner, const TRegValue8 aValue) |
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{ |
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AsspRegister::Write8( aOwner.Base() + OfFsEt, aValue) ; |
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} |
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393 |
static inline void Modify( T& aOwner, const TRegValue8 aClearMask, const TRegValue8 aSetMask) |
|
394 |
{ |
|
395 |
AsspRegister::Modify8( aOwner.Base() + OfFsEt, aClearMask, aSetMask) ; |
|
396 |
} |
|
397 |
} ; |
|
398 |
||
399 |
template <class T, TUint OfFsEt> |
|
400 |
class TDynReg16_W |
|
401 |
{ |
|
402 |
public : |
|
403 |
static inline void Write( T& aOwner, const TRegValue16 aValue) |
|
404 |
{ |
|
405 |
AsspRegister::Write16( aOwner.Base() + OfFsEt, aValue) ; |
|
406 |
} |
|
407 |
static inline void Modify( T& aOwner, const TRegValue16 aClearMask, const TRegValue16 aSetMask) |
|
408 |
{ |
|
409 |
AsspRegister::Modify16( aOwner.Base() + OfFsEt, aClearMask, aSetMask) ; |
|
410 |
} |
|
411 |
} ; |
|
412 |
||
413 |
template <class T, TUint OfFsEt> |
|
414 |
class TDynReg32_W |
|
415 |
{ |
|
416 |
public : |
|
417 |
static inline void Write( T& aOwner, const TRegValue32 aValue) |
|
418 |
{ |
|
419 |
AsspRegister::Write32( aOwner.Base() + OfFsEt, aValue) ; |
|
420 |
} |
|
421 |
static inline void Modify( T& aOwner, const TRegValue32 aClearMask, const TRegValue32 aSetMask) |
|
422 |
{ |
|
423 |
AsspRegister::Modify32( aOwner.Base() + OfFsEt, aClearMask, aSetMask) ; |
|
424 |
} |
|
425 |
} ; |
|
426 |
||
427 |
/** |
|
428 |
An Null class for when no register access is required. |
|
429 |
*/ |
|
430 |
class TNull_Reg |
|
431 |
{ |
|
432 |
public : |
|
433 |
static inline TRegValue Read() |
|
434 |
{ |
|
435 |
return 0 ; |
|
436 |
} |
|
437 |
static inline void Write(const TRegValue) |
|
438 |
{ |
|
439 |
} |
|
440 |
static inline void Modify(const TRegValue, const TRegValue) |
|
441 |
{ |
|
442 |
} |
|
443 |
} ; |
|
444 |
||
445 |
template <int aBiTpOsItIoN> |
|
446 |
class TBit |
|
447 |
{ |
|
448 |
public : |
|
449 |
enum TConstants |
|
450 |
{ |
|
451 |
KValue = (1 << aBiTpOsItIoN) |
|
452 |
} ; |
|
453 |
} ; |
|
454 |
||
455 |
template <int aBiTpOsItIoN, int aBiTwIdTh> |
|
456 |
class TBitFieldBase |
|
457 |
{ |
|
458 |
public : |
|
459 |
enum TConstants |
|
460 |
{ |
|
461 |
KShift = aBiTpOsItIoN, |
|
462 |
KValueMask = (TBit<aBiTwIdTh>::KValue - 1), |
|
463 |
KFieldMask = (KValueMask << KShift), |
|
464 |
KValueMax = KValueMask |
|
465 |
} ; |
|
466 |
} ; |
|
467 |
||
468 |
template <int aBiTpOsItIoN, int aBiTwIdTh, int aVaLuE> |
|
469 |
class TBitFieldValue : public TBitFieldBase<aBiTpOsItIoN, aBiTwIdTh> |
|
470 |
{ |
|
471 |
public : |
|
472 |
using TBitFieldBase<aBiTpOsItIoN, aBiTwIdTh>::KShift ; |
|
473 |
using TBitFieldBase<aBiTpOsItIoN, aBiTwIdTh>::KValueMask ; |
|
474 |
using TBitFieldBase<aBiTpOsItIoN, aBiTwIdTh>::KFieldMask ; |
|
475 |
using TBitFieldBase<aBiTpOsItIoN, aBiTwIdTh>::KValueMax ; |
|
476 |
||
477 |
enum TValues |
|
478 |
{ |
|
479 |
KValue = ((KValueMask & aVaLuE) << KShift) |
|
480 |
} ; |
|
481 |
} ; |
|
482 |
||
483 |
template <int aBiTpOsItIoN, int aBiTwIdTh> |
|
484 |
class TBitField : public TBitFieldBase<aBiTpOsItIoN, aBiTwIdTh> |
|
485 |
{ |
|
28
cf0489a7a8b1
Bug 1683 - GCC-E compilation error in beagleboard (783) (accessibility)
George Norton <>
parents:
0
diff
changeset
|
486 |
public : |
0 | 487 |
using TBitFieldBase<aBiTpOsItIoN, aBiTwIdTh>::KShift ; |
488 |
using TBitFieldBase<aBiTpOsItIoN, aBiTwIdTh>::KValueMask ; |
|
489 |
using TBitFieldBase<aBiTpOsItIoN, aBiTwIdTh>::KFieldMask ; |
|
490 |
using TBitFieldBase<aBiTpOsItIoN, aBiTwIdTh>::KValueMax ; |
|
28
cf0489a7a8b1
Bug 1683 - GCC-E compilation error in beagleboard (783) (accessibility)
George Norton <>
parents:
0
diff
changeset
|
491 |
|
0 | 492 |
template <int aVaLuE> |
493 |
class TConstVal : public TBitFieldValue<aBiTpOsItIoN, aBiTwIdTh, aVaLuE> |
|
494 |
{ |
|
495 |
public : |
|
496 |
using TBitFieldValue<aBiTpOsItIoN, aBiTwIdTh, aVaLuE>::KValue ; |
|
497 |
} ; |
|
498 |
||
499 |
inline TBitField(const TRegValue aValue) |
|
500 |
: iValue((KValueMask & aValue) << KShift) {} |
|
501 |
||
502 |
inline TBitField(const TRegValue * aValuePtr) |
|
503 |
: iValue(KFieldMask & *aValuePtr) {} |
|
504 |
||
505 |
template <TLinAddr aDdReSs> |
|
506 |
inline TBitField(const TReg32_R<aDdReSs>& aReg) |
|
507 |
: iValue(KFieldMask & aReg.Read()) {} |
|
508 |
||
509 |
inline TRegValue Value() const {return (KValueMask & (iValue >> KShift)) ;} |
|
510 |
||
511 |
inline TRegValue RegField() const {return (iValue) ;} |
|
512 |
||
513 |
private : |
|
514 |
TRegValue iValue ; |
|
515 |
} ; |
|
516 |
||
517 |
template <int aBiTpOsItIoN> |
|
518 |
class TSingleBitField : public TBitField<aBiTpOsItIoN, 1> |
|
519 |
{ |
|
520 |
public : |
|
521 |
enum TConstants |
|
522 |
{ |
|
523 |
KOff = 0, |
|
524 |
KOn = (1 << aBiTpOsItIoN), |
|
525 |
KClear = KOff, |
|
526 |
KSet = KOn, |
|
527 |
KMask = KOn, |
|
528 |
} ; |
|
529 |
} ; |
|
530 |
||
531 |
} ; // namespace Omap3530 |
|
532 |
||
533 |
} ; // namespace TexasInstruments |
|
534 |
||
535 |
||
536 |
namespace TI = TexasInstruments ; |
|
537 |
||
538 |
namespace OMAP3530 = TexasInstruments::Omap3530 ; |
|
539 |
||
540 |
namespace Omap3530HwBase = TexasInstruments::Omap3530 ; |
|
541 |
||
542 |
// **** TEST CODE **** |
|
543 |
//# define HEADER_OMAP3530_HARDWARE_BASE_H_DO_COMPILE_TIME_CHECK_TESTS 1 |
|
544 |
# ifdef HEADER_OMAP3530_HARDWARE_BASE_H_DO_COMPILE_TIME_CHECK_TESTS |
|
545 |
inline void CompileTimeChecks(void) |
|
546 |
{ |
|
547 |
__ASSERT_COMPILE((Omap3530HwBase::TVirtual<0x48318000>::KIsL4Core)) ; |
|
548 |
__ASSERT_COMPILE((TI::Omap3530::TVirtual<0x48318000>::KIsL4WakeUp)) ; |
|
549 |
__ASSERT_COMPILE((!Omap3530HwBase::TVirtual<0x48318000>::KIsL4Emu)) ; |
|
550 |
__ASSERT_COMPILE((!Omap3530HwBase::TVirtual<0x0000FFFF>::KIsConvertable)) ; |
|
551 |
__ASSERT_COMPILE((Omap3530HwBase::TLinearCheck< Omap3530HwBase::TVirtual<0x48318000>::Value >::KIsMapped)) ; |
|
552 |
__ASSERT_COMPILE((!Omap3530HwBase::TLinearCheck< Omap3530HwBase::TVirtual<0x0000FFFF>::Value >::KIsMapped)) ; |
|
553 |
const TLinAddr mapped(Omap3530HwBase::TVirtual<0x48318000>::Value) ; |
|
554 |
const TLinAddr unmapped(Omap3530HwBase::TVirtual<0x0000FFFF>::Value) ; |
|
555 |
__ASSERT_COMPILE((Omap3530HwBase::TLinearCheck< mapped >::KIsMapped)) ; |
|
556 |
__ASSERT_COMPILE((!Omap3530HwBase::TLinearCheck< unmapped >::KIsMapped)) ; |
|
557 |
__ASSERT_COMPILE((0)) ; // Prove that testing is happening |
|
558 |
} |
|
559 |
# endif |
|
560 |
||
561 |
const TUint KSetNone = 0; |
|
562 |
const TUint KSetAll = 0xffffffff; |
|
563 |
const TUint KClearNone = 0; |
|
564 |
const TUint KClearAll = 0xffffffff; |
|
565 |
const TUint KHOmapClkULPD48Mhz = 48000000; |
|
566 |
||
567 |
#endif // !OMAP3530_HARDWARE_BASE_H__ |
|
568 |
||
569 |
||
570 |