/* Cypress West Bridge API header file (cyasprotocol.h)

 ## ===========================

 ##

 ##  Copyright Cypress Semiconductor Corporation, 2006-2009,

 ##  All Rights Reserved

 ##  UNPUBLISHED, LICENSED SOFTWARE.

 ##

 ##  CONFIDENTIAL AND PROPRIETARY INFORMATION

 ##  WHICH IS THE PROPERTY OF CYPRESS.

 ##

 ##  Use of this file is governed

 ##  by the license agreement included in the file

 ##

 ##     <install>/license/license.txt

 ##

 ##  where <install> is the Cypress software

 ##  installation root directory path.

 ##

 ## ===========================

*/

#ifndef _INCLUDED_CYASPROTOCOL_H_

#define _INCLUDED_CYASPROTOCOL_H_

/*

 * Constants defining the per context buffer sizes

 */

#ifndef __doxygen__

#define CY_CTX_GEN_MAX_DATA_SIZE  (8)

#define CY_CTX_RES_MAX_DATA_SIZE  (8)

#define CY_CTX_STR_MAX_DATA_SIZE  (64)

#define CY_CTX_USB_MAX_DATA_SIZE  (130 + 23)

#define CY_CTX_TUR_MAX_DATA_SIZE  (12)

#endif

/* Summary

   This response indicates a command has been processed and returned a status.

   Direction

   West Bridge -> P Port Processor

   P Port Processor -> West Bridge

   Length (in transfers)

   1

   Mailbox0

   * Context = all

   * Response Code = 0

   D0

   * 0 = success (CY_AS_ERROR_SUCCESS)

   * non-zero = error code

   Description

   This response indicates that a request was processed and no data

   was generated as a result of the request beyond a single 16 bit

   status value.  This response contains the 16 bit data value.

 */

#define CY_RESP_SUCCESS_FAILURE                    (0)

/* Summary

   This response indicates an invalid request was sent

   Direction

   West Bridge -> P Port Processor

   P Port Processor -> West Bridge

   Length (in transfers)

   1

   Mailbox0

   * Context = all

   * Response Code = 1

   D0

   * Mailbox contents for invalid request

   Description

   This response is returned when a request is sent that contains an invalid

   context or request code.

*/

#define CY_RESP_INVALID_REQUEST                    (1)

/* Summary

   This response indicates a request of invalid length was sent

   Direction

   West Bridge -> P Port Processor

   P Port Processor -> West Bridge

   Length (in transfers)

   1

   Mailbox0

   * Context = all

   * Response Code = 2

   D0

   * Mailbox contenxt for invalid request

   * Length for invalid request

   Description

   The software API and firmware sends requests across the P Port to West Bridge

   interface on different contexts.  Each contexts has a maximum size of the

   request packet that can be received.  The size of a request can be determined

   during the first cycle of a request transfer.  If the request is larger

   than can be handled by the receiving context this response is returned.  Note

   that the complete request is received before this response is sent, but that

   the request is dropped after this response is sent.

*/

#define CY_RESP_INVALID_LENGTH                    (2)

/* Summary

   This response indicates a request was made to an invalid storage address.

   Direction

   West Bridge -> P Port Processor

   Length (in transfers)

   1

   Mailbox0

    * Context = all

    * Response Code = 0

   D0

   Bits 15 - 12 : Media Type

           * 0 = NAND

           * 1 = SD Flash

           * 2 = MMC Flash

           * 3 = CE-ATA

   Bits 11 - 8 : Zero based device index

   Bits 7 - 0 : Zero based unit index

   D1

   Upper 16 bits of block address

   D2

   Lower 16 bits of block address

   D3

   Portion of address that is invalid

        * 0 = Media Type

        * 1 = Device Index

        * 2 = Unit Index

        * 3 = Block Address

   Description

   This response indicates a request to an invalid storage media

   address

 */

#define CY_RESP_NO_SUCH_ADDRESS                    (3)

/******************************************************/

/*@@General requests

    Summary

    The general requests include:

    * CY_RQT_GET_FIRMWARE_VERSION

    * CY_RQT_SET_TRACE_LEVEL

    * CY_RQT_INITIALIZATION_COMPLETE

    * CY_RQT_READ_MCU_REGISTER

    * CY_RQT_WRITE_MCU_REGISTER

    * CY_RQT_STORAGE_MEDIA_CHANGED

    * CY_RQT_CONTROL_ANTIOCH_HEARTBEAT

    * CY_RQT_PREPARE_FOR_STANDBY

    * CY_RQT_ENTER_SUSPEND_MODE

    * CY_RQT_OUT_OF_SUSPEND

    * CY_RQT_GET_GPIO_STATE

    * CY_RQT_SET_GPIO_STATE

    * CY_RQT_SET_SD_CLOCK_FREQ

    * CY_RQT_WB_DEVICE_MISMATCH

    * CY_RQT_BOOTLOAD_NO_FIRMWARE

    * CY_RQT_RESERVE_LNA_BOOT_AREA

    * CY_RQT_ABORT_P2S_XFER

 */

#ifndef __doxygen__

#define CY_RQT_GENERAL_RQT_CONTEXT                (0)

#endif

/* Summary

   This command returns the firmware version number, media types supported and

   debug/release mode information.

   Direction

   P Port Processor-> West Bridge

   Length (in transfers)

   1

   MailBox0

    * Context = 0

    * Request Code = 0

   Description

   The response contains the 16-bit major version, the 16-bit minor version,

   the 16 bit build number, media types supported and release/debug mode

   information.

   Responses

    * CY_RESP_FIRMWARE_VERSION

 */

#define CY_RQT_GET_FIRMWARE_VERSION                (0)

/* Summary

   This command changes the trace level and trace information destination within

   the West Bridge firmware.

   Direction

   P Port Processor-> West Bridge

   Length (in transfers)

   1

   MailBox0

    * Context = 0

    * Request Code = 1

   D0

   Trace Level

    * 0 = no trace information

    * 1 = state information

    * 2 = function call

    * 3 = function call with args/return value

   D1

   Bits 12 - 15 : MediaType

    * 0 = NAND

    * 1 = SDIO Flash

    * 2 = MMC Flash

    * 3 = CE-ATA

   Bits 8 - 11 : Zero based device index

   Bits 0 - 7 : Zero based unit index

   Description

   The West Bridge firmware contains debugging facilities that can be used to trace the

   execution of the firmware.  This request sets the level of tracing information that

   is stored and the location where it is stored.

   Responses

    * CY_RESP_SUCCESS_FAILURE:CY_AS_ERROR_SUCCESS

    * CY_RESP_NO_SUCH_ADDRESS

 */

#define CY_RQT_SET_TRACE_LEVEL                                (1)

/* Summary

   This command indicates that the firmware is up and ready for communications with the

   P port processor.

   Direction

   West Bridge -> P Port Processor

   Length (in transfers)

   2

   Mailbox0

   * Context = 0

   * Request Code = 3

   D0

   Major Version

   D1

   Minor Version

   D2

   Build Number

   D3

   Bits 15-8: Media types supported on Bus 1.

   Bits  7-0: Media types supported on Bus 0.

     Bits 8, 0: NAND support.

       * 0: NAND is not supported.

       * 1: NAND is supported.

     Bits 9, 1: SD memory card support.

       * 0: SD memory card is not supported.

       * 1: SD memory card is supported.

     Bits 10, 2: MMC card support.

       * 0: MMC card is not supported.

       * 1: MMC card is supported.

     Bits 11, 3: CEATA drive support

       * 0: CEATA drive is not supported.

       * 1: CEATA drive is supported.

     Bits 12, 4: SD IO card support.

       * 0: SD IO card is not supported.

       * 1: SD IO card is supported.

   D4

   Bits 15 - 8 : MTP information

     * 0 : MTP not supported in firmware

     * 1 : MTP supported in firmware

   Bits 7 - 0  : Debug/Release mode information.

     * 0 : Release mode

     * 1 : Debug mode

   Description

   When the West Bridge firmware is loaded it being by performing initialization.  Initialization must

   be complete before West Bridge is ready to accept requests from the P port processor.  This request

   is sent from West Bridge to the P port processor to indicate that initialization is complete.

   Responses

   * CY_RESP_SUCCESS_FAILURE:CY_AS_ERROR_SUCCESS

*/

#define CY_RQT_INITIALIZATION_COMPLETE                (3)

/* Summary

   This command requests the firmware to read and return the contents of a MCU accessible

   register.

   Direction

   P Port Processor -> West Bridge

   Length (in transfers)

   1

   Mailbox0

   * Context = 0

   * Request code = 4

   D0

   Address of register to read

   Description

   This debug command allows the processor to read the contents of a MCU accessible register.

   Responses

   * CY_RESP_MCU_REGISTER_DATA

 */

#define CY_RQT_READ_MCU_REGISTER                (4)

/* Summary

   This command requests the firmware to write to an MCU accessible register.

   Direction

   P Port Processor -> West Bridge

   Length (in transfers)

   1

   Mailbox0

   * Context = 0

   * Request code = 5

   D0

   Address of register to be written

   D1

   Bits 15 - 8 : Mask to be applied to existing data.

   Bits 7  - 0 : Data to be ORed with masked data.

   Description

   This debug command allows the processor to write to an MCU accessible register.

   Note: This has to be used with caution, and is supported by the firmware only

         in special debug builds.

   Responses

   * CY_RESP_SUCCESS_FAILURE

 */

#define CY_RQT_WRITE_MCU_REGISTER                (5)

/* Summary

   This command tells the West Bridge firmware that a change in storage media has been detected.

   Direction

   P Port Processor -> West Bridge

   Length (in transfers)

   1

   Mailbox0

   * Context = 0

   * Request code = 6

   Description

   If the insertion or removal of SD or MMC cards is detected by hardware external to West Bridge,

   this command is used to tell the West Bridge firmware to re-initialize the storage controlled by

   the device.

   Responses

   * CY_RESP_SUCCESS_FAILURE

*/

#define CY_RQT_STORAGE_MEDIA_CHANGED                (6)

/* Summary

   This command enables/disables the periodic heartbeat message from the West Bridge firmware to

   the processor.

   Direction

   P Port Processor -> West Bridge

   Length (in transfers)

   1

   Mailbox0

   * Context = 0

   * Request code = 7

   Description

   This command enables/disables the periodic heartbeat message from the West Bridge firmware to

   the processor. The heartbeat message is left enabled by default, and can lead to a loss

   in performance on the P port interface.

   Responses

   * CY_RESP_SUCCESS_FAILURE

 */

#define CY_RQT_CONTROL_ANTIOCH_HEARTBEAT                        (7)

/* Summary

   This command requests the West Bridge firmware to prepare for the device going into standby

   mode.

   Direction

   P Port Processor -> West Bridge

   Length (in transfers)

   1

   Mailbox0

   * Context = 0

   * Request code = 8

   Description

   This command is sent by the processor to the West Bridge as preparation for going into

   standby mode. The request allows the firmware to complete any pending/cached storage

   operations before going into the low power state.

   Responses

   * CY_RESP_SUCCESS_FAILURE

 */

#define CY_RQT_PREPARE_FOR_STANDBY                              (8)

/* Summary

   Requests the firmware to go into suspend mode.

   Direction

   P Port Processor -> West Bridge

   Length (in transfers)

   1

   Mailbox0

   * Context = 0

   * Request code = 9

   D0

   Bits 7-0: Wakeup control information.

   Description

   This command is sent by the processor to the West Bridge to request the device

   to be placed in suspend mode. The firmware will complete any pending/cached storage

   operations before going into the low power state.

   Responses

   * CY_RESP_SUCCESS_FAILURE

 */

#define CY_RQT_ENTER_SUSPEND_MODE                               (9)

/* Summary

   Indicates that the device has left suspend mode.

   Direction

   West Bridge -> P Port Processor

   Length (in transfers)

   1

   Mailbox0

   * Context = 0

   * Request code = 10

   Description

   This message is sent by the West Bridge to the Processor to indicate that the device

   has woken up from suspend mode, and is ready to accept new requests.

   Responses

   * CY_RESP_SUCCESS_FAILURE

 */

#define CY_RQT_OUT_OF_SUSPEND                                   (10)

/* Summary

   Request to get the current state of an West Bridge GPIO pin.

   Direction

   P Port Processor -> West Bridge

   Length (in transfers)

   1

   Mailbox0

   * Context = 0

   * Request code = 11

   D0

   Bits 15 - 8 : GPIO pin identifier

   Responses

   * CY_RESP_GPIO_STATE

   Description

   Request from the processor to get the current state of an West Bridge GPIO pin.

 */

#define CY_RQT_GET_GPIO_STATE                                   (11)

/* Summary

   Request to update the output value on an West Bridge GPIO pin.

   Direction

   P Port Processor -> West Bridge

   Length (in transfers)

   1

   Mailbox0

   * Context = 0

   * Request code = 12

   D0

   Bits 15 - 8 : GPIO pin identifier

   Bit  0      : Desired output state