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1 // Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of the License "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: |
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14 // omap3530/assp/inc/omap3530_hardware_base.h |
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15 // Linear base addresses for hardware peripherals on the beagle board. |
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16 // This file is part of the Beagle Base port |
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17 // |
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18 |
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19 #ifndef OMAP3530_HARDWARE_BASE_H__ |
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20 # define OMAP3530_HARDWARE_BASE_H__ |
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21 |
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22 #include <assp.h> // for TPhysAddr, AsspRegister |
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23 #include <assp/omap3530_assp/omap3530_asspreg.h> |
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24 |
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25 namespace TexasInstruments |
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26 { |
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27 |
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28 namespace Omap3530 |
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29 { |
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30 |
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31 /** |
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32 Define constants for the various physical address blocks used on the OMAP3530 |
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33 */ |
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34 enum TPhysicalAddresses |
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35 { |
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36 KKiloByte = 1024, |
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37 KMegaByte = (1024 * KKiloByte), |
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38 KL4_Core_PhysicalBase = 0x48000000, |
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39 KL4_Core_PhysicalSize = (4 * KMegaByte), |
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40 KL4_Core_PhysicalEnd = (KL4_Core_PhysicalBase + KL4_Core_PhysicalSize), |
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41 |
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42 KL4_WakeUp_PhysicalBase = 0x48300000, |
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43 KL4_WakeUp_PhysicalSize = (256 * KKiloByte ), |
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44 KL4_WakeUp_PhysicalEnd = (KL4_WakeUp_PhysicalBase + KL4_WakeUp_PhysicalSize), |
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45 |
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46 KL4_Per_PhysicalBase = 0x49000000, |
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47 KL4_Per_PhysicalSize = (1 * KMegaByte), |
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48 KL4_Per_PhysicalEnd = (KL4_Per_PhysicalBase + KL4_Per_PhysicalSize), |
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49 |
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50 KL4_Sgx_PhysicalBase = 0x50000000, |
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51 KL4_Sgx_PhysicalSize = (64 * KKiloByte), |
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52 KL4_Sgx_PhysicalEnd = (KL4_Sgx_PhysicalBase + KL4_Sgx_PhysicalSize), |
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53 |
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54 KL4_Emu_PhysicalBase = 0x54000000, |
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55 KL4_Emu_PhysicalSize = (8 * KMegaByte), |
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56 KL4_Emu_PhysicalEnd = (KL4_Emu_PhysicalBase + KL4_Emu_PhysicalSize), |
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57 |
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58 KL3_Control_PhysicalBase = 0x68000000, |
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59 KL3_Control_PhysicalSize = (1 * KMegaByte), |
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60 KL3_Control_PhysicalEnd = (KL3_Control_PhysicalBase + KL3_Control_PhysicalSize), |
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61 |
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62 KL3_Gpmc_PhysicalBase = 0x6e000000, |
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63 KL3_Gpmc_PhysicalSize = (1 * KMegaByte), |
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64 KL3_Gpmc_PhysicalEnd = (KL3_Gpmc_PhysicalBase + KL3_Gpmc_PhysicalSize) |
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65 } ; |
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66 |
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67 /** |
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68 Define constants for the virtual address mappings used on the OMAP3530 |
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69 */ |
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70 enum TLinearAddresses |
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71 { |
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72 KL4_Core_LinearBase = 0xC6000000, |
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73 KL4_Core_LinearSize = KL4_Core_PhysicalSize, |
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74 KL4_Core_LinearEnd = (KL4_Core_LinearBase + KL4_Core_LinearSize), |
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75 |
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76 KL4_WakeUp_LinearBase = (KL4_Core_LinearBase + (KL4_WakeUp_PhysicalBase - KL4_Core_PhysicalBase)), |
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77 KL4_WakeUp_LinearSize = KL4_WakeUp_PhysicalSize, |
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78 KL4_WakeUp_LinearEnd = (KL4_WakeUp_LinearBase + KL4_WakeUp_LinearSize), |
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79 |
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80 KL4_Per_LinearBase = KL4_Core_LinearEnd, |
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81 KL4_Per_LinearSize = KL4_Per_PhysicalSize, |
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82 KL4_Per_LinearEnd = (KL4_Per_LinearBase + KL4_Per_LinearSize), |
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83 |
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84 KL4_Sgx_LinearBase = KL4_Per_LinearEnd, |
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85 KL4_Sgx_LinearSize = KL4_Sgx_PhysicalSize, |
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86 KL4_Sgx_LinearEnd = (KL4_Sgx_LinearBase + KL4_Sgx_LinearSize), |
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87 |
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88 KL4_Emu_LinearBase = KL4_Sgx_LinearBase + KMegaByte, |
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89 KL4_Emu_LinearSize = KL4_Emu_PhysicalSize, |
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90 KL4_Emu_LinearEnd = (KL4_Emu_LinearBase + KL4_Emu_LinearSize), |
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91 |
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92 KL3_Control_LinearBase = KL4_Emu_LinearEnd, |
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93 KL3_Control_LinearSize = KL3_Control_PhysicalSize, |
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94 KL3_Control_LinearEnd = (KL3_Control_LinearBase + KL3_Control_LinearSize), |
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95 |
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96 KL3_Gpmc_LinearBase = KL3_Control_LinearEnd, |
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97 KL3_Gpmc_LinearSize = KL3_Gpmc_PhysicalSize, |
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98 KL3_Gpmc_LinearEnd = (KL3_Gpmc_LinearBase + KL3_Gpmc_LinearSize) |
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99 } ; |
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100 |
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101 /** |
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102 A template to provide the virtual address of a given physical address. |
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103 @example |
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104 @code |
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105 enum TTimerBaseAddress |
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106 { |
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107 KGPTIMER1_Base = Omap3530HwBase::TVirtual<0x48318000>::Value, |
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108 } ; |
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109 */ |
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110 template<const TPhysAddr aDdReSs> |
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111 struct TVirtual |
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112 { |
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113 enum TConstants |
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114 { |
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115 KIsL4Core = ((aDdReSs >= KL4_Core_PhysicalBase) && (aDdReSs < KL4_Core_PhysicalEnd)), |
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116 KIsL4WakeUp = ((aDdReSs >= KL4_WakeUp_PhysicalBase) && (aDdReSs < KL4_WakeUp_PhysicalEnd)), // Subset of L4Core |
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117 KIsL4Per = ((aDdReSs >= KL4_Per_PhysicalBase) && (aDdReSs < KL4_Per_PhysicalEnd)), |
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118 KIsL4Sgx = ((aDdReSs >= KL4_Sgx_PhysicalBase) && (aDdReSs < KL4_Sgx_PhysicalEnd)), |
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119 KIsL4Emu = ((aDdReSs >= KL4_Emu_PhysicalBase) && (aDdReSs < KL4_Emu_PhysicalEnd)), |
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120 KIsL3Control = ((aDdReSs >= KL3_Control_PhysicalBase) && (aDdReSs < KL3_Control_PhysicalEnd)), |
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121 KIsL3Gpmc = ((aDdReSs >= KL3_Gpmc_PhysicalBase) && (aDdReSs < KL3_Gpmc_PhysicalEnd)), |
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122 KIsConvertable = (KIsL4Core || KIsL4Per || KIsL4Sgx || KIsL4Emu || KIsL3Control || KIsL3Gpmc), |
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123 KIsMapped = (KIsL4Core || KIsL4Per || KIsL4Sgx || KIsL4Emu || KIsL3Control || KIsL3Gpmc), |
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124 KOffset = ((KIsL4Core) ? (aDdReSs - KL4_Core_PhysicalBase) |
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125 : ((KIsL4Per) ? (aDdReSs - KL4_Per_PhysicalBase) |
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126 : ((KIsL4Sgx) ? (aDdReSs - KL4_Sgx_PhysicalBase) |
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127 : ((KIsL4Emu) ? (aDdReSs - KL4_Emu_PhysicalBase) |
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128 : ((KIsL3Control) ? (aDdReSs - KL3_Control_PhysicalBase) |
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129 : ((KIsL3Gpmc) ? (aDdReSs - KL3_Gpmc_PhysicalBase) |
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130 : (0))))))), |
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131 // TODO: Change to give compile time error if address not mapped |
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132 KLinearBase = ((KIsL4Core) ? (KL4_Core_LinearBase) |
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133 : ((KIsL4Per) ? (KL4_Per_LinearBase) |
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134 : ((KIsL4Sgx) ? (KL4_Sgx_LinearBase) |
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135 : ((KIsL4Emu) ? (KL4_Emu_LinearBase) |
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136 : ((KIsL3Control) ? (KL3_Control_LinearBase) |
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137 : ((KIsL3Gpmc) ? (KL3_Gpmc_LinearBase) |
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138 : (0))))))), |
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139 /** |
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140 Returns the Linear address mapping for a specific Physical address |
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141 */ |
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142 Value = (KLinearBase + KOffset) |
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143 } ; |
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144 } ; |
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145 |
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146 template<const TLinAddr aDdReSs> |
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147 struct TLinearCheck |
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148 { |
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149 enum TConstants |
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150 { |
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151 KIsL4Core = ((aDdReSs >= KL4_Core_LinearBase) && (aDdReSs < KL4_Core_LinearEnd)), |
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152 KIsL4Per = ((aDdReSs >= KL4_Per_LinearBase) && (aDdReSs < KL4_Per_LinearEnd)), |
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153 KIsL4Sgx = ((aDdReSs >= KL4_Sgx_LinearBase) && (aDdReSs < KL4_Sgx_LinearEnd)), |
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154 KIsL4Emu = ((aDdReSs >= KL4_Emu_LinearBase) && (aDdReSs < KL4_Emu_LinearEnd)), |
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155 KIsL3Control = ((aDdReSs >= KL3_Control_LinearBase) && (aDdReSs < KL3_Control_LinearBase)), |
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156 KIsL3Gpmc = ((aDdReSs >= KL3_Gpmc_LinearBase) && (aDdReSs < KL3_Gpmc_LinearBase)), |
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157 KIsMapped = (KIsL4Core || KIsL4Per || KIsL4Sgx || KIsL4Emu || KIsL3Control || KIsL3Gpmc) |
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158 } ; |
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159 } ; |
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160 |
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161 # ifdef __MEMMODEL_MULTIPLE__ |
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162 const TUint KL4_Core = KL4_Core_LinearBase; // KPrimaryIOBase |
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163 const TUint KL4_Per = KL4_Per_LinearBase; |
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164 const TUint KSgx = KL4_Sgx_LinearBase; |
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165 const TUint KL4_Emu = KL4_Emu_LinearBase; |
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166 const TUint KL3_Control = KL3_Control_LinearBase; |
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167 const TUint KL3_Gpmc = KL3_Gpmc_LinearBase; |
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168 //const TUint KIva2_2Ss = KL4_Core + 0x01910000; |
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169 //const TUint KL3ControlRegisters = KL4_Core + 0x04910000; |
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170 //const TUint KSmsRegisters = KL4_Core + 0x05910000; |
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171 //const TUint KSdrcRegisters = KL4_Core + 0x06910000; |
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172 //const TUint KGpmcRegisters = KL4_Core + 0x07910000; |
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173 |
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174 //#elif __MEMMODEL_FLEXIBLE__ |
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175 // define flexible memery model hw base addresses |
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176 |
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177 # else // unknown memery model |
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178 # error hardware_base.h: Constants may need changing |
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179 # endif // memory model |
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180 |
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181 // Register Access types. |
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182 |
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183 typedef TUint32 TRegValue; |
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184 typedef TUint32 TRegValue32; |
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185 typedef TUint16 TRegValue16; |
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186 typedef TUint8 TRegValue8; |
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187 |
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188 /** |
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189 An interface template for read-only registers. |
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190 */ |
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191 template <TLinAddr aDdReSs> |
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192 class TReg32_R |
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193 { |
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194 public : |
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195 static inline TRegValue Read() |
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196 { |
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197 __ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ; |
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198 return AsspRegister::Read32(aDdReSs) ; |
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199 } |
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200 } ; |
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201 |
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202 template <TLinAddr aDdReSs> |
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203 class TReg16_R |
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204 { |
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205 public : |
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206 static inline TRegValue16 Read() |
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207 { |
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208 __ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ; |
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209 return AsspRegister::Read16(aDdReSs) ; |
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210 } |
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211 } ; |
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212 |
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213 template <TLinAddr aDdReSs> |
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214 class TReg8_R |
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215 { |
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216 public : |
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217 static inline TRegValue8 Read() |
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218 { |
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219 __ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ; |
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220 return AsspRegister::Read8(aDdReSs) ; |
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221 } |
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222 } ; |
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223 |
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224 /** |
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225 An interface template for read-write registers. |
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226 */ |
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227 template <TLinAddr aDdReSs> |
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228 class TReg32_RW : public TReg32_R<aDdReSs> |
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229 { |
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230 public : |
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231 static inline void Write(const TRegValue aValue) |
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232 { |
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233 __ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ; |
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234 AsspRegister::Write32(aDdReSs, aValue) ; |
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235 } |
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236 static inline void Modify(const TRegValue aClearMask, const TRegValue aSetMask) |
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237 { |
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238 __ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ; |
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239 AsspRegister::Modify32(aDdReSs, aClearMask, aSetMask) ; |
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240 } |
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241 } ; |
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242 |
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243 template <TLinAddr aDdReSs> |
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244 class TReg16_RW : public TReg16_R<aDdReSs> |
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245 { |
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246 public : |
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247 static inline void Write(const TRegValue16 aValue) |
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248 { |
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249 __ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ; |
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250 AsspRegister::Write16(aDdReSs, aValue) ; |
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251 } |
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252 static inline void Modify(const TRegValue16 aClearMask, const TRegValue16 aSetMask) |
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253 { |
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254 __ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ; |
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255 AsspRegister::Modify16(aDdReSs, aClearMask, aSetMask) ; |
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256 } |
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257 } ; |
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258 |
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259 template <TLinAddr aDdReSs> |
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260 class TReg8_RW : public TReg8_R<aDdReSs> |
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261 { |
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262 public : |
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263 static inline void Write(const TRegValue8 aValue) |
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264 { |
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265 __ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ; |
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266 AsspRegister::Write8(aDdReSs, aValue) ; |
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267 } |
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268 static inline void Modify(const TRegValue8 aClearMask, const TRegValue8 aSetMask) |
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269 { |
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270 __ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ; |
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271 AsspRegister::Modify8(aDdReSs, aClearMask, aSetMask) ; |
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272 } |
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273 } ; |
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274 |
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275 /** |
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276 An interface template for write-only registers. |
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277 */ |
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278 template <TLinAddr aDdReSs> |
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279 class TReg32_W |
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280 { |
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281 public : |
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282 static inline void Write(const TRegValue aValue) |
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283 { |
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284 __ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ; |
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285 AsspRegister::Write32(aDdReSs, aValue) ; |
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286 } |
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287 } ; |
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288 |
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289 template <TLinAddr aDdReSs> |
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290 class TReg16_W |
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291 { |
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292 public : |
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293 static inline void Write(const TRegValue16 aValue) |
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294 { |
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295 __ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ; |
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296 AsspRegister::Write16(aDdReSs, aValue) ; |
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297 } |
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298 } ; |
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299 |
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300 template <TLinAddr aDdReSs> |
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301 class TReg8_W |
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302 { |
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303 public : |
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304 static inline void Write(const TRegValue8 aValue) |
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305 { |
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306 __ASSERT_COMPILE((TLinearCheck<aDdReSs>::KIsMapped)) ; |
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307 AsspRegister::Write8(aDdReSs, aValue) ; |
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308 } |
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309 } ; |
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310 |
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311 /** Class for registers that have dynamic base address */ |
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312 template <class T, TUint OfFsEt> |
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313 class TDynReg8_R |
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314 { |
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315 public : |
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316 static inline TRegValue8 Read( const T& aOwner ) |
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317 { |
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318 return AsspRegister::Read8( aOwner.Base() + OfFsEt ) ; |
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319 } |
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320 } ; |
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321 |
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322 template <class T, TUint OfFsEt> |
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323 class TDynReg16_R |
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324 { |
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325 public : |
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326 static inline TRegValue16 Read( const T& aOwner ) |
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327 { |
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328 return AsspRegister::Read16( aOwner.Base() + OfFsEt ) ; |
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329 } |
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330 } ; |
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331 |
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332 template <class T, TUint OfFsEt> |
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333 class TDynReg32_R |
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334 { |
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335 public : |
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336 static inline TRegValue32 Read( const T& aOwner ) |
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337 { |
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338 return AsspRegister::Read32( aOwner.Base() + OfFsEt ) ; |
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339 } |
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340 } ; |
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341 |
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342 |
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343 template <class T, TUint OfFsEt> |
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344 class TDynReg8_RW : public TDynReg8_R<T, OfFsEt> |
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345 { |
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346 public : |
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347 static inline void Write( T& aOwner, const TRegValue8 aValue) |
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348 { |
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349 AsspRegister::Write8( aOwner.Base() + OfFsEt, aValue) ; |
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350 } |
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351 static inline void Modify( T& aOwner, const TRegValue8 aClearMask, const TRegValue8 aSetMask) |
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352 { |
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353 AsspRegister::Modify8( aOwner.Base() + OfFsEt, aClearMask, aSetMask) ; |
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354 } |
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355 } ; |
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356 |
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357 template <class T, TUint OfFsEt> |
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358 class TDynReg16_RW : public TDynReg16_R<T, OfFsEt> |
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359 { |
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360 public : |
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361 static inline void Write( T& aOwner, const TRegValue16 aValue) |
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362 { |
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363 AsspRegister::Write16( aOwner.Base() + OfFsEt, aValue) ; |
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364 } |
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365 static inline void Modify( T& aOwner, const TRegValue16 aClearMask, const TRegValue16 aSetMask) |
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366 { |
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367 AsspRegister::Modify16( aOwner.Base() + OfFsEt, aClearMask, aSetMask) ; |
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368 } |
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369 } ; |
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370 |
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371 template <class T, TUint OfFsEt> |
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372 class TDynReg32_RW : public TDynReg32_R<T, OfFsEt> |
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373 { |
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374 public : |
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375 static inline void Write( T& aOwner, const TRegValue32 aValue) |
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376 { |
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377 AsspRegister::Write32( aOwner.Base() + OfFsEt, aValue) ; |
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378 } |
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379 static inline void Modify( T& aOwner, const TRegValue32 aClearMask, const TRegValue32 aSetMask) |
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380 { |
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381 AsspRegister::Modify32( aOwner.Base() + OfFsEt, aClearMask, aSetMask) ; |
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382 } |
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383 } ; |
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384 |
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385 template <class T, TUint OfFsEt> |
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386 class TDynReg8_W |
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387 { |
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388 public : |
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389 static inline void Write( T& aOwner, const TRegValue8 aValue) |
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390 { |
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391 AsspRegister::Write8( aOwner.Base() + OfFsEt, aValue) ; |
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392 } |
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393 static inline void Modify( T& aOwner, const TRegValue8 aClearMask, const TRegValue8 aSetMask) |
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394 { |
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395 AsspRegister::Modify8( aOwner.Base() + OfFsEt, aClearMask, aSetMask) ; |
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396 } |
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397 } ; |
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398 |
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399 template <class T, TUint OfFsEt> |
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400 class TDynReg16_W |
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401 { |
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402 public : |
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403 static inline void Write( T& aOwner, const TRegValue16 aValue) |
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404 { |
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405 AsspRegister::Write16( aOwner.Base() + OfFsEt, aValue) ; |
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406 } |
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407 static inline void Modify( T& aOwner, const TRegValue16 aClearMask, const TRegValue16 aSetMask) |
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408 { |
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409 AsspRegister::Modify16( aOwner.Base() + OfFsEt, aClearMask, aSetMask) ; |
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410 } |
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411 } ; |
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412 |
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413 template <class T, TUint OfFsEt> |
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414 class TDynReg32_W |
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415 { |
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416 public : |
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417 static inline void Write( T& aOwner, const TRegValue32 aValue) |
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418 { |
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419 AsspRegister::Write32( aOwner.Base() + OfFsEt, aValue) ; |
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420 } |
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421 static inline void Modify( T& aOwner, const TRegValue32 aClearMask, const TRegValue32 aSetMask) |
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422 { |
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423 AsspRegister::Modify32( aOwner.Base() + OfFsEt, aClearMask, aSetMask) ; |
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424 } |
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425 } ; |
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426 |
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427 /** |
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428 An Null class for when no register access is required. |
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429 */ |
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430 class TNull_Reg |
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431 { |
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432 public : |
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433 static inline TRegValue Read() |
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434 { |
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435 return 0 ; |
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436 } |
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437 static inline void Write(const TRegValue) |
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438 { |
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439 } |
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440 static inline void Modify(const TRegValue, const TRegValue) |
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441 { |
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442 } |
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443 } ; |
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444 |
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445 template <int aBiTpOsItIoN> |
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446 class TBit |
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447 { |
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448 public : |
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449 enum TConstants |
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450 { |
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451 KValue = (1 << aBiTpOsItIoN) |
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452 } ; |
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453 } ; |
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454 |
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455 template <int aBiTpOsItIoN, int aBiTwIdTh> |
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456 class TBitFieldBase |
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457 { |
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458 public : |
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459 enum TConstants |
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460 { |
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461 KShift = aBiTpOsItIoN, |
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462 KValueMask = (TBit<aBiTwIdTh>::KValue - 1), |
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463 KFieldMask = (KValueMask << KShift), |
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464 KValueMax = KValueMask |
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465 } ; |
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466 } ; |
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467 |
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468 template <int aBiTpOsItIoN, int aBiTwIdTh, int aVaLuE> |
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469 class TBitFieldValue : public TBitFieldBase<aBiTpOsItIoN, aBiTwIdTh> |
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470 { |
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471 public : |
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472 using TBitFieldBase<aBiTpOsItIoN, aBiTwIdTh>::KShift ; |
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473 using TBitFieldBase<aBiTpOsItIoN, aBiTwIdTh>::KValueMask ; |
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474 using TBitFieldBase<aBiTpOsItIoN, aBiTwIdTh>::KFieldMask ; |
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475 using TBitFieldBase<aBiTpOsItIoN, aBiTwIdTh>::KValueMax ; |
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476 |
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477 enum TValues |
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478 { |
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479 KValue = ((KValueMask & aVaLuE) << KShift) |
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480 } ; |
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481 } ; |
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482 |
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483 template <int aBiTpOsItIoN, int aBiTwIdTh> |
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484 class TBitField : public TBitFieldBase<aBiTpOsItIoN, aBiTwIdTh> |
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485 { |
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486 using TBitFieldBase<aBiTpOsItIoN, aBiTwIdTh>::KShift ; |
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487 using TBitFieldBase<aBiTpOsItIoN, aBiTwIdTh>::KValueMask ; |
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488 using TBitFieldBase<aBiTpOsItIoN, aBiTwIdTh>::KFieldMask ; |
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489 using TBitFieldBase<aBiTpOsItIoN, aBiTwIdTh>::KValueMax ; |
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490 public : |
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491 template <int aVaLuE> |
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492 class TConstVal : public TBitFieldValue<aBiTpOsItIoN, aBiTwIdTh, aVaLuE> |
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493 { |
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494 public : |
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495 using TBitFieldValue<aBiTpOsItIoN, aBiTwIdTh, aVaLuE>::KValue ; |
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496 } ; |
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497 |
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498 inline TBitField(const TRegValue aValue) |
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499 : iValue((KValueMask & aValue) << KShift) {} |
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500 |
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501 inline TBitField(const TRegValue * aValuePtr) |
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502 : iValue(KFieldMask & *aValuePtr) {} |
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503 |
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504 template <TLinAddr aDdReSs> |
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505 inline TBitField(const TReg32_R<aDdReSs>& aReg) |
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506 : iValue(KFieldMask & aReg.Read()) {} |
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507 |
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508 inline TRegValue Value() const {return (KValueMask & (iValue >> KShift)) ;} |
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509 |
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510 inline TRegValue RegField() const {return (iValue) ;} |
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511 |
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512 private : |
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513 TRegValue iValue ; |
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514 } ; |
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515 |
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516 template <int aBiTpOsItIoN> |
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517 class TSingleBitField : public TBitField<aBiTpOsItIoN, 1> |
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518 { |
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519 public : |
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520 enum TConstants |
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521 { |
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522 KOff = 0, |
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523 KOn = (1 << aBiTpOsItIoN), |
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524 KClear = KOff, |
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525 KSet = KOn, |
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526 KMask = KOn, |
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527 } ; |
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528 } ; |
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529 |
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530 } ; // namespace Omap3530 |
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531 |
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532 } ; // namespace TexasInstruments |
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533 |
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534 |
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535 namespace TI = TexasInstruments ; |
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536 |
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537 namespace OMAP3530 = TexasInstruments::Omap3530 ; |
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538 |
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539 namespace Omap3530HwBase = TexasInstruments::Omap3530 ; |
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540 |
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541 // **** TEST CODE **** |
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542 //# define HEADER_OMAP3530_HARDWARE_BASE_H_DO_COMPILE_TIME_CHECK_TESTS 1 |
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543 # ifdef HEADER_OMAP3530_HARDWARE_BASE_H_DO_COMPILE_TIME_CHECK_TESTS |
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544 inline void CompileTimeChecks(void) |
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545 { |
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546 __ASSERT_COMPILE((Omap3530HwBase::TVirtual<0x48318000>::KIsL4Core)) ; |
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547 __ASSERT_COMPILE((TI::Omap3530::TVirtual<0x48318000>::KIsL4WakeUp)) ; |
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548 __ASSERT_COMPILE((!Omap3530HwBase::TVirtual<0x48318000>::KIsL4Emu)) ; |
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549 __ASSERT_COMPILE((!Omap3530HwBase::TVirtual<0x0000FFFF>::KIsConvertable)) ; |
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550 __ASSERT_COMPILE((Omap3530HwBase::TLinearCheck< Omap3530HwBase::TVirtual<0x48318000>::Value >::KIsMapped)) ; |
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551 __ASSERT_COMPILE((!Omap3530HwBase::TLinearCheck< Omap3530HwBase::TVirtual<0x0000FFFF>::Value >::KIsMapped)) ; |
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552 const TLinAddr mapped(Omap3530HwBase::TVirtual<0x48318000>::Value) ; |
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553 const TLinAddr unmapped(Omap3530HwBase::TVirtual<0x0000FFFF>::Value) ; |
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554 __ASSERT_COMPILE((Omap3530HwBase::TLinearCheck< mapped >::KIsMapped)) ; |
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555 __ASSERT_COMPILE((!Omap3530HwBase::TLinearCheck< unmapped >::KIsMapped)) ; |
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556 __ASSERT_COMPILE((0)) ; // Prove that testing is happening |
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557 } |
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558 # endif |
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559 |
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560 const TUint KSetNone = 0; |
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561 const TUint KSetAll = 0xffffffff; |
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562 const TUint KClearNone = 0; |
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563 const TUint KClearAll = 0xffffffff; |
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564 const TUint KHOmapClkULPD48Mhz = 48000000; |
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565 |
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566 #endif // !OMAP3530_HARDWARE_BASE_H__ |
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567 |
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568 |
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569 |