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1 // Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of the License "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: |
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14 // omap3530/assp/inc/omap3530_irqmap.h |
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15 // |
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16 |
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17 #ifndef OMAP3530_IRQMAP_H |
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18 #define OMAP3530_IRQMAP_H |
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19 |
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20 #include <assp/omap3530_assp/omap3530_hardware_base.h> |
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21 |
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22 |
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23 #define INTCPS_BASE Omap3530HwBase::KL4_Core + 0x200000 |
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24 #define INTCPS_SYSCONFIG INTCPS_BASE + 0x10 |
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25 #define INTCPS_SYSSTATUS INTCPS_BASE + 0x14 |
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26 #define INTCPS_PROTECTION INTCPS_BASE + 0x4c |
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27 #define INTCPS_IRQ_PRIORITY INTCPS_BASE + 0x60 |
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28 #define INTCPS_FIQ_PRIORITY INTCPS_BASE + 0x64 |
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29 |
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30 |
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31 #define INTCPS_ITR(n) (INTCPS_BASE + 0x80 +( 0x20 *n)) |
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32 #define INTCPS_THRESHOLD INTCPS_BASE + 0x64 |
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33 #define INTCPS_IDLE INTCPS_BASE + 0x50 |
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34 //#define INTC_INIT_REGISTER1 0x470C8010 |
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35 //#define INTC_INIT_REGISTER2 0x470C8050 |
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36 #define INTCPS_ILRM(n) (INTCPS_BASE + 0x100 +(0x04 *n)) |
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37 |
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38 //current interrupt vector & clear regs |
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39 #define INTCPS_SIR_IRQ INTCPS_BASE + 0x40 |
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40 #define INTCPS_SIR_FIQ INTCPS_BASE + 0x44 |
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41 #define INTCPS_CONTROL INTCPS_BASE + 0x48 |
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42 |
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43 |
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44 #define INTCPS_PENDING_IRQ(n) (INTCPS_BASE + 0x98 + (0x20 * n)) |
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45 #define INTCPS_PENDING_FIQ(n) (INTCPS_BASE + 0x9c + (0x20 * n)) |
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46 //masks on /off |
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47 #define INTCPS_MIRn(n) (INTCPS_BASE + 0x084 + (n *0x20)) |
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48 #define INTCPS_MIR_SETn(n) (INTCPS_BASE + 0x08c + (n * 0x20)) |
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49 #define INTCPS_MIR_CLEARn(n) (INTCPS_BASE + 0x088 + (n *0x20)) |
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50 |
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51 |
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52 #define INTCPS_ISRSET(n) (INTCPS_BASE + 0x090 + (n *0x20)) |
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53 #define INTCPS_ISR_CLEAR(n) (INTCPS_BASE + 0x094 + (n *0x20)) |
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54 |
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55 //regvals |
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56 #define INTCPS_SYSCONFIG_AUTOIDLE 0x1 |
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57 #define INTCPS_IDLE_FUNCIDLE 0x0 |
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58 #define INTCPS_IDLE_TURBO 0x1 |
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59 #define INTCPS_ILRM_DEF_PRI (0x1 <<2) |
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60 #define INTCPS_ILRM_ROUTE_FIQ 0x1 |
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61 #define INTCPS_ILRM_ROUTE_IRQ 0x00 |
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62 #define INTCPS_MIR_ALL_UNSET 0x00000000 |
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63 #define INTCPS_MIR_ALL_SET 0xffffffff |
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64 |
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65 #define INTCPS_CONTROL_IRQ_CLEAR 0x1 |
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66 #define INTCPS_CONTROL_FIQ_CLEAR (0x1 << 1) |
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67 #define INTCPS_INIT_RG_LOW_PWR 0x1 |
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68 #define INTCPS_PENDING_MASK 0x7f |
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69 |
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70 |
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71 |
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72 // Base of each interrupt range supported within the ASSP layer |
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73 // Used to index the correct interrupt handler object |
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74 enum TIrqRangeIndex |
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75 { |
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76 EIrqRangeBaseCore, // main interrupt controller |
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77 EIrqRangeBasePrcm, // PRCM sub-controller interrupt sources |
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78 EIrqRangeBaseGpio, // GPIO sub-controller interrupt sources |
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79 EIrqRangeBasePsu, // Place-holder for off-board PSU device, reserved here because |
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80 // we know there will always be one (probably a TPD65950 or similar) |
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81 |
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82 KIrqRangeCount |
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83 }; |
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84 |
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85 const TInt KIrqRangeIndexShift = 16; |
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86 const TInt KIrqNumberMask = 0xFFFF; |
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87 |
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88 /** Class defining an interrupt dispatcher */ |
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89 class MInterruptDispatcher |
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90 { |
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91 public: |
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92 IMPORT_C void Register( TIrqRangeIndex aIndex ); |
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93 |
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94 virtual TInt Bind(TInt aId, TIsr aIsr, TAny* aPtr) = 0; |
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95 virtual TInt Unbind(TInt aId) = 0; |
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96 virtual TInt Enable(TInt aId) = 0; |
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97 virtual TInt Disable(TInt aId) = 0; |
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98 virtual TInt Clear(TInt aId) = 0; |
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99 virtual TInt SetPriority(TInt aId, TInt aPriority) = 0; |
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100 }; |
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101 |
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102 /* |
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103 (1) All the IRQ signals are active at low level. |
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104 (2) These interrupts are internally generated within the MPU subsystem. |
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105 |
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106 Table 10-4. Interrupt Mapping to the MPU Subsystem (continued) |
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107 */ |
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108 enum TOmap3530_IRQ { |
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109 |
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110 EOmap3530_IRQ0_EMUINT = (EIrqRangeBaseCore << KIrqRangeIndexShift), //MPU emulation(2) |
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111 EOmap3530_IRQ1_COMMTX, //MPU emulation(2) |
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112 EOmap3530_IRQ2_COMMRX, //MPU emulation(2) |
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113 EOmap3530_IRQ3_BENCH, //MPU emulation(2) |
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114 EOmap3530_IRQ4_MCBSP2_ST_IRQ, //Sidetone MCBSP2 overflow |
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115 EOmap3530_IRQ5_MCBSP3_ST_IRQ, //Sidetone MCBSP3 overflow |
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116 EOmap3530_IRQ6_SSM_ABORT_IRQ, //MPU subsystem secure state-machine abort (2) |
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117 EOmap3530_IRQ7_SYS_NIRQ, //External source (active low) |
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118 EOmap3530_IRQ8_RESERVED, //RESERVED |
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119 EOmap3530_IRQ9_SMX_DBG_IRQ, //SMX error for debug |
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120 EOmap3530_IRQ10_SMX_APP_IRQ, //SMX error for application |
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121 EOmap3530_IRQ11_PRCM_MPU_IRQ, //PRCM module IRQ |
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122 EOmap3530_IRQ12_SDMA_IRQ0, //System DMA request 0(3) |
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123 EOmap3530_IRQ13_SDMA_IRQ1, //System DMA request 1(3) |
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124 EOmap3530_IRQ14_SDMA_IRQ2, //System DMA request 2 |
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125 EOmap3530_IRQ15_SDMA_IRQ3, //System DMA request 3 |
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126 EOmap3530_IRQ16_MCBSP1_IRQ, //McBSP module 1 IRQ (3) |
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127 EOmap3530_IRQ17_MCBSP2_IRQ, //McBSP module 2 IRQ (3) |
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128 EOmap3530_IRQ18_SR1_IRQ, //SmartReflex™ 1 |
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129 EOmap3530_IRQ19_SR2_IRQ, //SmartReflex™ 2 |
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130 EOmap3530_IRQ20_GPMC_IRQ, //General-purpose memory controller module |
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131 EOmap3530_IRQ21_SGX_IRQ, //2D/3D graphics module |
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132 EOmap3530_IRQ22_MCBSP3_IRQ, //McBSP module 3(3) |
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133 EOmap3530_IRQ23_MCBSP4_IRQ, //McBSP module 4(3) |
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134 EOmap3530_IRQ24_CAEM_IRQ0, //Camera interface request 0 |
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135 EOmap3530_IRQ25_DSS_IRQ, //Display subsystem module(3) |
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136 EOmap3530_IRQ26_MAIL_U0_MPU_IRQ, //Mailbox user 0 request |
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137 EOmap3530_IRQ27_MCBSP5_IRQ, //McBSP module 5 (3) |
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138 EOmap3530_IRQ28_IVA2_MMU_IRQ, //IVA2 MMU |
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139 EOmap3530_IRQ29_GPIO1_MPU_IRQ, //GPIO module 1(3) |
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140 EOmap3530_IRQ30_GPIO2_MPU_IRQ, //GPIO module 2(3) |
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141 EOmap3530_IRQ31_GPIO3_MPU_IRQ, //GPIO module 3(3) |
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142 EOmap3530_IRQ32_GPIO4_MPU_IRQ, //GPIO module 4(3) |
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143 EOmap3530_IRQ33_GPIO5_MPU_IRQ, //GPIO module 5(3) |
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144 EOmap3530_IRQ34_GPIO6_MPU_IRQ, //GPIO module 6(3) |
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145 EOmap3530_IRQ35_USIEM_IRQ, //USIM interrupt (HS devices only) (4) |
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146 EOmap3530_IRQ36_WDT3_IRQ, //Watchdog timer module 3 overflow |
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147 EOmap3530_IRQ37_GPT1_IRQ, //General-purpose timer module 1 |
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148 EOmap3530_IRQ38_GPT2_IRQ, //General-purpose timer module 2 |
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149 EOmap3530_IRQ39_GPT3_IRQ, //General-purpose timer module 3 |
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150 EOmap3530_IRQ40_GPT4_IRQ, //General-purpose timer module 4 |
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151 EOmap3530_IRQ41_GPT5_IRQ, //General-purpose timer module 5(3) |
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152 EOmap3530_IRQ42_GPT6_IRQ, //General-purpose timer module 6(3) |
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153 EOmap3530_IRQ43_GPT7_IRQ, //General-purpose timer module 7(3) |
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154 EOmap3530_IRQ44_GPT8_IRQ, //General-purpose timer module 8(3) |
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155 EOmap3530_IRQ45_GPT9_IRQ, //General-purpose timer module 9 |
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156 EOmap3530_IRQ46_GPT10_IRQ, //General-purpose timer module 10 |
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157 EOmap3530_IRQ47_GPT11_IRQ, //General-purpose timer module 11 |
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158 EOmap3530_IRQ48_SPI4_IRQ, //McSPI module 4 |
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159 EOmap3530_IRQ49_SHA1MD5_IRQ2, //SHA-1/MD5 crypto-accelerator 2 (HS devices only)(4) |
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160 EOmap3530_IRQ50_FPKA_IRQREADY_N, //PKA crypto-accelerator (HS devices only) (4) |
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161 EOmap3530_IRQ51_SHA2MD5_IRQ, //SHA-2/MD5 crypto-accelerator 1 (HS devices only) (4) |
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162 EOmap3530_IRQ52_RNG_IRQ, //RNG module (HS devices only) (4) |
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163 EOmap3530_IRQ53_MG_IRQ, //MG function (3) |
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164 EOmap3530_IRQ54_MCBSP4_IRQTX, //McBSP module 4 transmit(3) |
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165 EOmap3530_IRQ55_MCBSP4_IRQRX, //McBSP module 4 receive(3) |
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166 EOmap3530_IRQ56_I2C1_IRQ, //I2C module 1 |
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167 EOmap3530_IRQ57_I2C2_IRQ, //I2C module 2 |
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168 EOmap3530_IRQ58_HDQ_IRQ, //HDQ/One-wire |
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169 EOmap3530_IRQ59_McBSP1_IRQTX, //McBSP module 1 transmit(3) |
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170 EOmap3530_IRQ60_McBSP1_IRQRX, //McBSP module 1 receive(3) |
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171 EOmap3530_IRQ61_I2C3_IRQ, //I2C module 3 |
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172 EOmap3530_IRQ62_McBSP2_IRQTX, //McBSP module 2 transmit(3) |
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173 EOmap3530_IRQ63_McBSP2_IRQRX, //McBSP module 2 receive(3) |
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174 EOmap3530_IRQ64_FPKA_IRQRERROR_N, //PKA crypto-accelerator (HS devices only) (4) |
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175 EOmap3530_IRQ65_SPI1_IRQ, //McSPI module 1 |
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176 EOmap3530_IRQ66_SPI2_IRQ, //McSPI module 2 |
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177 EOmap3530_IRQ67_RESERVED, //RESERVED |
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178 EOmap3530_IRQ68_RESERVED, //RESERVED |
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179 EOmap3530_IRQ69_RESERVED, //RESERVED |
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180 EOmap3530_IRQ70_RESERVED, //RESERVED |
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181 EOmap3530_IRQ71_RESERVED, //RESERVED |
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182 EOmap3530_IRQ72_UART1_IRQ, //UART module 1 |
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183 EOmap3530_IRQ73_UART2_IRQ, //UART module 2 |
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184 EOmap3530_IRQ74_UART3_IRQ, //UART module 3 (also infrared)(3) |
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185 EOmap3530_IRQ75_PBIAS_IRQ, //Merged interrupt for PBIASlite1 and 2 |
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186 EOmap3530_IRQ76_OHCI_IRQ, //OHCI controller HSUSB MP Host Interrupt |
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187 EOmap3530_IRQ77_EHCI_IRQ, //EHCI controller HSUSB MP Host Interrupt |
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188 EOmap3530_IRQ78_TLL_IRQ, //HSUSB MP TLL Interrupt |
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189 EOmap3530_IRQ79_PARTHASH_IRQ, //SHA2/MD5 crypto-accelerator 1 (HS devices only) (4) |
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190 EOmap3530_IRQ80_RESERVED, //Reserved |
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191 EOmap3530_IRQ81_MCBSP5_IRQTX, //McBSP module 5 transmit(3) |
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192 EOmap3530_IRQ82_MCBSP5_IRQRX, //McBSP module 5 receive(3) |
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193 EOmap3530_IRQ83_MMC1_IRQ, //MMC/SD module 1 |
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194 EOmap3530_IRQ84_MS_IRQ, //MS-PRO module |
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195 EOmap3530_IRQ85_RESERVED, //Reserved |
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196 EOmap3530_IRQ86_MMC2_IRQ, //MMC/SD module 2 |
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197 EOmap3530_IRQ87_MPU_ICR_IRQ, //MPU ICR |
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198 EOmap3530_IRQ88_RESERVED, //RESERVED |
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199 EOmap3530_IRQ89_MCBSP3_IRQTX, //McBSP module 3 transmit(3) |
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200 EOmap3530_IRQ90_MCBSP3_IRQRX, //McBSP module 3 receive(3) |
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201 EOmap3530_IRQ91_SPI3_IRQ, //McSPI module 3 |
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202 EOmap3530_IRQ92_HSUSB_MC_NINT, //High-Speed USB OTG controller |
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203 EOmap3530_IRQ93_HSUSB_DMA_NINT, //High-Speed USB OTG DMA controller |
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204 EOmap3530_IRQ94_MMC3_IRQ, //MMC/SD module 3 |
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205 EOmap3530_IRQ95_GPT12_IRQ, //General-purpose timer module 12 |
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206 |
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207 // IRQ virtual IDs |
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208 EOmap3530_GPIOIRQ_FIRST, |
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209 |
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210 EOmap3530_GPIOIRQ_PIN_0, |
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211 EOmap3530_GPIOIRQ_PIN_1, |
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212 EOmap3530_GPIOIRQ_PIN_2, |
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213 EOmap3530_GPIOIRQ_PIN_3, |
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214 EOmap3530_GPIOIRQ_PIN_4, |
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215 EOmap3530_GPIOIRQ_PIN_5, |
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216 EOmap3530_GPIOIRQ_PIN_6, |
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217 EOmap3530_GPIOIRQ_PIN_7, |
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218 EOmap3530_GPIOIRQ_PIN_8, |
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219 EOmap3530_GPIOIRQ_PIN_9, |
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220 EOmap3530_GPIOIRQ_PIN_10, |
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221 EOmap3530_GPIOIRQ_PIN_11, |
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222 EOmap3530_GPIOIRQ_PIN_12, |
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223 EOmap3530_GPIOIRQ_PIN_13, |
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224 EOmap3530_GPIOIRQ_PIN_14, |
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225 EOmap3530_GPIOIRQ_PIN_15, |
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226 EOmap3530_GPIOIRQ_PIN_16, |
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227 EOmap3530_GPIOIRQ_PIN_17, |
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228 EOmap3530_GPIOIRQ_PIN_18, |
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229 EOmap3530_GPIOIRQ_PIN_19, |
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230 EOmap3530_GPIOIRQ_PIN_20, |
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231 EOmap3530_GPIOIRQ_PIN_21, |
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232 EOmap3530_GPIOIRQ_PIN_22, |
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233 EOmap3530_GPIOIRQ_PIN_23, |
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234 EOmap3530_GPIOIRQ_PIN_24, |
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235 EOmap3530_GPIOIRQ_PIN_25, |
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236 EOmap3530_GPIOIRQ_PIN_26, |
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237 EOmap3530_GPIOIRQ_PIN_27, |
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238 EOmap3530_GPIOIRQ_PIN_28, |
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239 EOmap3530_GPIOIRQ_PIN_29, |
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240 EOmap3530_GPIOIRQ_PIN_30, |
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241 EOmap3530_GPIOIRQ_PIN_31, |
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242 EOmap3530_GPIOIRQ_PIN_32, |
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243 EOmap3530_GPIOIRQ_PIN_33, |
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244 EOmap3530_GPIOIRQ_PIN_34, |
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245 EOmap3530_GPIOIRQ_PIN_35, |
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246 EOmap3530_GPIOIRQ_PIN_36, |
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247 EOmap3530_GPIOIRQ_PIN_37, |
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248 EOmap3530_GPIOIRQ_PIN_38, |
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249 EOmap3530_GPIOIRQ_PIN_39, |
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250 EOmap3530_GPIOIRQ_PIN_40, |
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251 EOmap3530_GPIOIRQ_PIN_41, |
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252 EOmap3530_GPIOIRQ_PIN_42, |
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253 EOmap3530_GPIOIRQ_PIN_43, |
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254 EOmap3530_GPIOIRQ_PIN_44, |
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255 EOmap3530_GPIOIRQ_PIN_45, |
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256 EOmap3530_GPIOIRQ_PIN_46, |
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257 EOmap3530_GPIOIRQ_PIN_47, |
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258 EOmap3530_GPIOIRQ_PIN_48, |
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259 EOmap3530_GPIOIRQ_PIN_49, |
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260 EOmap3530_GPIOIRQ_PIN_50, |
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261 EOmap3530_GPIOIRQ_PIN_51, |
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262 EOmap3530_GPIOIRQ_PIN_52, |
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263 EOmap3530_GPIOIRQ_PIN_53, |
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264 EOmap3530_GPIOIRQ_PIN_54, |
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265 EOmap3530_GPIOIRQ_PIN_55, |
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266 EOmap3530_GPIOIRQ_PIN_56, |
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267 EOmap3530_GPIOIRQ_PIN_57, |
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268 EOmap3530_GPIOIRQ_PIN_58, |
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269 EOmap3530_GPIOIRQ_PIN_59, |
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270 EOmap3530_GPIOIRQ_PIN_60, |
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271 EOmap3530_GPIOIRQ_PIN_61, |
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272 EOmap3530_GPIOIRQ_PIN_62, |
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273 EOmap3530_GPIOIRQ_PIN_63, |
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274 EOmap3530_GPIOIRQ_PIN_64, |
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275 EOmap3530_GPIOIRQ_PIN_65, |
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276 EOmap3530_GPIOIRQ_PIN_66, |
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277 EOmap3530_GPIOIRQ_PIN_67, |
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278 EOmap3530_GPIOIRQ_PIN_68, |
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279 EOmap3530_GPIOIRQ_PIN_69, |
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280 EOmap3530_GPIOIRQ_PIN_70, |
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281 EOmap3530_GPIOIRQ_PIN_71, |
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282 EOmap3530_GPIOIRQ_PIN_72, |
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283 EOmap3530_GPIOIRQ_PIN_73, |
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284 EOmap3530_GPIOIRQ_PIN_74, |
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285 EOmap3530_GPIOIRQ_PIN_75, |
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286 EOmap3530_GPIOIRQ_PIN_76, |
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287 EOmap3530_GPIOIRQ_PIN_77, |
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288 EOmap3530_GPIOIRQ_PIN_78, |
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289 EOmap3530_GPIOIRQ_PIN_79, |
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290 EOmap3530_GPIOIRQ_PIN_80, |
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291 EOmap3530_GPIOIRQ_PIN_81, |
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292 EOmap3530_GPIOIRQ_PIN_82, |
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293 EOmap3530_GPIOIRQ_PIN_83, |
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294 EOmap3530_GPIOIRQ_PIN_84, |
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295 EOmap3530_GPIOIRQ_PIN_85, |
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296 EOmap3530_GPIOIRQ_PIN_86, |
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297 EOmap3530_GPIOIRQ_PIN_87, |
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298 EOmap3530_GPIOIRQ_PIN_88, |
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299 EOmap3530_GPIOIRQ_PIN_89, |
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300 EOmap3530_GPIOIRQ_PIN_90, |
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301 EOmap3530_GPIOIRQ_PIN_91, |
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302 EOmap3530_GPIOIRQ_PIN_92, |
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303 EOmap3530_GPIOIRQ_PIN_93, |
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304 EOmap3530_GPIOIRQ_PIN_94, |
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305 EOmap3530_GPIOIRQ_PIN_95, |
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306 EOmap3530_GPIOIRQ_PIN_96, |
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307 EOmap3530_GPIOIRQ_PIN_97, |
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308 EOmap3530_GPIOIRQ_PIN_98, |
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309 EOmap3530_GPIOIRQ_PIN_99, |
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310 EOmap3530_GPIOIRQ_PIN_100, |
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311 EOmap3530_GPIOIRQ_PIN_101, |
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312 EOmap3530_GPIOIRQ_PIN_102, |
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313 EOmap3530_GPIOIRQ_PIN_103, |
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314 EOmap3530_GPIOIRQ_PIN_104, |
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315 EOmap3530_GPIOIRQ_PIN_105, |
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316 EOmap3530_GPIOIRQ_PIN_106, |
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317 EOmap3530_GPIOIRQ_PIN_107, |
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318 EOmap3530_GPIOIRQ_PIN_108, |
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319 EOmap3530_GPIOIRQ_PIN_109, |
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320 EOmap3530_GPIOIRQ_PIN_110, |
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321 EOmap3530_GPIOIRQ_PIN_111, |
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322 EOmap3530_GPIOIRQ_PIN_112, |
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323 EOmap3530_GPIOIRQ_PIN_113, |
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324 EOmap3530_GPIOIRQ_PIN_114, |
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325 EOmap3530_GPIOIRQ_PIN_115, |
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326 EOmap3530_GPIOIRQ_PIN_116, |
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327 EOmap3530_GPIOIRQ_PIN_117, |
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328 EOmap3530_GPIOIRQ_PIN_118, |
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329 EOmap3530_GPIOIRQ_PIN_119, |
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330 EOmap3530_GPIOIRQ_PIN_120, |
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331 EOmap3530_GPIOIRQ_PIN_121, |
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332 EOmap3530_GPIOIRQ_PIN_122, |
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333 EOmap3530_GPIOIRQ_PIN_123, |
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334 EOmap3530_GPIOIRQ_PIN_124, |
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335 EOmap3530_GPIOIRQ_PIN_125, |
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336 EOmap3530_GPIOIRQ_PIN_126, |
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337 EOmap3530_GPIOIRQ_PIN_127, |
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338 EOmap3530_GPIOIRQ_PIN_128, |
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339 EOmap3530_GPIOIRQ_PIN_129, |
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340 EOmap3530_GPIOIRQ_PIN_130, |
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341 EOmap3530_GPIOIRQ_PIN_131, |
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342 EOmap3530_GPIOIRQ_PIN_132, |
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343 EOmap3530_GPIOIRQ_PIN_133, |
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344 EOmap3530_GPIOIRQ_PIN_134, |
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345 EOmap3530_GPIOIRQ_PIN_135, |
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346 EOmap3530_GPIOIRQ_PIN_136, |
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347 EOmap3530_GPIOIRQ_PIN_137, |
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348 EOmap3530_GPIOIRQ_PIN_138, |
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349 EOmap3530_GPIOIRQ_PIN_139, |
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350 EOmap3530_GPIOIRQ_PIN_140, |
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351 EOmap3530_GPIOIRQ_PIN_141, |
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352 EOmap3530_GPIOIRQ_PIN_142, |
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353 EOmap3530_GPIOIRQ_PIN_143, |
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354 EOmap3530_GPIOIRQ_PIN_144, |
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355 EOmap3530_GPIOIRQ_PIN_145, |
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356 EOmap3530_GPIOIRQ_PIN_146, |
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357 EOmap3530_GPIOIRQ_PIN_147, |
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358 EOmap3530_GPIOIRQ_PIN_148, |
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359 EOmap3530_GPIOIRQ_PIN_149, |
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360 EOmap3530_GPIOIRQ_PIN_150, |
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361 EOmap3530_GPIOIRQ_PIN_151, |
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362 EOmap3530_GPIOIRQ_PIN_152, |
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363 EOmap3530_GPIOIRQ_PIN_153, |
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364 EOmap3530_GPIOIRQ_PIN_154, |
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365 EOmap3530_GPIOIRQ_PIN_155, |
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366 EOmap3530_GPIOIRQ_PIN_156, |
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367 EOmap3530_GPIOIRQ_PIN_157, |
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368 EOmap3530_GPIOIRQ_PIN_158, |
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369 EOmap3530_GPIOIRQ_PIN_159, |
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370 EOmap3530_GPIOIRQ_PIN_160, |
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371 EOmap3530_GPIOIRQ_PIN_161, |
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372 EOmap3530_GPIOIRQ_PIN_162, |
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373 EOmap3530_GPIOIRQ_PIN_163, |
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374 EOmap3530_GPIOIRQ_PIN_164, |
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375 EOmap3530_GPIOIRQ_PIN_165, |
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376 EOmap3530_GPIOIRQ_PIN_166, |
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377 EOmap3530_GPIOIRQ_PIN_167, |
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378 EOmap3530_GPIOIRQ_PIN_168, |
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379 EOmap3530_GPIOIRQ_PIN_169, |
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380 EOmap3530_GPIOIRQ_PIN_170, |
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381 EOmap3530_GPIOIRQ_PIN_171, |
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382 EOmap3530_GPIOIRQ_PIN_172, |
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383 EOmap3530_GPIOIRQ_PIN_173, |
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384 EOmap3530_GPIOIRQ_PIN_174, |
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385 EOmap3530_GPIOIRQ_PIN_175, |
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386 EOmap3530_GPIOIRQ_PIN_176, |
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387 EOmap3530_GPIOIRQ_PIN_177, |
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388 EOmap3530_GPIOIRQ_PIN_178, |
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389 EOmap3530_GPIOIRQ_PIN_179, |
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390 EOmap3530_GPIOIRQ_PIN_180, |
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391 EOmap3530_GPIOIRQ_PIN_181, |
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392 EOmap3530_GPIOIRQ_PIN_182, |
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393 EOmap3530_GPIOIRQ_PIN_183, |
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394 EOmap3530_GPIOIRQ_PIN_184, |
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395 EOmap3530_GPIOIRQ_PIN_185, |
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396 EOmap3530_GPIOIRQ_PIN_186, |
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397 EOmap3530_GPIOIRQ_PIN_187, |
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398 EOmap3530_GPIOIRQ_PIN_188, |
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399 EOmap3530_GPIOIRQ_PIN_189, |
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400 EOmap3530_GPIOIRQ_PIN_190, |
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401 EOmap3530_GPIOIRQ_PIN_191, |
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402 |
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403 EOmap3530_GPIOIRQ_TOTAL, |
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404 |
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405 EOmap3530_TOTAL_IRQS |
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406 }; |
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407 |
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408 |
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409 |
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410 const TInt KNumOmap3530Ints = (EOmap3530_GPIOIRQ_FIRST -1); |
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411 |
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412 const TInt KOmap3530MaxIntPriority =0; |
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413 const TInt KOmap3530MinIntPriority =63; |
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414 const TInt KOmap3530DefIntPriority =KOmap3530MinIntPriority /2; |
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415 IMPORT_C void ClearAndDisableTestInterrupt(TInt anId); |
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416 IMPORT_C void TestInterrupts(TInt id,TIsr func); |
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417 |
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418 |
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419 #endif /*Omap3530_IRQMAP_H*/ |