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1 // Copyright (c) 2009 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of the License "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: |
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14 // /omap3530/assp/inc/omap3530_timer.h |
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15 // |
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16 |
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17 #ifndef HEADER_OMAP3530_TIMER_H_INCLUDED |
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18 # define HEADER_OMAP3530_TIMER_H_INCLUDED |
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19 |
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20 /** |
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21 @file |
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22 omap3530_timer.h header file |
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23 This file provides timer handling for the omap3530 timers |
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24 @publishedAll |
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25 @released |
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26 */ |
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27 |
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28 #include <assp/omap3530_assp/omap3530_hardware_base.h> |
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29 #include <assp/omap3530_assp/omap3530_irqmap.h> |
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30 |
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31 namespace TexasInstruments |
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32 { |
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33 |
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34 namespace Omap3530 |
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35 { |
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36 |
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37 |
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38 namespace GPTimer |
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39 { |
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40 |
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41 namespace TIOCP_CFG |
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42 { |
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43 /** |
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44 0 AUTOIDLE Internal L4 interface clock gating strategy 0 |
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45 0x0: L4 interface clock is free-running. |
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46 0x1: Automatic L4 interface clock gating strategy isapplied, based on the L4 interface activity. |
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47 */ |
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48 typedef TSingleBitField<0> T_AUTOIDLE ; |
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49 |
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50 /** |
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51 1 SOFTRESET Software reset. This bit is automatically reset by the RW 0 hardware. During reads, it always returns 0. |
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52 0x0: Normal mode |
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53 0x1: The module is reset. |
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54 */ |
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55 typedef TSingleBitField<1> T_SOFTRESET ; |
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56 |
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57 /** |
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58 2 ENAWAKEUP Wake-up feature global control RW 0 |
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59 0x0: No wake-up line assertion in idle mode |
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60 0x1: Wake-up line assertion enabled in smart-idle mode |
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61 */ |
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62 typedef TSingleBitField<2> T_ENAWAKEUP ; |
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63 |
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64 /** |
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65 4:3 IDLEMODE Power management, req/ack control RW 0x0 |
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66 0x0: Force-idle. An idle request is acknowledged unconditionally. |
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67 0x1: No-idle. An idle request is never acknowledged. |
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68 0x2: Smart-idle. Acknowledgement to an idle request is given based on the internal activity of the module. |
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69 0x3: Reserved. Do not use. |
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70 */ |
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71 class T_IDLEMODE : public TBitField<3, 2> |
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72 { |
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73 public : |
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74 enum TConstants |
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75 { |
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76 KForceIdle = TConstVal<0>::KValue, |
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77 KNoIdle = TConstVal<1>::KValue, |
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78 KSmartIdle = TConstVal<2>::KValue |
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79 } ; |
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80 } ; |
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81 |
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82 /** |
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83 5 EMUFREE Emulation mode RW 0 |
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84 0x0: Timer counter frozen in emulation |
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85 0x1: Timer counter free-running in emulation |
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86 */ |
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87 typedef TSingleBitField<5> T_EMUFREE ; |
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88 |
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89 /** |
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90 9:8 CLOCKACTIVITY Clock activity during wakeup mode period: RW 0x0 |
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91 0x0: L4 interface and Functional clocks can be switched off. |
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92 0x1: L4 interface clock is maintained during wake-up period; Functional clock can be switched off. |
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93 0x2: L4 interface clock can be switched off; Functional clock is maintained during wake-up period. |
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94 0x3: L4 interface and Functional clocks are maintained during wake-up period. |
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95 */ |
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96 class T_CLOCKACTIVITY : public TBitField<8, 2> |
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97 { |
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98 public : |
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99 enum TConstants |
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100 { |
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101 KMaintainNeither = TConstVal<0>::KValue, |
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102 KMaintainIfClock = TConstVal<1>::KValue, |
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103 KMaintainFuncClock = TConstVal<2>::KValue, |
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104 KMaintainBoth = TConstVal<3>::KValue |
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105 } ; |
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106 } ; |
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107 |
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108 } ; // namespace TIOCP_CFG |
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109 |
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110 namespace TISTAT |
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111 { |
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112 /** |
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113 0 RESETDONE Internal reset monitoring R 0 |
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114 0x0: Internal module reset is ongoing. |
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115 0x1: Reset completed |
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116 */ |
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117 typedef TSingleBitField<0> T_RESETDONE ; |
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118 |
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119 } ; // namespace TISTAT |
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120 |
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121 namespace TISR |
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122 { |
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123 /** |
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124 0 MAT_IT_FLAG Pending match interrupt status RW 0 |
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125 Read 0x0: No match interrupt pending |
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126 Write 0x0: Status unchanged |
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127 Read 0x1: Match interrupt pending |
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128 Write 0x1: Status bit cleared |
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129 */ |
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130 typedef TSingleBitField<0> T_MAT_IT_FLAG ; |
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131 |
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132 /** |
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133 1 OVF_IT_FLAG Pending overflow interrupt status RW 0 |
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134 Read 0x0: No overflow interrupt pending |
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135 Write 0x0: Status unchanged |
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136 Read 0x1: Overflow interrupt pending |
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137 Write 0x1: Status bit cleared |
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138 */ |
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139 typedef TSingleBitField<1> T_OVF_IT_FLAG ; |
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140 |
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141 /** |
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142 2 TCAR_IT_FLAG Pending capture interrupt status RW 0 |
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143 Read 0x0: No capture interrupt event pending |
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144 Write 0x0: Status unchanged |
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145 Read 0x1: Capture interrupt event pending |
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146 Write 0x1: Status bit cleared |
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147 */ |
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148 typedef TSingleBitField<2> T_TCAR_IT_FLAG ; |
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149 |
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150 } ; // namespace TISR |
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151 |
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152 namespace TIER |
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153 { |
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154 /** |
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155 0 MAT_IT_ENA Enable match interrupt RW 0 |
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156 0x0: Disable match interrupt. |
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157 0x1: Enable match interrupt. |
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158 */ |
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159 typedef TSingleBitField<0> T_MAT_IT_ENA ; |
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160 |
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161 /** |
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162 1 OVF_IT_ENA Enable overflow interrupt RW 0 |
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163 0x0: Disable overflow interrupt. |
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164 0x1: Enable overflow interrupt. |
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165 */ |
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166 typedef TSingleBitField<1> T_OVF_IT_ENA ; |
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167 |
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168 /** |
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169 2 TCAR_IT_ENA Enable capture interrupt RW 0 |
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170 0x0: Disable capture interrupt. |
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171 0x1: Enable capture interrupt. |
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172 */ |
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173 typedef TSingleBitField<2> T_TCAR_IT_ENA ; |
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174 |
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175 } ; // namespace TIER |
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176 |
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177 namespace TWER |
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178 { |
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179 /** |
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180 0 MAT_WUP_ENA Enable match wake-up RW 0 |
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181 0x0: Disable match wake-up. |
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182 0x1: Enable match wake-up. |
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183 */ |
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184 typedef TSingleBitField<0> T_MAT_WUP_ENA ; |
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185 |
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186 /** |
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187 1 OVF_WUP_ENA Enable overflow wake-up RW 0 |
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188 0x0: Disable overflow wake-up. |
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189 0x1: Enable overflow wake-up. |
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190 */ |
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191 typedef TSingleBitField<1> T_OVF_WUP_ENA ; |
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192 |
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193 /** |
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194 2 TCAR_WUP_ENA Enable capture wake-up RW 0 |
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195 0x0: Disable capture wake-up. |
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196 0x1: Enable capture wake-up. |
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197 */ |
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198 typedef TSingleBitField<2> T_TCAR_WUP_ENA ; |
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199 |
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200 } ; // namespace TWER |
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201 |
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202 namespace TCLR |
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203 { |
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204 /** |
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205 0 ST Start/stop timer control RW 0 |
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206 0x0: Stop the timer |
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207 0x1: Start the timer |
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208 */ |
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209 typedef TSingleBitField<0> T_ST ; |
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210 |
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211 /** |
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212 1 AR Autoreload mode RW 0 |
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213 0x0: One-shot mode overflow |
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214 0x1: Autoreload mode overflow |
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215 */ |
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216 typedef TSingleBitField<1> T_AR ; |
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217 |
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218 /** |
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219 4:2 PTV Trigger output mode |
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220 0x0: The timer counter is prescaled with the value: RW 0x0 |
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221 2(PTV+1). Example: PTV = 3, counter increases value (if started) after 16 functional clock periods. |
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222 */ |
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223 class T_PTV : public TBitField<2, 3> |
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224 { |
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225 public : |
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226 enum TConstants |
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227 { |
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228 KPS_2 = TConstVal<0>::KValue, |
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229 KPS_4 = TConstVal<1>::KValue, |
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230 KPS_8 = TConstVal<2>::KValue, |
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231 KPS_16 = TConstVal<3>::KValue, |
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232 KPS_32 = TConstVal<4>::KValue, |
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233 KPS_64 = TConstVal<5>::KValue, |
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234 KPS_128 = TConstVal<6>::KValue, |
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235 KPS_256 = TConstVal<7>::KValue |
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236 } ; |
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237 } ; |
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238 |
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239 /** |
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240 5 PRE Prescaler enable RW 0 |
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241 0x0: Prescaler disabled |
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242 0x1: Prescaler enabled |
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243 */ |
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244 typedef TSingleBitField<5> T_PRE ; |
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245 |
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246 /** |
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247 6 CE Compare enable RW 0 |
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248 0x0: Compare disabled |
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249 0x1: Compare enabled |
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250 */ |
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251 typedef TSingleBitField<6> T_CE ; |
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252 |
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253 /** |
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254 7 SCPWM Pulse-width-modulation output pin default setting when RW 0 |
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255 counter is stopped or trigger output mode is set to no trigger. |
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256 0x0: Default value of PWM_out output: 0 |
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257 0x1: Default value of PWM_out output: 1 |
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258 */ |
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259 typedef TSingleBitField<7> T_SCPWM ; |
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260 |
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261 /** |
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262 9:8 TCM Transition capture mode RW 0x0 |
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263 0x0: No capture |
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264 0x1: Capture on rising edges of EVENT_CAPTURE pin. |
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265 0x2: Capture on falling edges of EVENT_CAPTURE pin. |
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266 0x3: Capture on both edges of EVENT_CAPTURE pin. |
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267 */ |
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268 class T_TCM : public TBitField<8, 2> |
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269 { |
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270 public : |
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271 enum TConstants |
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272 { |
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273 KNoCapture = TConstVal<0>::KValue, |
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274 KRisingEdge = TConstVal<1>::KValue, |
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275 KFallingEdge = TConstVal<2>::KValue, |
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276 KBothEdges = TConstVal<3>::KValue |
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277 } ; |
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278 } ; |
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279 |
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280 /** |
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281 11:10 TRG Trigger output mode RW 0x0 |
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282 0x0: No trigger |
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283 0x1: Overflow trigger |
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284 0x2: Overflow and match trigger |
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285 0x3: Reserved |
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286 */ |
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287 class T_IDLEMODE : public TBitField<10, 2> |
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288 { |
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289 public : |
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290 enum TConstants |
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291 { |
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292 KNoTrigger = TConstVal<0>::KValue, |
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293 KOverflow = TConstVal<1>::KValue, |
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294 KOverflowAndMatch = TConstVal<2>::KValue |
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295 } ; |
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296 } ; |
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297 |
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298 /** |
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299 12 PT Pulse or toggle select bit RW 0 |
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300 0x0: Pulse modulation |
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301 0x1: Toggle modulation |
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302 */ |
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303 typedef TSingleBitField<12> T_PT ; |
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304 |
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305 /** |
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306 13 CAPT_MODE Capture mode select bit (first/second) RW 0 |
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307 0x0: Capture the first enabled capture event in TCAR1. |
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308 0x1: Capture the second enabled capture event in TCAR2. |
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309 */ |
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310 typedef TSingleBitField<13> T_CAPT_MODE ; |
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311 |
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312 /** |
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313 14 GPO_CFG PWM output/event detection input pin direction control: RW 0 |
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314 0x0: Configures the pin as an output (needed when PWM mode is required) |
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315 0x1: Configures the pin as an input (needed when capture mode is required) |
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316 */ |
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317 typedef TSingleBitField<14> T_GPO_CFG ; |
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318 |
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319 } ; // namespace TCLR |
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320 |
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321 namespace TWPS |
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322 { |
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323 /** |
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324 0 W_PEND_TCLR Write pending for register GPT_TCLR R 0 |
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325 0x0: Control register write not pending |
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326 0x1: Control register write pending |
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327 */ |
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328 typedef TSingleBitField<0> T_W_PEND_TCLR ; |
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329 |
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330 /** |
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331 1 W_PEND_TCRR Write pending for register GPT_TCRR R 0 |
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332 0x0: Counter register write not pending |
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333 0x1: Counter register write pending |
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334 */ |
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335 typedef TSingleBitField<1> T_W_PEND_TCRR ; |
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336 |
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337 /** |
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338 2 W_PEND_TLDR Write pending for register GPT_TLDR R 0 |
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339 0x0: Load register write not pending |
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340 0x1: Load register write pending |
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341 */ |
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342 typedef TSingleBitField<2> T_W_PEND_TLDR ; |
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343 |
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344 /** |
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345 3 W_PEND_TTGR Write pending for register GPT_TTGR R 0 |
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346 0x0: Trigger register write not pending |
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347 0x1: Trigger register write pending |
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348 */ |
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349 typedef TSingleBitField<3> T_W_PEND_TTGR ; |
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350 |
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351 /** |
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352 4 W_PEND_TMAR Write pending for register GPT_TMAR R 0 |
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353 0x0: Match register write not pending |
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354 0x1: Match register write pending |
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355 */ |
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356 typedef TSingleBitField<4> T_W_PEND_TMAR; |
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357 |
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358 /** |
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359 5 W_PEND_TPIR Write pending for register GPT_TPIR R 0 |
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360 Reserved for instances 3, 4, 5, 6, 7, 8, 9, 11, 12 Read returns reset value. R 0 |
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361 0x0: Positive increment register write not pending |
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362 0x1: Positive increment register write pending |
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363 */ |
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364 typedef TSingleBitField<5> T_W_PEND_TPIR ; |
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365 |
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366 /** |
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367 6 W_PEND_TNIR Write pending for register GPT_TNIR R 0 |
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368 0x0: Negative increment register write not pending |
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369 0x1: Negative increment register write pending |
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370 Reserved for instances 3, 4, 5, 6, 7, 8, 9, 11, 12 Read returns reset value. R 0 |
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371 */ |
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372 typedef TSingleBitField<6> T_W_PEND_TNIR ; |
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373 |
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374 /** |
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375 7 W_PEND_TCVR Write pending for register GPT_TCVR R 0 |
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376 0x0: Counter value register write not pending |
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377 0x1: Counter value register write pending |
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378 Reserved for instances 3, 4, 5, 6, 7, 8, 9, 11, 12 Read returns reset value. R 0 |
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379 */ |
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380 typedef TSingleBitField<7> T_W_PEND_TCVR ; |
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381 |
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382 /** |
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383 8 W_PEND_TOCR Write pending for register GPT_TOCR R 0 |
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384 0x0: Overflow counter register write not pending |
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385 0x1: Overflow counter register write pending |
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386 Reserved for instances 3, 4, 5, 6, 7, 8, 9, 11, 12 Read returns reset value. R 0 |
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387 */ |
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388 typedef TSingleBitField<8> T_W_PEND_TOCR ; |
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389 |
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390 /** |
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391 9 W_PEND_TOWR Write pending for register GPT_TOWR R 0 |
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392 0x0: Overflow wrapping register write not pending |
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393 0x1: Overflow wrapping register write pending |
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394 Reserved for instances 3, 4, 5, 6, 7, 8, 9, 11, 12 Read returns reset value. R 0 |
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395 */ |
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396 typedef TSingleBitField<9> T_W_PEND_TOWR ; |
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397 |
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398 } ; // namespace TWPS |
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399 |
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400 namespace TSICR |
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401 { |
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402 /** |
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403 1 SFT Reset software functional registers. This bit is automatically reset RW 0 |
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404 by the hardware. During reads, it always returns 0. |
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405 0x0: Normal functional mode |
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406 0x1: The functional registers are reset. |
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407 */ |
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408 typedef TSingleBitField<1> T_SFT ; |
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409 |
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410 /** |
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411 2 POSTED Posted mode selection RW 1 |
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412 0x0: Non-posted mode selected |
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413 0x1: Posted mode selected |
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414 */ |
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415 typedef TSingleBitField<2> T_POSTED ; |
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416 |
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417 } ; // namespace TSICR |
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418 |
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419 namespace TOCR |
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420 { |
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421 /** |
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422 23:0 OVF_COUNTER_VALUE The number of overflow events. RW 0x00000000 |
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423 */ |
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424 class T_OVF_COUNTER_VALUE : public TBitField<0, 24> |
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425 { |
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426 public : |
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427 enum TConstants |
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428 { |
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429 } ; |
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430 } ; |
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431 |
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432 } ; // namespace TOCR |
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433 |
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434 namespace TOWR |
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435 { |
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436 /** |
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437 23:0 OVF_WRAPPING_VALUE The number of masked interrupts. RW 0x00000000 |
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438 */ |
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439 class T_OVF_WRAPPING_VALUE : public TBitField<0, 24> |
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440 { |
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441 public : |
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442 enum TConstants |
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443 { |
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444 } ; |
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445 } ; |
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446 |
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447 } ; // namespace TOWR |
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448 |
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449 enum TBaseAddress |
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450 { |
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451 KGPTIMER1_Base = TVirtual<0x48318000>::Value, |
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452 KGPTIMER2_Base = TVirtual<0x49032000>::Value, |
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453 KGPTIMER3_Base = TVirtual<0x49034000>::Value, |
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454 KGPTIMER4_Base = TVirtual<0x49036000>::Value, |
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455 KGPTIMER5_Base = TVirtual<0x49038000>::Value, |
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456 KGPTIMER6_Base = TVirtual<0x4903A000>::Value, |
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457 KGPTIMER7_Base = TVirtual<0x4903C000>::Value, |
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458 KGPTIMER8_Base = TVirtual<0x4903E000>::Value, |
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459 KGPTIMER9_Base = TVirtual<0x49040000>::Value, |
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460 KGPTIMER10_Base = TVirtual<0x48086000>::Value, |
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461 KGPTIMER11_Base = TVirtual<0x48088000>::Value, |
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462 KGPTIMER12_Base = TVirtual<0x48304000>::Value, |
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463 } ; |
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464 |
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465 enum TTimerNumber |
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466 { |
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467 EGpTimer1, |
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468 EGpTimer2, |
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469 EGpTimer3, |
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470 EGpTimer4, |
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471 EGpTimer5, |
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472 EGpTimer6, |
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473 EGpTimer7, |
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474 EGpTimer8, |
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475 EGpTimer9, |
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476 EGpTimer10, |
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477 EGpTimer11, |
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478 EGpTimer12 |
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479 }; |
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480 |
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481 typedef void (*TTimerIsr)(TAny*) ; |
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482 |
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483 template<const TTimerNumber tImEr> |
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484 struct TTimerTraits |
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485 { |
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486 } ; |
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487 |
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488 template<> |
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489 struct TTimerTraits<EGpTimer1> |
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490 { |
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491 enum TraitValues |
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492 { |
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493 KBaseAddress = KGPTIMER1_Base, |
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494 KIrq = EOmap3530_IRQ37_GPT1_IRQ, |
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495 KClockSelMask = TSingleBitField<7>::KMask, |
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496 KClockSelValue = TSingleBitField<7>::KOn, |
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497 } ; |
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498 } ; |
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499 |
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500 template<> |
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501 struct TTimerTraits<EGpTimer2> |
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502 { |
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503 enum TraitValues |
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504 { |
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505 KBaseAddress = KGPTIMER2_Base, |
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506 KIrq = EOmap3530_IRQ38_GPT2_IRQ, |
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507 } ; |
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508 } ; |
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509 |
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510 template<> |
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511 struct TTimerTraits<EGpTimer3> |
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512 { |
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513 enum TraitValues |
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514 { |
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515 KBaseAddress = KGPTIMER3_Base, |
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516 KIrq = EOmap3530_IRQ39_GPT3_IRQ, |
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517 } ; |
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518 } ; |
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519 |
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520 template<> |
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521 struct TTimerTraits<EGpTimer4> |
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522 { |
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523 enum TraitValues |
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524 { |
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525 KBaseAddress = KGPTIMER4_Base, |
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526 KIrq = EOmap3530_IRQ40_GPT4_IRQ, |
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527 } ; |
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528 } ; |
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529 |
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530 template<> |
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531 struct TTimerTraits<EGpTimer5> |
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532 { |
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533 enum TraitValues |
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534 { |
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535 KBaseAddress = KGPTIMER5_Base, |
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536 KIrq = EOmap3530_IRQ41_GPT5_IRQ, |
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537 } ; |
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538 } ; |
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539 |
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540 template<> |
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541 struct TTimerTraits<EGpTimer6> |
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542 { |
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543 enum TraitValues |
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544 { |
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545 KBaseAddress = KGPTIMER6_Base, |
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546 KIrq = EOmap3530_IRQ42_GPT6_IRQ, |
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547 } ; |
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548 } ; |
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549 |
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550 template<> |
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551 struct TTimerTraits<EGpTimer7> |
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552 { |
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553 enum TraitValues |
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554 { |
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555 KBaseAddress = KGPTIMER7_Base, |
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556 KIrq = EOmap3530_IRQ43_GPT7_IRQ, |
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557 } ; |
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558 } ; |
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559 |
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560 template<> |
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561 struct TTimerTraits<EGpTimer8> |
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562 { |
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563 enum TraitValues |
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564 { |
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565 KBaseAddress = KGPTIMER8_Base, |
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566 KIrq = EOmap3530_IRQ44_GPT8_IRQ, |
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567 } ; |
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568 } ; |
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569 |
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570 template<> |
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571 struct TTimerTraits<EGpTimer9> |
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572 { |
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573 enum TraitValues |
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574 { |
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575 KBaseAddress = KGPTIMER9_Base, |
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576 KIrq = EOmap3530_IRQ45_GPT9_IRQ, |
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577 } ; |
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578 } ; |
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579 |
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580 template<> |
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581 struct TTimerTraits<EGpTimer10> |
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582 { |
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583 enum TraitValues |
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584 { |
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585 KBaseAddress = KGPTIMER10_Base, |
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586 KIrq = EOmap3530_IRQ46_GPT10_IRQ, |
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587 } ; |
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588 } ; |
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589 |
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590 template<> |
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591 struct TTimerTraits<EGpTimer11> |
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592 { |
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593 enum TraitValues |
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594 { |
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595 KBaseAddress = KGPTIMER11_Base, |
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596 KIrq = EOmap3530_IRQ47_GPT11_IRQ, |
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597 } ; |
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598 } ; |
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599 |
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600 template<> |
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601 struct TTimerTraits<EGpTimer12> |
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602 { |
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603 enum TraitValues |
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604 { |
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605 KBaseAddress = KGPTIMER12_Base, |
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606 KIrq = EOmap3530_IRQ95_GPT12_IRQ, |
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607 KClockSelReg = 0, |
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608 KClockSelMask = 0, |
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609 KClockSel32K = 0, |
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610 KClockSelSys = 0, |
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611 KClockSelValue = KClockSel32K |
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612 } ; |
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613 } ; |
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614 |
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615 /** |
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616 An interface template for OMAP3530 General Purpose timer functionality. |
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617 */ |
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618 template <const TTimerNumber tImEr> |
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619 class TGPT |
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620 { |
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621 protected : |
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622 enum TRegisterOffsets |
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623 { |
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624 KTIOCP_CFG_Offset = 0x010, |
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625 KTISTAT_Offset = 0x014, |
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626 KTISR_Offset = 0x018, |
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627 KTIER_Offset = 0x01C, |
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628 KTWER_Offset = 0x020, |
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629 KTCLR_Offset = 0x024, |
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630 KTCRR_Offset = 0x028, |
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631 KTLDR_Offset = 0x02C, |
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632 KTTGR_Offset = 0x030, |
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633 KTWPS_Offset = 0x034, |
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634 KTMAR_Offset = 0x038, |
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635 KTCAR1_Offset = 0x03C, |
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636 KTSICR_Offset = 0x040, |
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637 KTCAR2_Offset = 0x044 |
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638 } ; |
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639 enum TConstants |
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640 { |
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641 KHz = 1000, |
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642 KClockInputFrequency = 32768, |
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643 } ; |
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644 |
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645 public : |
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646 static inline TOmap3530_IRQ Irq() |
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647 { |
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648 return TOmap3530_IRQ(TTimerTraits<tImEr>::KIrq) ; |
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649 } |
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650 static inline TBool CanWriteTCLR() |
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651 { |
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652 return (0 == (iTWPS.Read() & TWPS::T_W_PEND_TCLR::KOn)) ; |
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653 } |
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654 static inline TBool CanWriteTCRR() |
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655 { |
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656 return (0 == (iTWPS.Read() & TWPS::T_W_PEND_TCRR::KOn)) ; |
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657 } |
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658 static inline TBool CanWriteTLDR() |
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659 { |
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660 return (0 == (iTWPS.Read() & TWPS::T_W_PEND_TLDR::KOn)) ; |
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661 } |
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662 static inline TBool CanWriteTTGR() |
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663 { |
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664 return (0 == (iTWPS.Read() & TWPS::T_W_PEND_TTGR::KOn)) ; |
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665 } |
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666 static inline TBool CanWriteTMAR() |
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667 { |
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668 return (0 == (iTWPS.Read() & TWPS::T_W_PEND_TMAR::KOn)) ; |
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669 } |
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670 static inline void Reset() |
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671 { |
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672 iTIOCP_CFG.Write(TIOCP_CFG::T_SOFTRESET::KOn) ; |
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673 } |
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674 static inline TBool ResetComplete() |
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675 { |
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676 return (TISTAT::T_RESETDONE::KOn & iTISTAT.Read()) ; |
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677 } |
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678 static inline TBool WriteOutstanding() |
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679 { |
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680 return (iTWPS.Read()) ; |
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681 } |
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682 |
|
683 public : |
|
684 static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTIOCP_CFG_Offset)> iTIOCP_CFG ; |
|
685 static TReg32_R<(TTimerTraits<tImEr>::KBaseAddress + KTISTAT_Offset)> iTISTAT ; |
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686 static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTISR_Offset)> iTISR ; |
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687 static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTIER_Offset)> iTIER ; |
|
688 static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTWER_Offset)> iTWER ; |
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689 static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTCLR_Offset)> iTCLR ; |
|
690 static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTCRR_Offset)> iTCRR ; |
|
691 static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTLDR_Offset)> iTLDR ; |
|
692 static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTTGR_Offset)> iTTGR ; |
|
693 static TReg32_R<(TTimerTraits<tImEr>::KBaseAddress + KTWPS_Offset)> iTWPS ; |
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694 static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTMAR_Offset)> iTMAR ; |
|
695 static TReg32_R<(TTimerTraits<tImEr>::KBaseAddress + KTCAR1_Offset)> iTCAR1 ; |
|
696 static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTSICR_Offset)> iTSICR ; |
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697 static TReg32_R<(TTimerTraits<tImEr>::KBaseAddress + KTCAR2_Offset)> iTCAR2 ; |
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698 } ; // class TGPTi |
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699 |
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700 /** |
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701 |
|
702 An interface template for OMAP3530 Microsecond aligned timer functionality. |
|
703 Encapsulates the extra registers provided for timers 1, 2 and 10. |
|
704 */ |
|
705 template <const TTimerNumber tImEr> |
|
706 class TMsSyncTimer : public TGPT<tImEr> |
|
707 { |
|
708 using TGPT<tImEr>::iTWPS ; |
|
709 using TGPT<tImEr>::iTLDR ; |
|
710 |
|
711 protected : |
|
712 enum TRegisterOffsets |
|
713 { |
|
714 KTPIR_Offset = 0x048, |
|
715 KTNIR_Offset = 0x04C, |
|
716 KTCVR_Offset = 0x050, |
|
717 KTOCR_Offset = 0x054, |
|
718 KTOWR_Offset = 0x058 |
|
719 } ; |
|
720 |
|
721 public : |
|
722 enum TRegisterValues |
|
723 { |
|
724 KInitialLoad = 0xFFFFFFE0, |
|
725 KInitialPIR = 0x38A40, |
|
726 KInitialNIR = 0xFFF44800 |
|
727 } ; |
|
728 |
|
729 static inline TBool CanWriteTPIR() |
|
730 { |
|
731 return (0 == (iTWPS.Read() & TWPS::T_W_PEND_TPIR::KOn)) ; |
|
732 } |
|
733 static inline TBool CanWriteTNIR() |
|
734 { |
|
735 return (0 == (iTWPS.Read() & TWPS::T_W_PEND_TNIR::KOn)) ; |
|
736 } |
|
737 static inline TBool CanWriteTCVR() |
|
738 { |
|
739 return (0 == (iTWPS.Read() & TWPS::T_W_PEND_TCVR::KOn)) ; |
|
740 } |
|
741 static inline TBool CanWriteTOCR() |
|
742 { |
|
743 return (0 == (iTWPS.Read() & TWPS::T_W_PEND_TOCR::KOn)) ; |
|
744 } |
|
745 static inline TBool CanWriteTOWR() |
|
746 { |
|
747 return (0 == (iTWPS.Read() & TWPS::T_W_PEND_TOWR::KOn)) ; |
|
748 } |
|
749 |
|
750 static inline void ConfigureFor1Ms() |
|
751 { |
|
752 iTLDR.Write( KInitialLoad ); |
|
753 iTPIR.Write( KInitialPIR ); |
|
754 iTNIR.Write( KInitialNIR ); |
|
755 } |
|
756 |
|
757 public : |
|
758 static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTPIR_Offset)> iTPIR ; |
|
759 static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTNIR_Offset)> iTNIR ; |
|
760 static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTCVR_Offset)> iTCVR ; |
|
761 static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTOCR_Offset)> iTOCR ; |
|
762 static TReg32_RW<(TTimerTraits<tImEr>::KBaseAddress + KTOWR_Offset)> iTOWR ; |
|
763 } ; // class TMsSyncTimer |
|
764 |
|
765 |
|
766 } // namespage GPTimer |
|
767 |
|
768 typedef GPTimer::TMsSyncTimer<GPTimer::EGpTimer1> TGpTimer1 ; |
|
769 typedef GPTimer::TMsSyncTimer<GPTimer::EGpTimer2> TGpTimer2 ; |
|
770 typedef GPTimer::TGPT<GPTimer::EGpTimer3> TGpTimer3 ; |
|
771 typedef GPTimer::TGPT<GPTimer::EGpTimer4> TGpTimer4 ; |
|
772 typedef GPTimer::TGPT<GPTimer::EGpTimer5> TGpTimer5 ; |
|
773 typedef GPTimer::TGPT<GPTimer::EGpTimer6> TGpTimer6 ; |
|
774 typedef GPTimer::TGPT<GPTimer::EGpTimer7> TGpTimer7 ; |
|
775 typedef GPTimer::TGPT<GPTimer::EGpTimer8> TGpTimer8 ; |
|
776 typedef GPTimer::TGPT<GPTimer::EGpTimer9> TGpTimer9 ; |
|
777 typedef GPTimer::TMsSyncTimer<GPTimer::EGpTimer10> TGpTimer10 ; |
|
778 typedef GPTimer::TGPT<GPTimer::EGpTimer11> TGpTimer11 ; |
|
779 typedef GPTimer::TGPT<GPTimer::EGpTimer12> TGpTimer12 ; |
|
780 |
|
781 |
|
782 /** |
|
783 An interface template for OMAP3530 32-KHz aligned timer functionality. |
|
784 */ |
|
785 class T32KhzSyncTimer |
|
786 { |
|
787 protected : |
|
788 enum TRegisterAddress |
|
789 { |
|
790 KREG_32KSYNCNT_SYSCONFIG = TVirtual<0x48320004>::Value, |
|
791 KREG_32KSYNCNT_CR = TVirtual<0x48320010>::Value |
|
792 } ; |
|
793 |
|
794 public : |
|
795 static TReg32_RW<KREG_32KSYNCNT_SYSCONFIG> iSysConfig ; |
|
796 static TReg32_R<KREG_32KSYNCNT_CR> iCR ; |
|
797 |
|
798 private : |
|
799 } ; // class TMsSyncTimer |
|
800 |
|
801 } // namespace Omap3530 |
|
802 |
|
803 } // namespace TexasInstruments |
|
804 |
|
805 |
|
806 // **** TEST CODE **** |
|
807 //# define HEADER_OMAP3530_TIMER_H_DO_COMPILE_TIME_CHECK_TESTS 1 |
|
808 # ifdef HEADER_OMAP3530_TIMER_H_DO_COMPILE_TIME_CHECK_TESTS |
|
809 inline void CompileTimeChecks(void) |
|
810 { |
|
811 __ASSERT_COMPILE((TI::Omap3530::GPTimer::TIOCP_CFG::T_IDLEMODE::KSmartIdle == (2 << 3))) ; |
|
812 __ASSERT_COMPILE((TI::Omap3530::GPTimer::TIOCP_CFG::T_CLOCKACTIVITY::KMaintainIfClock == (1 << 8))) ; |
|
813 __ASSERT_COMPILE((TI::Omap3530::GPTimer::KGPTIMER1_Base == (0xC6318000))) ; |
|
814 __ASSERT_COMPILE((0)) ; // Prove that testing is happening |
|
815 } |
|
816 # endif |
|
817 #endif /* ndef HEADER_OMAP3530_TIMER_H_INCLUDED */ |