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1 // Copyright (c) 1994-2009 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of the License "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: |
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14 // omap3530/beagleboard/src/variant.cia |
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15 // |
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16 |
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17 #include <e32cmn.h> |
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18 #include <e32cia.h> |
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19 #include <beagle/iolines.h> |
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20 |
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21 /****************************************************************************** |
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22 * Interrupt handling/dispatch |
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23 ******************************************************************************/ |
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24 __NAKED__ void XIntDispatch(TAny*) |
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25 { |
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26 // Service second-level Variant Interrupts |
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27 // Enter with r0->{Variant int controller base; Handlers;} |
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28 asm("stmfd sp!, {r4,lr} "); |
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29 asm("ldmia r0, {r3,r4} "); // r3=Variant interrupt controller base, r4->handlers |
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30 asm("0: "); |
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31 asm("ldr r0, [r3, #%a0]" : : "i" ((TInt)KHoIntContEnable)); // r0=bitmask with enabled interrupts |
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32 asm("ldr r1, [r3, #%a0]" : : "i" ((TInt)KHoIntContPending)); // r1=bitmask with pending interrupts |
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33 asm("mov r2, #31 "); // int id |
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34 asm("and r0, r0, r1 "); |
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35 asm("bics r0, r0, #0xf8000000 "); // mask unused bits (only 26 2nd-level ints defined) |
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36 asm("ldmeqfd sp!, {r4,pc} "); // if no 2nd level interrupts pending, exit |
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37 asm("cmp r0, #0x00010000 "); |
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38 asm("movcc r0, r0, lsl #16 "); |
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39 asm("subcc r2, r2, #16 "); |
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40 asm("cmp r0, #0x01000000 "); |
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41 asm("movcc r0, r0, lsl #8 "); |
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42 asm("subcc r2, r2, #8 "); |
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43 asm("cmp r0, #0x10000000 "); |
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44 asm("movcc r0, r0, lsl #4 "); |
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45 asm("subcc r2, r2, #4 "); |
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46 asm("cmp r0, #0x40000000 "); |
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47 asm("movcc r0, r0, lsl #2 "); |
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48 asm("subcc r2, r2, #2 "); |
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49 asm("cmp r0, #0x80000000 "); |
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50 asm("subcc r2, r2, #1 "); // r2=bit no. of MS 1 |
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51 asm("add r0, r4, r2, lsl #3 "); // r0->handler for this interrupt |
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52 asm("adr lr, 0b "); // look again after calling handler |
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53 asm("ldmia r0, {r0,pc} "); // jump to handler |
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54 } |
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55 |
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56 __NAKED__ void ArmWaitForInterrupt() |
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57 { |
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58 //ARM_WFI; |
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59 asm(".word %a0" : : "i" ((TInt)(0x0320f003 | ((14)<<28) )) ) |
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60 asm(" bx lr"); |
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61 } |
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62 |
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63 |