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1 // Copyright (c) 1994-2009 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of the License "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: |
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14 // omap3530/omap3530_drivers/gpio/gpio_interrupts.cpp |
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15 // |
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16 |
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17 #include <e32cmn.h> |
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18 #include <nk_priv.h> |
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19 #include <assp/omap3530_assp/omap3530_gpio.h> |
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20 #include <assp/omap3530_assp/omap3530_irqmap.h> |
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21 #include <assp/omap3530_assp/omap3530_ktrace.h> |
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22 #include <assp/omap3530_assp/omap3530_assp_priv.h> |
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23 #include <assp/omap3530_assp/locks.h> |
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24 |
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25 NONSHARABLE_CLASS( TGpioDispatcher ) : public MInterruptDispatcher |
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26 { |
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27 public: |
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28 TGpioDispatcher(); |
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29 |
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30 TInt Init(); |
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31 |
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32 virtual TInt Bind(TInt aId, TIsr aIsr, TAny* aPtr); |
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33 virtual TInt Unbind(TInt aId); |
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34 virtual TInt Enable(TInt aId); |
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35 virtual TInt Disable(TInt aId); |
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36 virtual TInt Clear(TInt aId); |
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37 virtual TInt SetPriority(TInt aId, TInt aPriority); |
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38 |
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39 private: |
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40 static void Spurious( TAny* aParam ); |
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41 static void DispatchIsr( TAny* aParam ); |
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42 |
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43 static TInt GetGPIOPin( TInt aId,GpioPin *aPin ); |
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44 static TInt SetGPIOPin(TInt aId,GpioPin *aPin); |
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45 |
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46 static FORCE_INLINE TBool IsValidId( TInt aId ); |
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47 }; |
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48 |
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49 TSpinLock GPIOpinsDescLock(/*TSpinLock::EOrderGenericIrqLow0*/); |
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50 static GpioPin GpioPins[KHwGpioPinMax]; |
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51 |
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52 |
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53 TGpioDispatcher::TGpioDispatcher() |
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54 { |
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55 for (TInt32 i = 0; i < KHwGpioPinMax; i++) |
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56 { |
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57 GpioPins[i].iMode = GPIO::EIdle; |
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58 GpioPins[i].irq.iIsr = Spurious; |
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59 GpioPins[i].irq.iPtr = &GpioPins[i]; |
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60 GpioPins[i].iBankAddr = GPIO_BASE_ADDRESS(i); |
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61 GpioPins[i].iBank = i / KHwGpioPinsPerBank; |
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62 GpioPins[i].iIrqVector = EOmap3530_IRQ29_GPIO1_MPU_IRQ +GpioPins[i].iBank; |
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63 } |
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64 } |
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65 |
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66 |
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67 TInt TGpioDispatcher::Init() |
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68 { |
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69 for(TInt i=0; i < KHwGpioBanks; i++) |
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70 { |
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71 TInt r = Interrupt::Bind(EOmap3530_IRQ29_GPIO1_MPU_IRQ+i,DispatchIsr,(TAny*) i); |
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72 // Pass in a pointer to the first pin in the bank - shouldn't use addition on the constant here |
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73 __ASSERT_ALWAYS(r==KErrNone,Kern::Fault("ExternalInterrupt::%s Cant Bind to %d",EOmap3530_IRQ29_GPIO1_MPU_IRQ+i)); |
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74 } |
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75 |
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76 Register( EIrqRangeBaseGpio ); |
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77 |
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78 return KErrNone; |
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79 } |
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80 |
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81 |
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82 |
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83 TInt TGpioDispatcher::GetGPIOPin(TInt aId,GpioPin *aPin) |
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84 { |
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85 |
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86 if(! ( aId >= 0 && aId < KHwGpioPinMax) ) |
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87 return KErrArgument; |
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88 |
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89 TInt irq = /*NKern::DisableAllInterrupts();*/__SPIN_LOCK_IRQSAVE_R(GPIOpinsDescLock); |
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90 memcpy(aPin,&GpioPins[aId],sizeof(GpioPin)); |
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91 /*NKern::RestoreInterrupts(irq);*/__SPIN_UNLOCK_IRQRESTORE_R(GPIOpinsDescLock,irq); |
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92 |
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93 return KErrNone; |
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94 } |
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95 |
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96 TInt TGpioDispatcher::SetGPIOPin(TInt aId,GpioPin *aPin) |
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97 { |
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98 |
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99 if(! ( aId >= 0 && aId < KHwGpioPinMax) ) |
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100 return KErrArgument; |
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101 |
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102 TInt irq = /*NKern::DisableAllInterrupts();*/__SPIN_LOCK_IRQSAVE_W(GPIOpinsDescLock); |
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103 memcpy(&GpioPins[aId],aPin,sizeof(GpioPin )); |
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104 /*NKern::RestoreInterrupts(irq);*/__SPIN_UNLOCK_IRQRESTORE_W(GPIOpinsDescLock,irq); |
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105 |
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106 return KErrNone; |
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107 } |
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108 |
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109 FORCE_INLINE TBool TGpioDispatcher::IsValidId( TInt aId ) |
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110 { |
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111 return ((TUint)aId < EGPIOIRQ_END && (TUint)aId>=EGPIOIRQ_FIRST); |
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112 } |
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113 |
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114 |
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115 void TGpioDispatcher::Spurious(TAny* aId) |
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116 { |
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117 Kern::Fault("SpuriousExtInt",(TInt)aId); |
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118 } |
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119 |
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120 |
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121 void TGpioDispatcher::DispatchIsr(TAny *aPtr) |
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122 { |
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123 Interrupt::Disable(EOmap3530_IRQ29_GPIO1_MPU_IRQ + (TInt) aPtr); |
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124 |
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125 //need to spinlock the gpio here..... |
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126 TUint32 highVectors = AsspRegister::Read32(KGPIO_BASE_ADDRESSES[(TInt) aPtr] + KGPIO_IRQSTATUS1); |
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127 AsspRegister::Write32(KGPIO_BASE_ADDRESSES[(TInt) aPtr] + KGPIO_IRQSTATUS1, highVectors); |
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128 |
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129 GpioPin pin; |
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130 for (TInt i = 0; i < KHwGpioPinsPerBank ; i++,highVectors >>=1) |
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131 { |
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132 if(highVectors & 0x1) |
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133 { |
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134 GetGPIOPin(i+(TInt)aPtr*KHwGpioPinsPerBank, &pin); |
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135 (*pin.irq.iIsr)(pin.irq.iPtr); // dispatch this pin's ISR |
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136 } |
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137 } |
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138 Interrupt::Enable(EOmap3530_IRQ29_GPIO1_MPU_IRQ + (TInt)aPtr); |
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139 } |
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140 |
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141 |
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142 TInt TGpioDispatcher::Bind(TInt anId, TIsr anIsr, TAny* aPtr) |
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143 { |
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144 if(IsValidId(anId)) |
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145 { |
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146 //we want to bind the callers isrfunc to the pin dispatch here |
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147 GpioPin pin; |
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148 GetGPIOPin(anId- EGPIOIRQ_FIRST,&pin); |
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149 pin.irq.iIsr = anIsr; |
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150 pin.irq.iPtr = aPtr; |
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151 SetGPIOPin(anId- EGPIOIRQ_FIRST,&pin); |
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152 return KErrNone; |
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153 } |
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154 else |
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155 { |
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156 return KErrArgument; |
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157 } |
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158 } |
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159 |
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160 TInt TGpioDispatcher::Unbind(TInt anId) |
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161 { |
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162 __KTRACE_OPT(KGPIO,Kern::Printf("GPIO:%s id=%d",__FUNCTION__,anId)); |
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163 |
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164 if(IsValidId(anId)) |
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165 { |
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166 GpioPin pin; |
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167 TInt pinNr = anId - EGPIOIRQ_FIRST; |
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168 GetGPIOPin(pinNr,&pin); |
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169 pin.irq.iIsr=Spurious; |
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170 pin.irq.iPtr=NULL; |
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171 SetGPIOPin(pinNr,&pin); |
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172 return KErrNone; |
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173 } |
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174 else |
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175 { |
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176 return KErrArgument; |
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177 } |
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178 } |
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179 |
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180 |
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181 TInt TGpioDispatcher::Enable(TInt anId) |
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182 { |
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183 __KTRACE_OPT(KGPIO,Kern::Printf("GPIO:%s id=%d +",__FUNCTION__,anId)); |
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184 CHECK_PRECONDITIONS(MASK_NO_FAST_MUTEX,"GPIO::InterruptEnable Cant Hold Mutex in Blocking function"); |
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185 |
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186 if(IsValidId(anId)) |
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187 { |
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188 GpioPin pin; |
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189 TInt pinNr = anId - EGPIOIRQ_FIRST; |
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190 GetGPIOPin(pinNr,&pin); |
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191 |
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192 if(Spurious == pin.irq.iIsr) |
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193 { |
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194 |
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195 __KTRACE_OPT(KGPIO,Kern::Printf("GPIO:%s id=%d NOT BOUND",__FUNCTION__,anId)); |
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196 return KErrNotReady; |
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197 } |
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198 AsspRegister::Write32(pin.iBankAddr+KGPIO_SETIRQENABLE1,GPIO_PIN_OFFSET( pinNr)); |
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199 |
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200 if(!Omap3530Interrupt::IsInterruptEnabled(pin.iIrqVector)) |
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201 Interrupt::Enable(pin.iIrqVector); |
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202 |
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203 return KErrNone; |
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204 } |
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205 else |
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206 { |
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207 return KErrArgument; |
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208 } |
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209 } |
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210 |
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211 TInt TGpioDispatcher::Disable(TInt anId) |
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212 { |
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213 |
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214 __KTRACE_OPT(KGPIO,Kern::Printf("GPIO:%s id=%d",__FUNCTION__,anId)); |
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215 CHECK_PRECONDITIONS(MASK_NO_FAST_MUTEX,"GPIO::InterruptDisable Cant Hold Mutex in Blocking function"); |
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216 if(IsValidId(anId)) |
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217 { |
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218 TInt pinNr = anId- EGPIOIRQ_FIRST; |
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219 GpioPin pin; |
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220 GetGPIOPin(pinNr, &pin); |
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221 |
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222 AsspRegister::Write32(pin.iBankAddr+KGPIO_CLEARIRQENABLE1, GPIO_PIN_OFFSET(pinNr)); |
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223 |
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224 //is this the last one for this bank ? then unmap |
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225 if(0x00 == AsspRegister::Read32(pin.iBankAddr+KGPIO_IRQENABLE1)) |
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226 { |
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227 Interrupt::Disable(pin.iIrqVector); |
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228 } |
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229 return KErrNone; |
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230 } |
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231 else |
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232 { |
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233 return KErrArgument; |
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234 } |
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235 } |
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236 |
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237 TInt TGpioDispatcher::Clear(TInt anId) |
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238 { |
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239 |
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240 __KTRACE_OPT(KGPIO,Kern::Printf("GPIO:%s id=%d",__FUNCTION__,anId)); |
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241 CHECK_PRECONDITIONS(MASK_NO_FAST_MUTEX,"GPIO::InterruptDisable Cant Hold Mutex in Blocking function"); |
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242 |
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243 if(IsValidId(anId)) |
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244 { |
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245 TInt pinNr = anId- EGPIOIRQ_FIRST; |
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246 GpioPin myPin; |
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247 GetGPIOPin(pinNr, &myPin); |
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248 |
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249 AsspRegister::Write32((myPin.iBankAddr+KGPIO_IRQSTATUS1), GPIO_PIN_OFFSET(pinNr)); |
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250 //if that was the only high bit clear the mainline as well |
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251 if(0 == AsspRegister::Read32(myPin.iBankAddr+KGPIO_IRQSTATUS1)) |
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252 { |
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253 Interrupt::Clear(myPin.iIrqVector); |
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254 } |
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255 } |
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256 return KErrNone; |
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257 } |
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258 |
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259 TInt TGpioDispatcher::SetPriority(TInt aId, TInt aPriority) |
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260 { |
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261 return KErrNotSupported; |
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262 } |
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263 |
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264 |
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265 GLDEF_C TInt InitGpioInterrupts() |
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266 { |
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267 TInt r = KErrNoMemory; |
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268 |
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269 TGpioDispatcher* dispatcher = new TGpioDispatcher; |
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270 if( dispatcher ) |
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271 { |
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272 r = dispatcher->Init(); |
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273 } |
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274 return r; |
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275 } |