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1 // Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of the License "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: |
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14 // omap3530/assp/test/t_i2c.cpp |
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15 // Test code for I2C Driver |
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16 // This file is part of the Beagle Base port |
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17 // |
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18 |
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19 #include <assp/omap3530_assp/omap3530_i2creg.h> |
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20 |
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21 #include <kernel.h> |
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22 #include <nk_priv.h> |
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23 #include <assp.h> |
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24 |
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25 DECLARE_STANDARD_EXTENSION() |
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26 { |
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27 _LIT(K, "T_I2C"); |
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28 |
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29 TDynamicDfcQue* dfcQueue; |
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30 TInt r = Kern::DynamicDfcQCreate(dfcQueue, 24, K); |
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31 __NK_ASSERT_ALWAYS(r == KErrNone); |
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32 |
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33 I2c::TConfigPb ccb; |
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34 ccb.iUnit = I2c::E1; |
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35 ccb.iRole = I2c::EMaster; |
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36 ccb.iMode = I2c::E7Bit; |
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37 ccb.iExclusiveClient = (void*) InitExtension; |
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38 ccb.iRate = I2c::E400K; |
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39 ccb.iOwnAddress = 0x01; |
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40 ccb.iDfcQueue = dfcQueue; |
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41 ccb.iDeviceAddress = 0x4b; |
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42 I2c::THandle h4b = I2c::Open(ccb); |
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43 __NK_ASSERT_ALWAYS(h4b >= KErrNone); |
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44 |
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45 ccb.iDeviceAddress = 0x49; |
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46 I2c::THandle h49 = I2c::Open(ccb); |
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47 __NK_ASSERT_ALWAYS(h49 >= KErrNone); |
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48 |
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49 ccb.iUnit = I2c::E3; |
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50 ccb.iRate = I2c::E100K; |
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51 ccb.iDeviceAddress = 0x50; |
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52 I2c::THandle hEdid = I2c::Open(ccb); |
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53 __NK_ASSERT_ALWAYS(hEdid >= KErrNone); |
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54 |
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55 const TUint8 KTotalRead = 128; |
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56 const TUint8 KReadPerTransfer = 16; |
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57 |
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58 I2c::TTransferPb addressPhase; |
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59 addressPhase.iType = I2c::TTransferPb::EWrite; |
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60 addressPhase.iLength = 1; |
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61 |
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62 I2c::TTransferPb dataPhase; |
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63 dataPhase.iType = I2c::TTransferPb::ERead; |
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64 dataPhase.iLength = KReadPerTransfer; |
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65 |
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66 addressPhase.iNextPhase = &dataPhase; // a two phase transfer |
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67 |
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68 TUint8 data[128]; |
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69 |
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70 for (TUint8 address = 0; address < KTotalRead; address += KReadPerTransfer) |
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71 { |
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72 addressPhase.iData = &address; |
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73 dataPhase.iData = &data[address]; |
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74 |
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75 r = I2c::TransferS(hEdid, addressPhase); |
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76 if (r != KErrNone) |
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77 { |
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78 Kern::Printf("*** Check that the DVI cable is connected ***"); |
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79 break; |
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80 } |
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81 } |
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82 |
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83 I2c::Close(hEdid); |
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84 |
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85 for (TInt i = 0; i < KTotalRead; i += 16) |
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86 { |
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87 Kern::Printf("%02x: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", |
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88 i, data[i + 0], data[i + 1], data[i + 2], data[i + 3], data[i + 4], data[i + 5], data[i + 6], data[i + 7], |
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89 data[i + 8], data[i + 9], data[i + 10], data[i + 11], data[i + 12], data[i + 13], data[i + 14], data[i + 15]); |
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90 } |
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91 |
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92 TUint8 rd = I2cReg::ReadB(h4b, 0x7a); Kern::Printf("expect 0x20:%d", rd); |
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93 rd = I2cReg::ReadB(h4b, 0x7a); Kern::Printf("expect 0x03:%d", rd); |
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94 rd = I2cReg::ReadB(h4b, 0x8E); Kern::Printf("expect 0xE0:%d", rd); |
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95 rd = I2cReg::ReadB(h4b, 0x91); Kern::Printf("expect 0x05:%d", rd); |
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96 rd = I2cReg::ReadB(h49, 0x01); Kern::Printf("expect 0x03:%d", rd); |
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97 rd = I2cReg::ReadB(h49, 0x02); Kern::Printf("expect 0xc0:%d", rd); |
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98 rd = I2cReg::ReadB(h49, 0x03); Kern::Printf("expect 0x00:%d", rd); |
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99 rd = I2cReg::ReadB(h49, 0x04); Kern::Printf("expect 0x00:%d", rd); |
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100 rd = I2cReg::ReadB(h49, 0x05); Kern::Printf("expect 0x00:%d", rd); |
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101 rd = I2cReg::ReadB(h49, 0x06); Kern::Printf("expect 0x00:%d", rd); |
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102 rd = I2cReg::ReadB(h49, 0x07); Kern::Printf("expect 0x00:%d", rd); |
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103 rd = I2cReg::ReadB(h49, 0x08); Kern::Printf("expect 0x00:%d", rd); |
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104 rd = I2cReg::ReadB(h49, 0x09); Kern::Printf("expect 0x00:%d", rd); |
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105 rd = I2cReg::ReadB(h49, 0x0a); Kern::Printf("expect 0x00:%d", rd); |
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106 rd = I2cReg::ReadB(h49, 0x0b); Kern::Printf("expect 0x00:%d", rd); |
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107 rd = I2cReg::ReadB(h49, 0x0c); Kern::Printf("expect 0x00:%d", rd); |
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108 rd = I2cReg::ReadB(h49, 0x0d); Kern::Printf("expect 0x00:%d", rd); |
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109 rd = I2cReg::ReadB(h49, 0x0e); Kern::Printf("expect 0x00:%d", rd); |
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110 rd = I2cReg::ReadB(h49, 0x0f); Kern::Printf("expect 0x00:%d", rd); |
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111 rd = I2cReg::ReadB(h49, 0x10); Kern::Printf("expect 0x00:%d", rd); |
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112 rd = I2cReg::ReadB(h49, 0x11); Kern::Printf("expect 0x00:%d", rd); |
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113 rd = I2cReg::ReadB(h49, 0x12); Kern::Printf("expect 0x6c:%d", rd); |
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114 rd = I2cReg::ReadB(h49, 0x13); Kern::Printf("expect 0x6c:%d", rd); |
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115 rd = I2cReg::ReadB(h49, 0x14); Kern::Printf("expect 0x00:%d", rd); |
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116 rd = I2cReg::ReadB(h49, 0x15); Kern::Printf("expect 0x00:%d", rd); |
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117 rd = I2cReg::ReadB(h49, 0x16); Kern::Printf("expect 0x00:%d", rd); |
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118 rd = I2cReg::ReadB(h49, 0x17); Kern::Printf("expect 0x0c:%d", rd); |
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119 rd = I2cReg::ReadB(h49, 0x18); Kern::Printf("expect 0x00:%d", rd); |
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120 rd = I2cReg::ReadB(h49, 0x19); Kern::Printf("expect 0x00:%d", rd); |
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121 rd = I2cReg::ReadB(h49, 0x1a); Kern::Printf("expect 0x00:%d", rd); |
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122 rd = I2cReg::ReadB(h49, 0x1b); Kern::Printf("expect 0x2b:%d", rd); |
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123 rd = I2cReg::ReadB(h49, 0x1c); Kern::Printf("expect 0x2b:%d", rd); |
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124 rd = I2cReg::ReadB(h49, 0x1d); Kern::Printf("expect 0x00:%d", rd); |
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125 rd = I2cReg::ReadB(h49, 0x1e); Kern::Printf("expect 0x00:%d", rd); |
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126 rd = I2cReg::ReadB(h49, 0x1f); Kern::Printf("expect 0x00:%d", rd); |
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127 rd = I2cReg::ReadB(h49, 0x20); Kern::Printf("expect 0x00:%d", rd); |
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128 rd = I2cReg::ReadB(h49, 0x21); Kern::Printf("expect 0x00:%d", rd); |
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129 rd = I2cReg::ReadB(h49, 0x22); Kern::Printf("expect 0x24:%d", rd); |
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130 rd = I2cReg::ReadB(h49, 0x23); Kern::Printf("expect 0x0a:%d", rd); |
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131 rd = I2cReg::ReadB(h49, 0x24); Kern::Printf("expect 0x42:%d", rd); |
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132 rd = I2cReg::ReadB(h49, 0x25); Kern::Printf("expect 0x00:%d", rd); |
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133 |
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134 rd = I2cReg::ReadB(h4b, 0x29); Kern::Printf("RTC_CTRL_REG:%d", rd); |
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135 rd = I2cReg::ReadB(h4b, 0x2a); Kern::Printf("RTC_STATUS_REG:%d", rd); |
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136 I2cReg::WriteB(h4b, 0x2a, 0x80); |
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137 rd = I2cReg::ReadB(h4b, 0x2a); Kern::Printf("RTC_STATUS_REG:%d", rd); |
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138 |
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139 rd = I2cReg::ReadB(h4b, 0x29); Kern::Printf("RTC_CTRL_REG:%d", rd); |
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140 I2cReg::WriteB(h4b, 0x29, 0x01); |
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141 rd = I2cReg::ReadB(h4b, 0x3f); Kern::Printf("CFG_PWRANA2:%d", rd); |
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142 |
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143 Kern::Printf("RTC_CTRL_REG:%d", rd); |
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144 rd = I2cReg::ReadB(h4b, 0x2a); Kern::Printf("RTC_STATUS_REG:%d", rd); |
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145 |
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146 rd = I2cReg::ReadB(h4b, 0x1c); Kern::Printf("SECONDS_REG:%d", rd); |
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147 rd = I2cReg::ReadB(h4b, 0x1d); Kern::Printf("MINUTES_REG:%d", rd); |
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148 rd = I2cReg::ReadB(h4b, 0x1e); Kern::Printf("HOURS_REG:%d", rd); |
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149 rd = I2cReg::ReadB(h4b, 0x1f); Kern::Printf("DAYS_REG:%d", rd); |
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150 rd = I2cReg::ReadB(h4b, 0x20); Kern::Printf("MONTHS_REG:%d", rd); |
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151 rd = I2cReg::ReadB(h4b, 0x21); Kern::Printf("YEARS_REG:%d", rd); |
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152 rd = I2cReg::ReadB(h4b, 0x22); Kern::Printf("WEEKS_REG:%d", rd); |
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153 rd = I2cReg::ReadB(h4b, 0x23); Kern::Printf("ALARM_SECONDS_REG:%d", rd); |
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154 rd = I2cReg::ReadB(h4b, 0x24); Kern::Printf("ALARM_MINUTES_REG:%d", rd); |
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155 rd = I2cReg::ReadB(h4b, 0x25); Kern::Printf("ALARM_HOURS_REG:%d", rd); |
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156 rd = I2cReg::ReadB(h4b, 0x26); Kern::Printf("ALARM_DAYS_REG:%d", rd); |
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157 rd = I2cReg::ReadB(h4b, 0x27); Kern::Printf("ALARM_MONTHS_REG:%d", rd); |
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158 rd = I2cReg::ReadB(h4b, 0x28); Kern::Printf("ALARM_YEARS_REG:%d", rd); |
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159 rd = I2cReg::ReadB(h4b, 0x29); Kern::Printf("RTC_CTRL_REG:%d", rd); |
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160 rd = I2cReg::ReadB(h4b, 0x2a); Kern::Printf("RTC_STATUS_REG:%d", rd); |
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161 rd = I2cReg::ReadB(h4b, 0x2b); Kern::Printf("RTC_INTERRUPTS_REG:%d", rd); |
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162 rd = I2cReg::ReadB(h4b, 0x2c); Kern::Printf("RTC_COMP_LSB_REG:%d", rd); |
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163 rd = I2cReg::ReadB(h4b, 0x2d); Kern::Printf("RTC_COMP_MSB_REG:%d", rd); |
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164 |
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165 TUint8 ctrl = I2cReg::ReadB(h4b, 0x29); |
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166 ctrl &= ~0x01; |
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167 I2cReg::WriteB(h4b, 0x29, ctrl); |
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168 ctrl = I2cReg::ReadB(h4b, 0x29); Kern::Printf("RTC_CTRL_REG:%d", ctrl); |
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169 |
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170 I2cReg::WriteB(h4b, 0x28, 0x08); |
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171 I2cReg::WriteB(h4b, 0x27, 0x12); |
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172 I2cReg::WriteB(h4b, 0x26, 0x17); |
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173 I2cReg::WriteB(h4b, 0x25, 0x10); |
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174 I2cReg::WriteB(h4b, 0x24, 0x00); |
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175 I2cReg::WriteB(h4b, 0x23, 0x00); |
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176 I2cReg::WriteB(h4b, 0x22, 0x00); |
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177 I2cReg::WriteB(h4b, 0x21, 0x08); |
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178 I2cReg::WriteB(h4b, 0x20, 0x12); |
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179 I2cReg::WriteB(h4b, 0x1f, 0x16); |
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180 I2cReg::WriteB(h4b, 0x1e, 0x10); |
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181 I2cReg::WriteB(h4b, 0x1d, 0x17); |
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182 I2cReg::WriteB(h4b, 0x1c, 0x30); |
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183 |
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184 ctrl |= 0x01; |
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185 I2cReg::WriteB(h4b, 0x29, ctrl); |
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186 ctrl = I2cReg::ReadB(h4b, 0x29); Kern::Printf("RTC_CTRL_REG:%d", ctrl); |
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187 |
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188 NKern::Sleep(2000); |
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189 |
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190 rd = I2cReg::ReadB(h4b, 0x2a); Kern::Printf("RTC_STATUS_REG:%d", rd); |
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191 |
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192 ctrl |= 0x40; |
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193 I2cReg::WriteB(h4b, 0x29, ctrl); |
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194 ctrl = I2cReg::ReadB(h4b, 0x29); Kern::Printf("RTC_CTRL_REG:%d", ctrl); |
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195 |
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196 rd = I2cReg::ReadB(h4b, 0x1c); Kern::Printf("SECONDS_REG:%d", rd); |
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197 rd = I2cReg::ReadB(h4b, 0x1d); Kern::Printf("MINUTES_REG:%d", rd); |
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198 rd = I2cReg::ReadB(h4b, 0x1e); Kern::Printf("HOURS_REG:%d", rd); |
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199 rd = I2cReg::ReadB(h4b, 0x1f); Kern::Printf("DAYS_REG:%d", rd); |
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200 rd = I2cReg::ReadB(h4b, 0x20); Kern::Printf("MONTHS_REG:%d", rd); |
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201 rd = I2cReg::ReadB(h4b, 0x21); Kern::Printf("YEARS_REG:%d", rd); |
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202 rd = I2cReg::ReadB(h4b, 0x22); Kern::Printf("WEEKS_REG:%d", rd); |
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203 rd = I2cReg::ReadB(h4b, 0x23); Kern::Printf("ALARM_SECONDS_REG:%d", rd); |
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204 rd = I2cReg::ReadB(h4b, 0x24); Kern::Printf("ALARM_MINUTES_REG:%d", rd); |
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205 rd = I2cReg::ReadB(h4b, 0x25); Kern::Printf("ALARM_HOURS_REG:%d", rd); |
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206 rd = I2cReg::ReadB(h4b, 0x26); Kern::Printf("ALARM_DAYS_REG:%d", rd); |
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207 rd = I2cReg::ReadB(h4b, 0x27); Kern::Printf("ALARM_MONTHS_REG:%d", rd); |
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208 rd = I2cReg::ReadB(h4b, 0x28); Kern::Printf("ALARM_YEARS_REG:%d", rd); |
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209 rd = I2cReg::ReadB(h4b, 0x29); Kern::Printf("RTC_CTRL_REG:%d", rd); |
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210 rd = I2cReg::ReadB(h4b, 0x2a); Kern::Printf("RTC_STATUS_REG:%d", rd); |
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211 rd = I2cReg::ReadB(h4b, 0x2b); Kern::Printf("RTC_INTERRUPTS_REG:%d", rd); |
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212 rd = I2cReg::ReadB(h4b, 0x2c); Kern::Printf("RTC_COMP_LSB_REG:%d", rd); |
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213 rd = I2cReg::ReadB(h4b, 0x2d); Kern::Printf("RTC_COMP_MSB_REG:%d", rd); |
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214 |
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215 I2c::Close(h4b); |
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216 I2c::Close(h49); |
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217 dfcQueue->Destroy(); |
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218 |
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219 return KErrNone; |
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220 } |