1 // Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies).

     2 // All rights reserved.

     3 // This component and the accompanying materials are made available

     4 // under the terms of the License "Eclipse Public License v1.0"

     5 // which accompanies this distribution, and is available

     6 // at the URL "http://www.eclipse.org/legal/epl-v10.html".

     7 //

     8 // Initial Contributors:

     9 // Nokia Corporation - initial contribution.

    10 //

    11 // Contributors:

    12 //

    13 // Description:

    14 // \omap3530\omap3530_assp\prcm.h

    15 // Access to PRCM.

    16 // This file is part of the Beagle Base port

    17 //

    18 

    19 #ifndef PRCM_H__

    20 #define PRCM_H__

    21 

    22 #include <e32cmn.h>

    23 #include <assp/omap3530_assp/omap3530_irqmap.h>

    24 

    25 namespace Prcm

    26 {

    27 enum TPanic

    28 	{

    29 	ESetPllConfigBadPll,	///< bad PLL ID in SetPllConfiguration()

    30 	EGetPllConfigBadPll,	///< bad PLL ID in PllConfiguration()

    31 	ESetPllConfigBadFreqRange,	///< bad PLL frequency range in SetPllConfiguration()

    32 	ESetPllConfigBadRamp,		///< bad PLL ramp setting in SetPllConfiguration()

    33 	ESetPllConfigBadDrift,		///< bad PLL drift setting in SetPllConfiguration()

    34 	ESetPllConfigBadDivider,	///< bad divider setting in SetPllConfiguration()

    35 	ESetPllConfigBadMultiplier,	///< bad divider setting in SetPllConfiguration()

    36 	ESetPllLpBadPll,		///< bad PLL ID in SetPllLp()

    37 	EGetPllLpBadPll,		///< bad PLL ID in PllLp()

    38 	ESetPllLpBadMode,		///< bad PLL LP mode in SetPllLp()

    39 	ESetDividerBadClock,	///< bad clock ID in SetDivider()

    40 	EGetDividerBadClock,	///< bad clock ID in Divider()

    41 	ESetStateBadClock,		///< bad clock ID in SetClockState()

    42 	ESetWakeupBadClock,		///< bad clock ID in SetWakeupMode()

    43 	ESetPllModeBadClock,

    44 	ESetPllModeBadMode,

    45 	EGetStateBadClock,		///< bad clock ID in ClockState()

    46 	EGetWakeupBadClock,		///< bad clock ID in WakeupMode()

    47 	ESetGptClockBadGpt,		///< bad GPT ID in SetGptClockSource()

    48 	EGetWakeupGroupBadClock,

    49 	EGetWakeupGroupBadGroup,

    50 	EAddWakeupGroupBadClock,

    51 	EAddWakeupGroupBadGroup,

    52 	ERemoveWakeupGroupBadClock,

    53 	ERemoveWakeupGroupBadGroup,

    54 	EAddDomainBadClock,		///< bad clock in call to AddToWakeupDomain()

    55 	ERemoveDomainBadClock,	///< bad clock in call to RemoveFromWakeupDomain()

    56 	ECheckDomainBadClock,	///< bad clock in call to IsInWakeupDomain()

    57 	EAddDomainBadDomain,	///< bad domain in call to AddToWakeupDomain()

    58 	ERemoveDomainBadDomain,	///< bad domain in call to RemoveFromWakeupDomain()

    59 	ECheckDomainBadDomain,	///< bad domain in call to IsInWakeupDomain()

    60 	ESetDividerUnsupportedClock,	///< attempt to set divider on clock that does not have divider

    61 	ESetDividerBadDivider,	///< bad divider value in SetDivider()

    62 	EGetNameBadClock,		///< bad clock ID in PrmName()

    63 	EClockFrequencyBadClock,	///< bad clock ID in ClockFrequency()

    64 	ESetClockMuxBadClock,	///< bad clock ID in SetClockMux()

    65 	ESetClockMuxBadSource,	///< bad source clock ID in SetClockMux()

    66 	EGetClockMuxBadClock,	///< bad clock ID in ClockMux()

    67 	ESetDomainModeBadDomain,	///< bad domain in SetPowerDomainMode()

    68 	ESetDomainModeBadMode,		///< bad mode in SetPowerDomainMode()

    69 	EGetDomainModeBadDomain,	///< bad domain in PowerDomainMode()

    70 	ESetDomainModeUnsupportedMode,	///< mode requested in SetPowerDomainMode() not supported by that domain

    71 	EPllIsLockedBadPll,			///< bad PLL ID in PllIsLocked()

    72 	EWaitForPllLockBadPll,		///< bad PLL ID in WaitForPllLocked()

    73 	ESetPllBypassDividerBadPll,	///< bad PLL ID in SetPllBypassDivider()

    74 	EPllBypassDividerBadPll,		///< bad PLL ID in PllBypassDivider()

    75 	ESetPllBypassDividerBadDivider,	///< bad dividier value in SetPllBypassDivider()

    76 	EPllInternalFrequencyOutOfRange	///< PLL internal frequency out of range in AutoSetPllFrequencyRange()

    77 	};

    78 

    79 enum TClock

    80 	{

    81 	EClkMpu,		///< DPLL1

    82 	EClkIva2Pll,	///< DPLL2

    83 	EClkCore,		///< DPLL3

    84 	EClkPeriph,		///< DPLL4

    85 	EClkPeriph2,	///< DPLL5

    86 

    87 	EClkPrcmInterface,

    88 

    89 	EClkEmu,		///< Emulation clock

    90 	EClkNeon,

    91 

    92 	EClkL3Domain,

    93 	EClkL4Domain,

    94 

    95 	EClkMpuPll_Bypass,	///< DPLL1 bypass frequency

    96 	EClkIva2Pll_Bypass,	///< DPLL2 bypass frequency

    97 	EClkRM_F,			///< Reset manager functional clock	

    98 	EClk96M,			///< 96MHz clock

    99 	EClk120M,			///< 120MHz clock

   100 	EClkSysOut,

   101 

   102 	// Functional clocks

   103 	EClkTv_F,			///< TV functional clock, same as 54MHz FCLK

   104 	EClkDss1_F,

   105 	EClkDss2_F,

   106 	EClkCsi2_F,

   107 	EClkCam_F,

   108 	EClkIva2_F,

   109 	EClkMmc1_F,

   110 	EClkMmc2_F,

   111 	EClkMmc3_F,

   112 	EClkMsPro_F,

   113 	EClkHdq_F,

   114 	EClkMcBsp1_F,

   115 	EClkMcBsp2_F,

   116 	EClkMcBsp3_F,

   117 	EClkMcBsp4_F,

   118 	EClkMcBsp5_F,

   119 	EClkMcSpi1_F,

   120 	EClkMcSpi2_F,

   121 	EClkMcSpi3_F,

   122 	EClkMcSpi4_F,

   123 	EClkI2c1_F,

   124 	EClkI2c2_F,

   125 	EClkI2c3_F,

   126 	EClkUart1_F,

   127 	EClkUart2_F,

   128 	EClkUart3_F,

   129 	EClkGpt1_F,

   130 	EClkGpt2_F,

   131 	EClkGpt3_F,

   132 	EClkGpt4_F,

   133 	EClkGpt5_F,

   134 	EClkGpt6_F,

   135 	EClkGpt7_F,

   136 	EClkGpt8_F,

   137 	EClkGpt9_F,

   138 	EClkGpt10_F,

   139 	EClkGpt11_F,

   140 	EClkUsbTll_F,

   141 	EClkTs_F,

   142 	EClkCpeFuse_F,

   143 

   144 	EClkSgx_F,

   145 

   146 	EClkUsim_F,

   147 	EClkSmartReflex2_F,

   148 	EClkSmartReflex1_F,

   149 	EClkWdt2_F,

   150 	EClkWdt3_F,

   151 	EClkGpio1_F,

   152 	EClkGpio2_F,

   153 	EClkGpio3_F,

   154 	EClkGpio4_F,

   155 	EClkGpio5_F,

   156 	EClkGpio6_F,

   157 

   158 	EClkUsb120_F,		///< USB host 120MHz functional clock

   159 	EClkUsb48_F,		///< USB host 48MHz functional clock

   160 

   161 

   162 	// Interface clocks

   163 	EClkDss_I,

   164 	EClkCam_I,

   165 	EClkIcr_I,

   166 	EClkMmc1_I,

   167 	EClkMmc2_I,

   168 	EClkMmc3_I,

   169 	EClkMsPro_I,

   170 	EClkHdq_I,

   171 	EClkAes1_I,

   172 	EClkAes2_I,

   173 	EClkSha11_I,

   174 	EClkSha12_I,

   175 	EClkDes1_I,

   176 	EClkDes2_I,

   177 	EClkMcBsp1_I,

   178 	EClkMcBsp2_I,

   179 	EClkMcBsp3_I,

   180 	EClkMcBsp4_I,

   181 	EClkMcBsp5_I,

   182 	EClkI2c1_I,

   183 	EClkI2c2_I,

   184 	EClkI2c3_I,

   185 	EClkUart1_I,

   186 	EClkUart2_I,

   187 	EClkUart3_I,

   188 	EClkMcSpi1_I,

   189 	EClkMcSpi2_I,

   190 	EClkMcSpi3_I,

   191 	EClkMcSpi4_I,

   192 	EClkGpt1_I,

   193 	EClkGpt2_I,

   194 	EClkGpt3_I,

   195 	EClkGpt4_I,

   196 	EClkGpt5_I,

   197 	EClkGpt6_I,

   198 	EClkGpt7_I,

   199 	EClkGpt8_I,

   200 	EClkGpt9_I,

   201 	EClkGpt10_I,

   202 	EClkGpt11_I,

   203 	EClkGpt12_I,

   204 	EClkMailboxes_I,

   205 	EClkOmapSCM_I,

   206 	EClkHsUsbOtg_I,

   207 	EClkSdrc_I,

   208 	EClkPka_I,

   209 	EClkRng_I,

   210 	EClkUsbTll_I,

   211 

   212 	EClkSgx_I,

   213 

   214 	EClkUsim_I,

   215 	EClkWdt1_I,

   216 	EClkWdt2_I,

   217 	EClkWdt3_I,

   218 	EClkGpio1_I,

   219 	EClkGpio2_I,

   220 	EClkGpio3_I,

   221 	EClkGpio4_I,

   222 	EClkGpio5_I,

   223 	EClkGpio6_I,

   224 	EClk32Sync_I,

   225 

   226 	EClkUsb_I,			///< USB host interface clock

   227 

   228 	EClk48M,			///< 48MHz clock

   229 	EClk12M,			///< 12MHz clock

   230 

   231 	// These cannot be modified, they just represent the input clocks

   232 	// They must remain last in the table

   233 	EClkSysClk,			///< SYSCLK input clock

   234 	EClkAltClk,			///< SYSCLK32k input clock

   235 	EClkSysClk32k,		///< ALTCLK input clock

   236 

   237 	KSupportedClockCount

   238 	};

   239 

   240 enum TInterruptIds

   241 	{

   242 	EIntWkUp	= (EIrqRangeBasePrcm << KIrqRangeIndexShift),

   243 	EIntUnused1,

   244 	EIntEvGenOn,

   245 	EIntEvGenOff,

   246 	EIntTransition,

   247 	EIntCoreDpll,

   248 	EIntPeriphDpll,

   249 	EIntMpuDpll,

   250 	EIntIvaDpll,

   251 	EIntIo,

   252 	EIntVp1OpChangeDone,

   253 	EIntVp1MinVdd,

   254 	EIntVp1MaxVdd,

   255 	EIntVp1NoSmpsAck,

   256 	EIntVp1EqValue,

   257 	EIntVp1TranDone,

   258 	EIntVp2OpChangeDone,

   259 	EIntVp2MinVdd,

   260 	EIntVp2MaxVdd,

   261 	EIntVp2NoSmpsAck,

   262 	EIntVp2EqValue,

   263 	EIntVp2TranDone,

   264 	EIntVcSaErr,

   265 	EIntVcRaErr,

   266 	EIntVcTimeoutErr,

   267 	EIntSndPeriphDpll,

   268 

   269 	KPrcmLastInterruptPlusOne

   270 	};

   271 const TInt KInterruptCount = KPrcmLastInterruptPlusOne - EIrqRangeBasePrcm;

   272 

   273 

   274 /** GPT reference enumeration */

   275 enum TGpt

   276 	{

   277 	EGpt1,

   278 	EGpt2,

   279 	EGpt3,

   280 	EGpt4,

   281 	EGpt5,

   282 	EGpt6,

   283 	EGpt7,

   284 	EGpt8,

   285 	EGpt9, 

   286 	EGpt10,

   287 	EGpt11,

   288 	EGpt12,

   289 

   290 	KSupportedGptCount

   291 	};

   292 

   293 /** Enumeration of supported PLLs */

   294 enum TPll

   295 	{

   296 	EDpll1,

   297 	EDpll2,

   298 	EDpll3,

   299 	EDpll4,

   300 	EDpll5,

   301 

   302 	KSupportedPllCount

   303 	};

   304 

   305 enum TGptClockSource

   306 	{

   307 	EGptClockSysClk,

   308 	EGptClock32k

   309 	};

   310 

   311 enum TClockState

   312 	{

   313 	EClkOff,		///< clock is disabled

   314 	EClkOn,		///< clock is enabled

   315 	EClkAuto		///< clock is in auto mode (enabled when required)

   316 	};

   317 

   318 enum TWakeupMode

   319 	{

   320 	EWakeupDisabled,

   321 	EWakeupEnabled,

   322 	};

   323 

   324 enum TLpMode

   325 	{

   326 	ENormalMode,

   327 	ELpMode

   328 	};

   329 

   330 enum TPowerSaveMode

   331 	{

   332 	EPowerSaveOff,

   333 	EPowerSaveIdle,

   334 	EPowerSaveStandby

   335 	};

   336 

   337 enum TPllMode

   338 	{

   339 	EPllStop,

   340 	EPllBypass,

   341 	EPllRun,

   342 	EPllFastRelock,

   343 	EPllAuto

   344 	};

   345 

   346 enum TBypassDivider

   347 	{

   348 	EBypassDiv1,

   349 	EBypassDiv2,

   350 	EBypassDiv4

   351 	};

   352 

   353 enum TPowerDomainMode

   354 	{

   355 	EPowerOff,

   356 	EPowerRetention,

   357 	EPowerReserved,

   358 	EPowerOn,

   359 	};

   360 

   361 enum TPowerDomain

   362 	{

   363 	EPowerDomainMpu,

   364 	EPowerDomainIva2,

   365 	EPowerDomainNeon,

   366 	EPowerDomainCore,

   367 	EPowerDomainSgx,

   368 	EPowerDomainDss,

   369 	EPowerDomainCamera,

   370 	EPowerDomainUsb,

   371 	EPowerDomainPer,

   372 

   373 	KSupportedPowerDomainCount

   374 	};

   375 

   376 enum TWakeupDomain

   377 	{

   378 	EWakeDomainMpu,

   379 	EWakeDomainCore,

   380 	EWakeDomainIva2,

   381 	EWakeDomainPeripheral,

   382 	EWakeDomainDss,

   383 	EWakeDomainWakeup,

   384 

   385 	KSupportedWakeupDomainCount

   386 	};

   387 

   388 enum TWakeupGroup

   389 	{

   390 	EWakeGroupMpu,

   391 	EWakeGroupIva2,

   392 

   393 	KSupportedWakeupGroupCount

   394 	};

   395 

   396 /** Indicates how to handle a request to set a clock frequency */

   397 enum TClockRoundMode

   398 	{

   399 	EExactOnly,		///< only set clock if requested frequency can be set exactly

   400 	ENearest,		///< always set clock to nearest possible frequency higher or lower than requested

   401 	ENearestLower,	///< set to nearest frequency <=requested, fail if no frequency <= requested is possible

   402 	ENearestHigher,	///< set to nearest frequency >=requested, fail if no frequency >= requested is possible

   403 	};

   404 

   405 /** Enumeration of valid Pll frequency ranges */

   406 enum TPllFrequencyRange

   407 	{

   408 	EPllRange_075_100		= 0x3,	///<	0.75 - 1.0 MHz

   409 	EPllRange_100_125		= 0x4,	///<	<1.0 MHz - 1.25 MHz

   410 	EPllRange_125_150		= 0x5,	///<	<1.25 MHz - 1.5 MHz

   411 	EPllRange_150_175		= 0x6,	///<	<1.5 MHz - 1.75 MHz

   412 	EPllRange_175_210		= 0x7,	///<	<1.75 MHz - 2.1 MHz

   413 	EPllRange_750_1000		= 0xB,	///<	<7.5 MHz - 10 MHz

   414 	EPllRange_1000_1250		= 0xC,	///<	<10 MHz - 12.5 MHz

   415 	EPllRange_1250_1500		= 0xD,	///<	<12.5 MHz - 15 MHz

   416 	EPllRange_1500_1750		= 0xE,	///<	<15 MHz - 17.5 MHz

   417 	EPllRange_1750_2100		= 0xF	///<	<17.5 MHz - 21 MHz

   418 	};

   419 

   420 /** Enumeration of valid PLL ramp settings */

   421 enum TPllRamp

   422 	{

   423 	EPllRampDisabled = 0x0,

   424 	EPllRamp4us		= 0x1,

   425 	EPllRam20us		= 0x2,

   426 	EPllRamp40us	= 0x3

   427 	};

   428 

   429 /** Enumeration of vali PLL driftguard settings */

   430 enum TPllDrift

   431 	{

   432 	EPllDriftGuardDisabled,

   433 	EPllDriftGuardEnabled

   434 	};

   435 

   436 /** Structure containing configuration for a PLL */

   437 struct TPllConfiguration

   438 	{

   439 	TUint		iMultiplier;		///< Multiple value

   440 	TUint		iDivider;			///< Divider value (this is actual divider, hardware is programmed with iDivider-1)

   441 	TPllFrequencyRange	iFreqRange : 8;

   442 	TPllRamp	iRamp : 8;

   443 	TPllDrift	iDrift : 8;

   444 	TUint8		__spare;

   445 	};

   446 

   447 /** Enumeration of supported SysClk frequency configurations */

   448 enum TSysClkFrequency

   449 	{

   450 	ESysClk12MHz,

   451 	ESysClk13MHz,

   452 	ESysClk16_8MHz,

   453 	ESysClk19_2MHz,

   454 	ESysClk26MHz,

   455 	ESysClk38_4MHz

   456 	};

   457 

   458 // called during start-up

   459 IMPORT_C void Init3(); // PRCM (disable every peripheral leaving DSS (and UART3 in debug) running)

   460 

   461 IMPORT_C void SetPllConfig( TPll aPll, const TPllConfiguration& aConfig  );

   462 IMPORT_C void PllConfig( TPll aPll, TPllConfiguration& aConfigResult );

   463 

   464 

   465 /** Configure PLL frequency */

   466 IMPORT_C void SetPllMode( TPll aPll, TPllMode aPllMode );

   467 

   468 /** Return PLL frequency configuration */

   469 IMPORT_C TPllMode PllMode( TPll aPll );

   470 

   471 /** Test whether a PLL is locked */

   472 IMPORT_C TBool PllIsLocked( TPll aPll );

   473 

   474 /** Wait for a PLL to lock */

   475 IMPORT_C void WaitForPllLock( TPll aPll );

   476 

   477 /** Calculate the correct FreqRange setting for the given pll

   478  * Updates the iFreqRange parameter of the given TPllConfiguration

   479  */

   480 IMPORT_C void CalcPllFrequencyRange( TPll aPll, TPllConfiguration& aConfig );

   481 

   482 /** Enable LP mode on a DLL if it is within LP frequency range */

   483 IMPORT_C void AutoSetPllLpMode( TPll aPll );

   484 

   485 /** Enable or disable PLL LP mode */

   486 IMPORT_C void SetPllLp( TPll aPll, TLpMode aLpMode );

   487 

   488 /** Get LP mode setting for a PLL */

   489 IMPORT_C TLpMode PllLp( TPll aPll );

   490 

   491 /** Set the bypass divider for a PLL */

   492 IMPORT_C void SetPllBypassDivider( TPll aPll, TBypassDivider aDivider );

   493 

   494 /** Get the current bypass divider for a PLL */

   495 IMPORT_C TBypassDivider PllBypassDivider( TPll aPll );

   496 

   497 /** Set the divider value for the given clock 

   498  * aDivider is the required divide value - e.g. to divide by 4

   499  * aDivider=4.

   500  *

   501  * Note that not all clocks support division by any number, and

   502  * only some clocks have a divider. Attempting to set a divider

   503  * on a clock without a divider will have no effect in UREL and

   504  * will panic in UDEB with ESetDividerUnsupportedClock.

   505  * Attempting to set a divider value not supported by the clock

   506  * will have no effect in UREL and will panic in UDEB with

   507  * ESetDividerBadDivider.

   508  *

   509  * Note 1: for EClkSgx_F the value valued of aDivide are 0, 3, 4, 6.

   510  * 0 sets the clock to be the 96MHz clock

   511  * 3, 4, 6 set it to be CORE_CLK divided by 3, 4, or 6

   512  *

   513  * Note 2: you cannot use this function to set EClkUsim_F, use

   514  * SetUsimClockDivider().

   515  */

   516 IMPORT_C void SetDivider( TClock aClock, TUint aDivide );

   517 

   518 /** Get the current divider value of the given clock */

   519 IMPORT_C TUint Divider( TClock aClock );

   520 

   521 //IMPORT_C void SetUsimClockDivider( TUint TUsimDivideMode aMode );

   522 //IMPORT_C TUsimDivideMode UsimClockDivider();

   523 

   524 /** Controls power to a power domain */

   525 IMPORT_C void SetPowerDomainMode( TPowerDomain aDomain, TPowerDomainMode aMode );

   526 

   527 /** Gets the current mode of a power domain power control */

   528 IMPORT_C TPowerDomainMode PowerDomainMode( TPowerDomain aDomain );

   529 

   530 //IMPORT_C void SetPowerSaveMode( TClock aClock, TPowerSaveMode aMode );

   531 //IMPORT_C TPowerSaveMode PowerSaveMode( TClock aClock );

   532 

   533 //IMPORT_C TBool DomainClockActive( TClock aClock );

   534 

   535 // Set clock enable/disable

   536 /** Set the clock state of a given clock */

   537 IMPORT_C void SetClockState( TClock aClock, TClockState aState );

   538 

   539 /** Get the configured clock state of a given clock */

   540 IMPORT_C TClockState ClockState( TClock aClock );

   541 

   542 // Configure wakeup mode for clocks

   543 /** Configure wakeup mode for a clock

   544  * Note - for peripheral blocks with an interface and functional clock, it is

   545  * the interface clock which is configured for wakeup. Attempting to configure

   546  * wakeup on the functional clock has no effect

   547  */

   548 IMPORT_C void SetWakeupMode( TClock aClock, TWakeupMode aMode );

   549 

   550 /** Get configured wakeup mode for a clock */

   551 IMPORT_C TWakeupMode WakeupMode( TClock aClock );

   552 

   553 /** Add a peripheral interface clock to the specified wakeup group */

   554 IMPORT_C void AddToWakeupGroup( TClock aClock, TWakeupGroup aGroup );

   555 

   556 /** Remove a peripheral interface clock from the specified wakeup group */

   557 IMPORT_C void RemoveFromWakeupGroup( TClock aClock, TWakeupGroup aGroup );

   558 

   559 /** Test whether a peripheral interface clock is in the specified wakeup group */

   560 IMPORT_C TBool IsInWakeupGroup( TClock aClock, TWakeupGroup aGroup );

   561 

   562 /** Add a clock to the given wakeup domain */

   563 IMPORT_C void AddToWakeupDomain( TClock aClock, TWakeupDomain aDomain );

   564 

   565 /** Remove a clock from the given wakeup domain */

   566 IMPORT_C void RemoveFromWakeupDomain( TClock aClock, TWakeupDomain aDomain );

   567 

   568 /** Test whether a clock is in the specified wakeup domain */

   569 IMPORT_C TBool IsInWakeupDomain( TClock aClock, TWakeupDomain aDomain );

   570 

   571 

   572 // Functions for configuring clock sources

   573 

   574 /** Set the clock source for a GPT timer */

   575 IMPORT_C void SetGptClockSource( TGpt aGpt, TGptClockSource aSource );

   576 

   577 /** Get the current clock source of a GPT */

   578 IMPORT_C TGptClockSource GptClockSource( TGpt aGpt );

   579 

   580 /** Get the USIM divider factor */

   581 IMPORT_C TUint UsimDivider();

   582 

   583 /** Get the USIM source clock */

   584 IMPORT_C TClock UsimClockSource();

   585 

   586 /** Sets the current input clock into the clock mux for the specified clock

   587  * aClock must refer to a clock that has a mux for selecting input clock

   588  * and aSource must be a possible input clock for aClock

   589  */

   590 IMPORT_C void SetClockMux( TClock aClock, TClock aSource );

   591 

   592 

   593 /** Gets the current input clock into the clock mux for the specified clock

   594  * aClock must refer to a clock that has a mux for selecting input clock

   595  */

   596 IMPORT_C TClock ClockMux( TClock aClock );

   597 

   598 /** Get the currently configured frequency of the specified clock

   599  * Note that this is regardless of whether the clock is currently running.

   600  * That is, if a clock is configured to run at 8MHz, then this function

   601  * will return 8000000 whether the clock is currently enabled or disabled.

   602  *

   603  * @param	aClock	clock required

   604  * @return	Frequency in Hz

   605  */

   606 IMPORT_C TUint ClockFrequency( TClock aClock );

   607 

   608 /** Set the correct SysClock frequency */

   609 IMPORT_C void SetSysClkFrequency( TSysClkFrequency aFrequency );

   610 

   611 /** Get the currently configured SysClk frequency */

   612 IMPORT_C TSysClkFrequency SysClkFrequency();

   613 

   614 /** Function to get the name to be passed to the Power Resource Manager

   615  * to refer to the given clock source

   616  */

   617 IMPORT_C const TDesC& PrmName( TClock aClock );

   618 

   619 }

   620 

   621 #endif // !defined PRCM_H__