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1 // Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of the License "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: |
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14 // omap3530/omap3530_drivers/uart/omap3530_uart.h |
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15 // This file is part of the Beagle Base port |
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16 // |
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17 |
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18 #ifndef __OMAP3530_UART_H__ |
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19 #define __OMAP3530_UART_H__ |
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20 |
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21 #include <assp/omap3530_assp/omap3530_hardware_base.h> |
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22 #include <assp/omap3530_assp/omap3530_prcm.h> |
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23 //#include "assp/omap3530_assp/omap3530_prm.h" |
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24 #include <assp/omap3530_assp/omap3530_irqmap.h> |
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25 |
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26 //#include "omap3530_prm.h" |
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27 |
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28 |
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29 namespace Omap3530Uart |
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30 { |
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31 using namespace TexasInstruments::Omap3530; |
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32 |
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33 enum TUartNumber |
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34 { |
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35 EUartNone = -1, |
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36 EUart0 = 0, |
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37 EUart1, |
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38 EUart2 |
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39 }; |
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40 |
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41 template< const TUartNumber aUartNumber > |
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42 struct TUartTraits |
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43 { |
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44 }; |
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45 |
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46 template<> |
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47 struct TUartTraits< EUart0 > |
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48 { |
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49 static const TUint32 KBaseAddress = Omap3530HwBase::KL4_Core + 0x0006A000; |
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50 static const TInt KInterruptId = EOmap3530_IRQ72_UART1_IRQ; |
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51 static const Prcm::TClock KInterfaceClock = Prcm::EClkUart1_I; |
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52 static const Prcm::TClock KFunctionClock = Prcm::EClkUart1_F; |
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53 // static const Omap3530Prm::TPrmId KPrmInterfaceClock = Omap3530Prm::EPrmClkUart1_I; |
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54 // static const Omap3530Prm::TPrmId KPrmFunctionClock = Omap3530Prm::EPrmClkUart1_F; |
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55 }; |
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56 |
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57 template<> |
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58 struct TUartTraits< EUart1 > |
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59 { |
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60 static const TUint32 KBaseAddress = Omap3530HwBase::KL4_Core + 0x0006C000; |
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61 static const TInt KInterruptId = EOmap3530_IRQ73_UART2_IRQ; |
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62 static const Prcm::TClock KInterfaceClock = Prcm::EClkUart2_I; |
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63 static const Prcm::TClock KFunctionClock = Prcm::EClkUart2_F; |
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64 // static const Omap3530Prm::TPrmId KPrmInterfaceClock = Omap3530Prm::EPrmClkUart2_I; |
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65 // static const Omap3530Prm::TPrmId KPrmFunctionClock = Omap3530Prm::EPrmClkUart2_F; |
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66 }; |
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67 |
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68 template<> |
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69 struct TUartTraits< EUart2 > |
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70 { |
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71 static const TUint32 KBaseAddress = Omap3530HwBase::KL4_Per + 0x00020000; |
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72 static const TInt KInterruptId = EOmap3530_IRQ74_UART3_IRQ; |
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73 static const Prcm::TClock KInterfaceClock = Prcm::EClkUart3_I; |
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74 static const Prcm::TClock KFunctionClock = Prcm::EClkUart3_F; |
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75 // static const Omap3530Prm::TPrmId KPrmInterfaceClock = Omap3530Prm::EPrmClkUart3_I; |
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76 // static const Omap3530Prm::TPrmId KPrmFunctionClock = Omap3530Prm::EPrmClkUart3_F; |
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77 }; |
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78 |
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79 // Forward declaration |
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80 class TUart; |
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81 |
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82 |
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83 /** Representation of general UART register set */ |
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84 struct DLL |
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85 { |
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86 static const TInt KOffset = 0x00; |
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87 static TDynReg8_RW< TUart, KOffset > iMem; |
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88 typedef TBitField<0,8> CLOCK_LSB; |
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89 }; |
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90 |
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91 struct RHR |
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92 { |
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93 static const TInt KOffset = 0x00; |
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94 static TDynReg8_R< TUart, KOffset > iMem; |
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95 typedef TBitField<0,8> Value; |
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96 }; |
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97 |
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98 struct THR |
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99 { |
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100 static const TInt KOffset = 0x00; |
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101 static TDynReg8_W< TUart, KOffset > iMem; |
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102 typedef TBitField<0,8> Value; |
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103 }; |
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104 |
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105 struct IER |
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106 { |
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107 static const TInt KOffset = 0x04; |
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108 static TDynReg8_RW< TUart, KOffset > iMem; |
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109 typedef TSingleBitField<7> CTS_IT; |
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110 typedef TSingleBitField<6> RTS_IT; |
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111 typedef TSingleBitField<5> XOFF_IT; |
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112 typedef TSingleBitField<4> SLEEP_MODE; |
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113 typedef TSingleBitField<3> MODEM_STS_IT; |
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114 typedef TSingleBitField<2> LINE_STS_IT; |
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115 typedef TSingleBitField<1> THR_IT; |
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116 typedef TSingleBitField<0> RHR_IT; |
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117 }; |
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118 |
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119 struct IER_IRDA |
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120 { |
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121 static const TInt KOffset = 0x04; |
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122 static TDynReg8_RW< TUart, KOffset > iMem; |
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123 typedef TSingleBitField<7> EOF_IT; |
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124 typedef TSingleBitField<6> LINE_STS_IT; |
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125 typedef TSingleBitField<5> TX_STATUS_IT; |
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126 typedef TSingleBitField<4> STS_FIFO_TRIG_IT; |
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127 typedef TSingleBitField<3> RX_OVERRUN_IT; |
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128 typedef TSingleBitField<2> LAST_RX_BYTE_IT; |
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129 typedef TSingleBitField<1> THR_IT; |
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130 typedef TSingleBitField<0> RHR_IT; |
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131 }; |
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132 |
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133 struct DLH |
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134 { |
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135 static const TInt KOffset = 0x04; |
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136 static TDynReg8_RW< TUart, KOffset > iMem; |
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137 typedef TBitField<0,6> CLOCK_MSB; |
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138 }; |
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139 |
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140 struct FCR |
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141 { |
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142 static const TInt KOffset = 0x08; |
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143 static TDynReg8_W< TUart, KOffset > iMem; |
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144 typedef TSingleBitField<0> FIFO_EN; |
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145 typedef TSingleBitField<1> RX_FIFO_CLEAR; |
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146 typedef TSingleBitField<2> TX_FIFO_CLEAR; |
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147 typedef TSingleBitField<3> DMA_MODE; |
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148 struct TX_FIFO_TRIG : public TBitField<4,2> |
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149 { |
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150 enum TConstants |
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151 { |
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152 K8Char = 0 << KShift, |
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153 K16Char = 1 << KShift, |
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154 K32Char = 2 << KShift, |
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155 K56Char = 3 << KShift |
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156 }; |
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157 }; |
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158 struct RX_FIFO_TRIG : public TBitField<6,2> |
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159 { |
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160 static const TUint8 K8Char = 0 << KShift; |
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161 static const TUint8 K16Char = 1 << KShift; |
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162 static const TUint8 K56Char = 2 << KShift; |
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163 static const TUint8 K60Char = 3 << KShift; |
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164 }; |
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165 }; |
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166 |
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167 struct IIR |
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168 { |
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169 static const TInt KOffset = 0x08; |
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170 static TDynReg8_R< TUart, KOffset > iMem; |
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171 typedef TBitField<6,2> FCR_MIRROR; |
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172 struct IT_TYPE : public TBitField<1,5> |
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173 { |
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174 enum TConstants |
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175 { |
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176 EModem = 0 << KShift, |
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177 ETHR = 1 << KShift, |
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178 ERHR = 2 << KShift, |
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179 ERxLineStatus = 3 << KShift, |
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180 ERxTimeout = 6 << KShift, |
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181 EXoff = 8 << KShift, |
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182 ECtsRts = 16 << KShift |
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183 }; |
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184 }; |
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185 typedef TSingleBitField<0> IT_PENDING; |
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186 }; |
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187 |
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188 struct EFR |
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189 { |
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190 static const TInt KOffset = 0x08; |
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191 static TDynReg8_RW< TUart, KOffset > iMem; |
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192 typedef TSingleBitField<7> AUTO_CTS_EN; |
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193 typedef TSingleBitField<6> AUTO_RTS_EN; |
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194 typedef TSingleBitField<5> SPEC_CHAR; |
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195 typedef TSingleBitField<4> ENHANCED_EN; |
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196 struct SW_FLOW_CONTROL : public TBitField<0,4> |
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197 { |
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198 enum TFlowControl |
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199 { |
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200 ENone = 0, |
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201 EXonXoff1 = 8, |
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202 EXonXoff2 = 4, |
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203 EXonXoffBoth = 8 + 4, |
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204 }; |
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205 }; |
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206 }; |
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207 |
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208 struct LCR |
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209 { |
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210 static const TInt KOffset = 0x0c; |
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211 static TDynReg8_RW< TUart, KOffset > iMem; |
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212 typedef TSingleBitField<7> DIV_EN; |
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213 typedef TSingleBitField<6> BREAK_EN; |
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214 typedef TSingleBitField<5> PARITY_TYPE2; |
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215 typedef TSingleBitField<4> PARITY_TYPE1; |
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216 typedef TSingleBitField<3> PARITY_EN; |
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217 struct NB_STOP : public TSingleBitField<2> |
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218 { |
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219 enum TConstants |
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220 { |
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221 E1Stop = 0 << KShift, |
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222 E1_5Stop = 1 << KShift, |
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223 E2Stop = 1 << KShift |
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224 }; |
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225 }; |
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226 struct CHAR_LENGTH : public TBitField<0,2> |
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227 { |
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228 enum TConstants |
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229 { |
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230 E5Bits = 0, |
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231 E6Bits = 1, |
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232 E7Bits = 2, |
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233 E8Bits = 3 |
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234 }; |
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235 }; |
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236 |
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237 /** Special magic number to enter MODEA */ |
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238 static const TUint8 KConfigModeA = 0x80; |
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239 |
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240 /** Special magic number to enter MODEB */ |
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241 static const TUint8 KConfigModeB = 0xBF; |
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242 |
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243 /** Special magic number to enter operational mode */ |
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244 static const TUint8 KConfigModeOperational = 0x00; |
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245 }; |
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246 |
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247 struct MCR |
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248 { |
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249 static const TInt KOffset = 0x10; |
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250 static TDynReg8_RW< TUart, KOffset > iMem; |
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251 typedef TSingleBitField<6> TCR_TLR; |
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252 typedef TSingleBitField<5> XON_EN; |
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253 typedef TSingleBitField<4> LOOPBACK_EN; |
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254 typedef TSingleBitField<3> CD_STS_CH; |
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255 typedef TSingleBitField<2> RI_STS_CH; |
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256 typedef TSingleBitField<1> RTS; |
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257 typedef TSingleBitField<0> DTR; |
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258 }; |
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259 |
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260 struct XON1_ADDR1 |
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261 { |
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262 static const TInt KOffset = 0x10; |
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263 static TDynReg8_RW< TUart, KOffset > iMem; |
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264 typedef TBitField<0,8> Value; |
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265 }; |
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266 |
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267 struct LSR |
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268 { |
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269 static const TInt KOffset = 0x14; |
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270 static TDynReg8_R< TUart, KOffset > iMem; |
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271 typedef TSingleBitField<7> RX_FIFO_STS; |
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272 typedef TSingleBitField<6> TX_SR_E; |
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273 typedef TSingleBitField<5> TX_FIFO_E; |
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274 typedef TSingleBitField<4> RX_BI; |
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275 typedef TSingleBitField<3> RX_FE; |
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276 typedef TSingleBitField<2> RX_PE; |
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277 typedef TSingleBitField<1> RX_OE; |
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278 typedef TSingleBitField<0> RX_FIFO_E; |
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279 }; |
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280 |
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281 struct XON2_ADDR2 |
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282 { |
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283 static const TInt KOffset = 0x14; |
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284 static TDynReg8_RW< TUart, KOffset > iMem; |
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285 typedef TBitField<0,8> Value; |
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286 }; |
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287 |
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288 struct XOFF1 |
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289 { |
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290 static const TInt KOffset = 0x18; |
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291 static TDynReg8_RW< TUart, KOffset > iMem; |
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292 typedef TBitField<0,8> Value; |
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293 }; |
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294 |
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295 struct TCR |
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296 { |
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297 static const TInt KOffset = 0x18; |
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298 static TDynReg8_RW< TUart, KOffset > iMem; |
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299 typedef TBitField<4,4> RX_FIFO_TRIG_START; |
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300 typedef TBitField<0,4> RX_FIFO_TRIG_HALT; |
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301 }; |
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302 |
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303 struct MSR |
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304 { |
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305 static const TInt KOffset = 0x18; |
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306 static TDynReg8_R< TUart, KOffset > iMem; |
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307 typedef TSingleBitField<7> NCD_STS; |
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308 typedef TSingleBitField<6> NRI_STS; |
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309 typedef TSingleBitField<5> NDSR_STS; |
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310 typedef TSingleBitField<4> NCTS_STS; |
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311 typedef TSingleBitField<3> DCD_STS; |
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312 typedef TSingleBitField<2> RI_STS; |
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313 typedef TSingleBitField<1> DSR_STS; |
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314 typedef TSingleBitField<0> CTS_STS; |
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315 }; |
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316 |
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317 struct SPR |
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318 { |
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319 static const TInt KOffset = 0x1c; |
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320 static TDynReg8_RW< TUart, KOffset > iMem; |
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321 typedef TBitField<0,8> SPR_WORD; |
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322 }; |
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323 |
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324 struct XOFF2 |
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325 { |
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326 static const TInt KOffset = 0x1c; |
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327 static TDynReg8_RW< TUart, KOffset > iMem; |
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328 typedef TBitField<0,8> Value; |
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329 }; |
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330 |
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331 struct TLR |
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332 { |
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333 static const TInt KOffset = 0x1c; |
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334 static TDynReg8_RW< TUart, KOffset > iMem; |
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335 typedef TBitField<4,4> RX_FIFO_TRIG_DMA; |
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336 typedef TBitField<0,4> TX_FIFO_TRIG_DMA; |
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337 }; |
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338 |
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339 struct MDR1 |
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340 { |
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341 static const TInt KOffset = 0x20; |
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342 static TDynReg8_RW< TUart, KOffset > iMem; |
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343 typedef TSingleBitField<7> FRAME_END_MODE; |
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344 typedef TSingleBitField<6> SIP_MODE; |
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345 typedef TSingleBitField<5> SCT; |
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346 typedef TSingleBitField<4> SET_TXIR; |
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347 typedef TSingleBitField<3> IR_SLEEP; |
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348 struct MODE_SELECT : public TBitField<0,3> |
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349 { |
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350 enum TMode |
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351 { |
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352 EUart16x = 0, |
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353 ESIR = 1, |
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354 EUart16xAutoBaud = 2, |
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355 EUart13x = 3, |
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356 EMIR = 4, |
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357 EFIR = 5, |
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358 ECIR = 6, |
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359 EDisable = 7 |
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360 }; |
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361 }; |
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362 }; |
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363 |
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364 struct MDR2 |
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365 { |
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366 static const TInt KOffset = 0x24; |
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367 static TDynReg8_RW< TUart, KOffset > iMem; |
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368 typedef TSingleBitField<6> IRRXINVERT; |
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369 struct CIR_PULSE_MODE : public TBitField<4,2> |
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370 { |
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371 enum TConstants |
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372 { |
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373 EPw3 = 0 << KShift, |
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374 EPw4 = 1 << KShift, |
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375 EPw5 = 2 << KShift, |
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376 EPw6 = 3 << KShift |
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377 }; |
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378 }; |
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379 typedef TSingleBitField<3> UART_PULSE; |
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380 struct STS_FIFO_TRIG : public TBitField<1,2> |
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381 { |
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382 enum TConstants |
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383 { |
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384 E1Entry = 0 << KShift, |
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385 E4Entry = 1 << KShift, |
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386 E7Entry = 2 << KShift, |
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387 E8Entry = 3 << KShift |
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388 }; |
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389 }; |
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390 typedef TSingleBitField<0> IRTX_UNDERRUN; |
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391 }; |
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392 |
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393 struct TXFLL |
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394 { |
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395 static const TInt KOffset = 0x28; |
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396 static TDynReg8_W< TUart, KOffset > iMem; |
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397 typedef TBitField<0,8> TX_FLL; |
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398 }; |
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399 |
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400 struct SFLSR |
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401 { |
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402 static const TInt KOffset = 0x28; |
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403 static TDynReg8_R< TUart, KOffset > iMem; |
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404 typedef TSingleBitField<4> OE_ERROR; |
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405 typedef TSingleBitField<3> FTL_ERROR; |
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406 typedef TSingleBitField<2> ABORT_DETECT; |
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407 typedef TSingleBitField<1> CRC_ERROR; |
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408 }; |
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409 |
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410 struct RESUME |
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411 { |
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412 static const TInt KOffset = 0x2c; |
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413 static TDynReg8_R< TUart, KOffset > iMem; |
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414 typedef TBitField<0,8> Value; |
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415 }; |
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416 |
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417 struct TXFLH |
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418 { |
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419 static const TInt KOffset = 0x2c; |
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420 static TDynReg8_W< TUart, KOffset > iMem; |
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421 typedef TBitField<0,5> TX_FLH; |
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422 }; |
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423 |
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424 struct RXFLL |
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425 { |
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426 static const TInt KOffset = 0x30; |
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427 static TDynReg8_W< TUart, KOffset > iMem; |
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428 typedef TBitField<0,8> RX_FLL; |
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429 }; |
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430 |
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431 struct SFREGL |
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432 { |
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433 static const TInt KOffset = 0x30; |
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434 static TDynReg8_R< TUart, KOffset > iMem; |
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435 typedef TBitField<0,8> Value; |
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436 }; |
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437 |
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438 struct SFREGH |
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439 { |
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440 static const TInt KOffset = 0x34; |
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441 static TDynReg8_R< TUart, KOffset > iMem; |
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442 typedef TBitField<0,4> Value; |
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443 }; |
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444 |
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445 struct RXFLH |
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446 { |
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447 static const TInt KOffset = 0x34; |
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448 static TDynReg8_W< TUart, KOffset > iMem; |
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449 typedef TBitField<0,4> RX_FLH; |
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450 }; |
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451 |
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452 struct BLR |
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453 { |
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454 typedef TSingleBitField<7> STS_FIFO_RESET; |
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455 typedef TSingleBitField<6> XBOF_TYPE; |
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456 }; |
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457 |
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458 struct UASR |
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459 { |
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460 static const TInt KOffset = 0x38; |
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461 static TDynReg8_R< TUart, KOffset > iMem; |
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462 struct PARITY_TYPE : public TBitField<6,2> |
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463 { |
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464 enum TConstants |
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465 { |
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466 ENone = 0 << KShift, |
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467 ESpace = 1 << KShift, |
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468 EEven = 2 << KShift, |
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469 EOdd = 3 << KShift |
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470 }; |
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471 }; |
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472 struct BIT_BY_CHAR : public TSingleBitField<5> |
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473 { |
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474 enum TConstants |
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475 { |
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476 E7Bit = 0 << KShift, |
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477 E8Bit = 1 << KShift |
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478 }; |
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479 }; |
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480 struct SPEED : public TBitField<0,5> |
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481 { |
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482 enum TBaud |
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483 { |
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484 EUnknown = 0, |
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485 E115200 = 1, |
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486 E57600 = 2, |
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487 E38400 = 3, |
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488 E28800 = 4, |
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489 E19200 = 5, |
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490 E14400 = 6, |
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491 E9600 = 7, |
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492 E4800 = 8, |
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493 E4800_2 = 9, |
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494 E1200 = 10 |
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495 }; |
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496 }; |
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497 }; |
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498 |
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499 struct ACREG |
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500 { |
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501 static const TInt KOffset = 0x3c; |
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502 static TDynReg8_RW< TUart, KOffset > iMem; |
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503 typedef TSingleBitField<7> PULSE_TYPE; |
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504 typedef TSingleBitField<6> SID_MOD; |
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505 typedef TSingleBitField<5> DIS_IR_RX; |
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506 typedef TSingleBitField<4> DIS_TX_UNDERRUN; |
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507 typedef TSingleBitField<3> SEND_SIP; |
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508 typedef TSingleBitField<2> SCTX_EN; |
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509 typedef TSingleBitField<1> ABORT_EN; |
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510 typedef TSingleBitField<0> EOT_EN; |
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511 }; |
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512 |
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513 struct SCR |
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514 { |
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515 static const TInt KOffset = 0x40; |
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516 static TDynReg8_RW< TUart, KOffset > iMem; |
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517 typedef TSingleBitField<7> RX_TRIG_GRANU1; |
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518 typedef TSingleBitField<6> TX_TRIG_GRANU1; |
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519 typedef TSingleBitField<4> RX_CTS_WU_EN; |
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520 typedef TSingleBitField<3> TX_EMPTY_CTL_IT; |
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521 typedef TBitField<1,2> DMA_MODE2; |
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522 typedef TSingleBitField<0> DMA_MODE_CTL; |
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523 }; |
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524 |
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525 struct SSR |
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526 { |
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527 static const TInt KOffset = 0x44; |
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528 static TDynReg8_R< TUart, KOffset > iMem; |
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529 typedef TSingleBitField<1> RX_CTS_WU_STS; |
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530 typedef TSingleBitField<0> TX_FIFO_FULL; |
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531 }; |
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532 |
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533 struct EBLR |
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534 { |
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535 static const TInt KOffset = 0x48; |
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536 static TDynReg8_RW< TUart, KOffset > iMem; |
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537 typedef TBitField<0,8> Value; |
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538 }; |
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539 |
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540 struct SYSC |
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541 { |
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542 static const TInt KOffset = 0x54; |
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543 static TDynReg8_RW< TUart, KOffset > iMem; |
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544 struct IDLE_MODE : public TBitField<3,2> |
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545 { |
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546 enum TMode |
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547 { |
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548 EForceIdle = 0 << KShift, |
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549 ENoIdle = 1 << KShift, |
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550 ESmartIdle = 2 << KShift |
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551 }; |
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552 }; |
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553 typedef TSingleBitField<2> ENAWAKEUP; |
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554 typedef TSingleBitField<1> SOFTRESET; |
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555 typedef TSingleBitField<0> AUTOIDLE; |
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556 }; |
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557 |
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558 struct SYSS |
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559 { |
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560 static const TInt KOffset = 0x58; |
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561 static TDynReg8_R< TUart, KOffset > iMem; |
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562 typedef TSingleBitField<0> RESETDONE; |
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563 }; |
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564 |
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565 struct WER |
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566 { |
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567 static const TInt KOffset = 0x5c; |
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568 static TDynReg8_RW< TUart, KOffset > iMem; |
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569 typedef TSingleBitField<6> EVENT_6_RLS_INTERRUPT; |
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570 typedef TSingleBitField<5> EVENT_5_RHR_INTERRUPT; |
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571 typedef TSingleBitField<4> EVENT_4_RX_ACTIVITY; |
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572 typedef TSingleBitField<2> EVENT_2_RI_ACTIVITY; |
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573 typedef TSingleBitField<0> EVENT_0_CTS_ACTIVITY; |
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574 }; |
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575 |
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576 struct CFPS |
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577 { |
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578 static const TInt KOffset = 0x60; |
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579 static TDynReg8_RW< TUart, KOffset > iMem; |
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580 typedef TBitField<0,8> Value; |
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581 }; |
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582 |
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583 |
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584 class TUart |
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585 { |
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586 public: |
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587 enum TBaud |
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588 { |
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589 E1200, |
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590 E2400, |
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591 E4800, |
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592 E9600, |
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593 E14400, |
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594 E19200, |
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595 E28800, |
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596 E38400, |
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597 E57600, |
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598 E115200, |
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599 E230400, |
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600 E460800, |
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601 E921600, |
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602 E1843000, |
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603 E3688400, |
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604 E4000000, // FIR |
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605 |
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606 KSupportedBaudCount |
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607 }; |
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608 |
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609 enum TParity |
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610 { |
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611 ENone, |
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612 EOdd, |
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613 EEven, |
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614 EMark, |
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615 ESpace |
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616 }; |
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617 |
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618 enum TDataBits |
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619 { |
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620 E5Data = ::Omap3530Uart::LCR::CHAR_LENGTH::E5Bits, |
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621 E6Data = ::Omap3530Uart::LCR::CHAR_LENGTH::E6Bits, |
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622 E7Data = ::Omap3530Uart::LCR::CHAR_LENGTH::E7Bits, |
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623 E8Data = ::Omap3530Uart::LCR::CHAR_LENGTH::E8Bits, |
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624 }; |
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625 |
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626 enum TStopBits |
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627 { |
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628 E1Stop = ::Omap3530Uart::LCR::NB_STOP::E1Stop, |
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629 E1_5Stop = ::Omap3530Uart::LCR::NB_STOP::E1_5Stop, |
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630 E2Stop = ::Omap3530Uart::LCR::NB_STOP::E2Stop, |
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631 }; |
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632 |
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633 enum TUartMode |
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634 { |
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635 EUart, |
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636 EUartAutoBaud, |
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637 ESIR, |
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638 EMIR, |
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639 EFIR, |
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640 ECIR, |
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641 |
|
642 KSupportedUartModes |
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643 }; |
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644 |
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645 enum TFifoTrigger |
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646 { |
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647 ETrigger8, |
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648 ETrigger16, |
|
649 ETrigger32, |
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650 ETrigger56, |
|
651 ETrigger60, |
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652 ETriggerUnchanged |
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653 }; |
|
654 |
|
655 enum TEnableState |
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656 { |
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657 EDisabled, |
|
658 EEnabled |
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659 }; |
|
660 |
|
661 enum TInterrupt |
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662 { |
|
663 EIntRhr = 0, |
|
664 EIntThr = 1, |
|
665 EIntLineStatus = 2, |
|
666 EIntModemStatus = 3, |
|
667 EIntXoff = 5, |
|
668 EIntRts = 6, |
|
669 EIntCts = 7 |
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670 }; |
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671 |
|
672 public: |
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673 inline TUart( const TUartNumber aUartNumber ) |
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674 : iBase( (aUartNumber == EUart0 ) ? TUartTraits<EUart0>::KBaseAddress |
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675 : (aUartNumber == EUart1 ) ? TUartTraits<EUart1>::KBaseAddress |
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676 : (aUartNumber == EUart2 ) ? TUartTraits<EUart2>::KBaseAddress |
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677 : 0 ), |
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678 iUartNumber( aUartNumber ) |
|
679 {} |
|
680 |
|
681 FORCE_INLINE TLinAddr Base() const |
|
682 { return iBase; } |
|
683 |
|
684 IMPORT_C TInt InterruptId() const; |
|
685 |
|
686 IMPORT_C Prcm::TClock PrcmInterfaceClk() const; |
|
687 |
|
688 IMPORT_C Prcm::TClock PrcmFunctionClk() const; |
|
689 |
|
690 // IMPORT_C TInt PrmInterfaceClk() const; |
|
691 |
|
692 // IMPORT_C TInt PrmFunctionClk() const; |
|
693 |
|
694 /** Reset and initialize the UART |
|
695 * On return the UART will be in disable mode */ |
|
696 IMPORT_C void Init(); |
|
697 |
|
698 /** Defines which mode the UART will run in when enabled, but does not configure that mode |
|
699 * You must call this before calling SetBaud to ensure that correct baud rate multiplier is used */ |
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700 IMPORT_C void DefineMode( const TUartMode aMode ); |
|
701 |
|
702 /** Enabled the UART in the defined mode |
|
703 * You must call DefineMode() and SetBaud() before calling Enable() |
|
704 */ |
|
705 IMPORT_C void Enable(); |
|
706 |
|
707 /** Disables the UART */ |
|
708 IMPORT_C void Disable(); |
|
709 |
|
710 /** Set the baud rate |
|
711 * Do not call this while the UART is enabled |
|
712 * You must have previously called DefineMode() |
|
713 */ |
|
714 IMPORT_C void SetBaud( const TBaud aBaud ); |
|
715 |
|
716 /** Set the data length, parity and stop bits */ |
|
717 IMPORT_C void SetDataFormat( const TDataBits aDataBits, const TStopBits aStopBits, const TParity aParity ); |
|
718 |
|
719 /** Setup the FIFO configuration */ |
|
720 IMPORT_C void EnableFifo( const TEnableState aState, const TFifoTrigger aRxTrigger = ETriggerUnchanged, const TFifoTrigger aTxTrigger = ETriggerUnchanged ); |
|
721 |
|
722 /** Enable a particular interrupt source */ |
|
723 IMPORT_C void EnableInterrupt( const TInterrupt aWhich ); |
|
724 |
|
725 /** Disable a particular interrupt source */ |
|
726 IMPORT_C void DisableInterrupt( const TInterrupt aWhich ); |
|
727 |
|
728 /** Disable all interrupts */ |
|
729 IMPORT_C void DisableAllInterrupts(); |
|
730 |
|
731 inline TBool TxFifoFull() |
|
732 { return SSR::iMem.Read(*this) bitand SSR::TX_FIFO_FULL::KMask; } |
|
733 |
|
734 inline TBool TxFifoEmpty() |
|
735 { return LSR::iMem.Read(*this) bitand LSR::TX_FIFO_E::KMask; } |
|
736 |
|
737 inline TBool RxFifoEmpty() |
|
738 { return !(LSR::iMem.Read(*this) bitand LSR::RX_FIFO_E::KMask); } |
|
739 |
|
740 inline void Write( TUint8 aByte ) |
|
741 { THR::iMem.Write( *this, aByte ); } |
|
742 |
|
743 inline TUint8 Read() |
|
744 { return RHR::iMem.Read( *this ); } |
|
745 |
|
746 private: |
|
747 TUart(); |
|
748 |
|
749 public: |
|
750 const TLinAddr iBase; |
|
751 const TUartNumber iUartNumber : 8; |
|
752 TUartMode iMode : 8; |
|
753 ::Omap3530Uart::MDR1::MODE_SELECT::TMode iTargetMode : 8; |
|
754 }; |
|
755 |
|
756 |
|
757 } // Omap3530Uart |
|
758 |
|
759 #endif // ndef __OMAP3530_UART_H__ |
|
760 |