|
1 // Copyright (c) 2009 Nokia Corporation and/or its subsidiary(-ies). |
|
2 // All rights reserved. |
|
3 // This component and the accompanying materials are made available |
|
4 // under the terms of the License "Eclipse Public License v1.0" |
|
5 // which accompanies this distribution, and is available |
|
6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
|
7 // |
|
8 // Initial Contributors: |
|
9 // Nokia Corporation - initial contribution. |
|
10 // |
|
11 // Contributors: |
|
12 // |
|
13 // Description: |
|
14 // \omap3530\omap3530_assp\shared\tps65950\tps65950_int.cpp |
|
15 // Interrupt dispatcher for TPS65950 |
|
16 // This file is part of the Beagle Base port |
|
17 // |
|
18 |
|
19 #include <e32cmn.h> |
|
20 #include <nk_priv.h> |
|
21 #include <kernel.h> |
|
22 //#include <e32atomics.h> |
|
23 #include <omap3530_i2c.h> |
|
24 #include <omap3530_i2creg.h> |
|
25 #include "tps65950.h" |
|
26 #include <assp/omap3530_assp/locks.h> |
|
27 |
|
28 // Use a dedicated thread for processing interrupts to prevent deadlocking |
|
29 // the main TSP65960 thread and to avoid needing a big state machine to |
|
30 // process interrupts in multiple DFCs |
|
31 TDfcQue* TheInterruptDfcQue; |
|
32 _LIT( KInterruptDfcQueName, "TPS65950INT" ); |
|
33 const TInt KInterruptDfcQuePriority = 28; |
|
34 const TInt KDfcPriority = 2; |
|
35 |
|
36 #define FULL_RISING_EDGEMASK 0xAA |
|
37 #define FULL_FALLING_EDGEMASK 0x55 |
|
38 |
|
39 |
|
40 namespace TPS65950 |
|
41 { |
|
42 |
|
43 struct TInterruptBank |
|
44 { |
|
45 TInt iBit[8]; |
|
46 }; |
|
47 |
|
48 struct TSubInterruptBank |
|
49 { |
|
50 TUint8 iLen; |
|
51 TUint16 iRegs[6]; |
|
52 }; |
|
53 |
|
54 enum TMaskPolarity |
|
55 { |
|
56 EClearToEnable, |
|
57 ESetToEnable |
|
58 }; |
|
59 |
|
60 struct TControl |
|
61 { |
|
62 TUint16 iSetReg; |
|
63 TUint16 iClrReg; |
|
64 TUint16 iStatReg; |
|
65 TUint8 iBitMask; |
|
66 TMaskPolarity iPolarity : 8; |
|
67 }; |
|
68 |
|
69 NONSHARABLE_CLASS( TPS65950Int ) : public MInterruptDispatcher |
|
70 { |
|
71 public: |
|
72 TPS65950Int(); |
|
73 TInt Init(); |
|
74 |
|
75 virtual TInt Bind(TInt aId, TIsr aIsr, TAny* aPtr); |
|
76 virtual TInt Unbind(TInt aId); |
|
77 virtual TInt Enable(TInt aId); |
|
78 virtual TInt Disable(TInt aId); |
|
79 virtual TInt Clear(TInt aId); |
|
80 virtual TInt SetPriority(TInt aId, TInt aPriority); |
|
81 |
|
82 private: |
|
83 static void Spurious( TAny* aParam ); |
|
84 static void Dispatch( TAny* aParam ); |
|
85 static void Dfc( TAny* aParam ); |
|
86 |
|
87 TInt InitialiseTPS65950IntController(); |
|
88 |
|
89 private: |
|
90 TDfc iDfc; |
|
91 }; |
|
92 |
|
93 static SInterruptHandler TheHandlers[ TPS65950::KNumTPSInts ]; |
|
94 |
|
95 static const TControl KControl[ TPS65950::KNumTPSInts ] = |
|
96 { |
|
97 //iimr iReg group bitoffset /* |
|
98 /*0*/{ Register::PWR_IMR1, Register::PWR_IMR1, Register::PWR_ISR1, PWR_IMR1::PWR_SC_DETECT, ESetToEnable}, |
|
99 /*1*/{ Register::PWR_IMR1, Register::PWR_IMR1, Register::PWR_ISR1, PWR_IMR1::PWR_MBCHG, ESetToEnable}, |
|
100 /*2*/{ Register::PWR_IMR1, Register::PWR_IMR1, Register::PWR_ISR1, PWR_IMR1::PWR_PWROK_TIMEOUT, ESetToEnable}, |
|
101 /*3*/{ Register::PWR_IMR1, Register::PWR_IMR1, Register::PWR_ISR1, PWR_IMR1::PWR_HOT_DIE, ESetToEnable}, |
|
102 /*4*/{ Register::PWR_IMR1, Register::PWR_IMR1, Register::PWR_ISR1, PWR_IMR1::PWR_RTC_IT, ESetToEnable}, |
|
103 /*5*/{ Register::PWR_IMR1, Register::PWR_IMR1, Register::PWR_ISR1, PWR_IMR1::PWR_USB_PRES, ESetToEnable}, |
|
104 /*6*/{ Register::PWR_IMR1, Register::PWR_IMR1, Register::PWR_ISR1, PWR_IMR1::PWR_CHG_PRES, ESetToEnable}, |
|
105 /*7*/{ Register::PWR_IMR1, Register::PWR_IMR1, Register::PWR_ISR1, PWR_IMR1::PWR_CHG_PWRONS, ESetToEnable}, |
|
106 |
|
107 /*8*/{ Register::MADC_IMR1, Register::MADC_IMR1, Register::MADC_ISR1, MADC_IMR1::MADC_USB_ISR1, EClearToEnable}, |
|
108 /*9*/{ Register::MADC_IMR1, Register::MADC_IMR1, Register::MADC_ISR1, MADC_IMR1::MADC_SW2_ISR1, EClearToEnable}, |
|
109 /*10*/{ Register::MADC_IMR1, Register::MADC_IMR1, Register::MADC_ISR1, MADC_IMR1::MADC_SW1_ISR1, EClearToEnable}, |
|
110 /*11*/{ Register::MADC_IMR1, Register::MADC_IMR1, Register::MADC_ISR1, MADC_IMR1::MADC_RT_ISR1, EClearToEnable}, |
|
111 |
|
112 /*12*/{ Register::GPIO_IMR1A, Register::GPIO_IMR1A, Register::GPIO_ISR1A, GPIO_IMR1A::GPIO7ISR1, EClearToEnable}, |
|
113 /*13*/{ Register::GPIO_IMR1A, Register::GPIO_IMR1A, Register::GPIO_ISR1A, GPIO_IMR1A::GPIO6ISR1, EClearToEnable}, |
|
114 /*14*/{ Register::GPIO_IMR1A, Register::GPIO_IMR1A, Register::GPIO_ISR1A, GPIO_IMR1A::GPIO5ISR1, EClearToEnable}, |
|
115 /*15*/{ Register::GPIO_IMR1A, Register::GPIO_IMR1A, Register::GPIO_ISR1A, GPIO_IMR1A::GPIO4ISR1, EClearToEnable}, |
|
116 /*16*/{ Register::GPIO_IMR1A, Register::GPIO_IMR1A, Register::GPIO_ISR1A, GPIO_IMR1A::GPIO3ISR1, EClearToEnable}, |
|
117 /*17*/{ Register::GPIO_IMR1A, Register::GPIO_IMR1A, Register::GPIO_ISR1A, GPIO_IMR1A::GPIO2ISR1, EClearToEnable}, |
|
118 /*18*/{ Register::GPIO_IMR1A, Register::GPIO_IMR1A, Register::GPIO_ISR1A, GPIO_IMR1A::GPIO1ISR1, EClearToEnable}, |
|
119 /*19*/{ Register::GPIO_IMR1A, Register::GPIO_IMR1A, Register::GPIO_ISR1A, GPIO_IMR1A::GPIO0ISR1, EClearToEnable}, |
|
120 |
|
121 /*20*/ { Register::GPIO_IMR2A, Register::GPIO_IMR2A, Register::GPIO_ISR2A, GPIO_IMR2A::GPIO15ISR2, EClearToEnable}, |
|
122 /*22*/{ Register::GPIO_IMR2A, Register::GPIO_IMR2A, Register::GPIO_ISR2A, GPIO_IMR2A::GPIO14ISR2, EClearToEnable}, |
|
123 /*23*/{ Register::GPIO_IMR2A, Register::GPIO_IMR2A, Register::GPIO_ISR2A, GPIO_IMR2A::GPIO13ISR2, EClearToEnable}, |
|
124 /*24*/{ Register::GPIO_IMR2A, Register::GPIO_IMR2A, Register::GPIO_ISR2A, GPIO_IMR2A::GPIO12ISR2, EClearToEnable}, |
|
125 /*25*/{ Register::GPIO_IMR2A, Register::GPIO_IMR2A, Register::GPIO_ISR2A, GPIO_IMR2A::GPIO11ISR2, EClearToEnable}, |
|
126 /*26*/{ Register::GPIO_IMR2A, Register::GPIO_IMR2A, Register::GPIO_ISR2A, GPIO_IMR2A::GPIO10ISR2, EClearToEnable}, |
|
127 /*27*/{ Register::GPIO_IMR2A, Register::GPIO_IMR2A, Register::GPIO_ISR2A, GPIO_IMR2A::GPIO9ISR2, EClearToEnable}, |
|
128 /*28*/{ Register::GPIO_IMR2A, Register::GPIO_IMR2A, Register::GPIO_ISR2A, GPIO_IMR2A::GPIO8ISR2, EClearToEnable}, |
|
129 |
|
130 /*29*/{ Register::GPIO_IMR3A, Register::GPIO_IMR3A, Register::GPIO_ISR3A, GPIO_IMR3A::GPIO17ISR3, EClearToEnable}, |
|
131 /*30*/{ Register::GPIO_IMR3A, Register::GPIO_IMR3A, Register::GPIO_ISR3A, GPIO_IMR3A::GPIO16ISR3, EClearToEnable}, |
|
132 |
|
133 /*31*/{ Register::BCIIMR1A, Register::BCIIMR1A, Register::BCIISR1A, BCIIMR1A::BCI_BATSTS_ISR1, EClearToEnable}, |
|
134 /*32*/{ Register::BCIIMR1A, Register::BCIIMR1A, Register::BCIISR1A, BCIIMR1A::BCI_TBATOR1_ISR1, EClearToEnable}, |
|
135 /*33*/{ Register::BCIIMR1A, Register::BCIIMR1A, Register::BCIISR1A, BCIIMR1A::BCI_TBATOR2_ISR1, EClearToEnable}, |
|
136 /*34*/{ Register::BCIIMR1A, Register::BCIIMR1A, Register::BCIISR1A, BCIIMR1A::BCI_ICHGEOC_ISR1, EClearToEnable}, |
|
137 /*35*/{ Register::BCIIMR1A, Register::BCIIMR1A, Register::BCIISR1A, BCIIMR1A::BCI_ICHGLOW_ISR1ASTO, EClearToEnable}, |
|
138 /*36*/{ Register::BCIIMR1A, Register::BCIIMR1A, Register::BCIISR1A, BCIIMR1A::BCI_IICHGHIGH_ISR1, EClearToEnable}, |
|
139 /*37*/{ Register::BCIIMR1A, Register::BCIIMR1A, Register::BCIISR1A, BCIIMR1A::BCI_TMOVF_ISR1, EClearToEnable}, |
|
140 /*38*/{ Register::BCIIMR1A, Register::BCIIMR1A, Register::BCIISR1A, BCIIMR1A::BCI_WOVF_ISR1, EClearToEnable}, |
|
141 |
|
142 /*39*/{ Register::BCIIMR2A, Register::BCIIMR2A, Register::BCIISR2A, BCIIMR2A::BCI_ACCHGOV_ISR1, EClearToEnable}, |
|
143 /*40*/{ Register::BCIIMR2A, Register::BCIIMR2A, Register::BCIISR2A, BCIIMR2A::BCI_VBUSOV_ISR1, EClearToEnable}, |
|
144 /*41*/{ Register::BCIIMR2A, Register::BCIIMR2A, Register::BCIISR2A, BCIIMR2A::BCI_VBATOV_ISR1, EClearToEnable}, |
|
145 /*42*/{ Register::BCIIMR2A, Register::BCIIMR2A, Register::BCIISR2A, BCIIMR2A::BCI_VBATLVL_ISR1, EClearToEnable}, |
|
146 |
|
147 /*43*/{ Register::KEYP_IMR1, Register::KEYP_IMR1, Register::KEYP_ISR1, KEYP_IMR1::KEYP_ITMISR1, EClearToEnable}, |
|
148 /*44*/{ Register::KEYP_IMR1, Register::KEYP_IMR1, Register::KEYP_ISR1, KEYP_IMR1::KEYP_ITTOISR1, EClearToEnable}, |
|
149 /*45*/{ Register::KEYP_IMR1, Register::KEYP_IMR1, Register::KEYP_ISR1, KEYP_IMR1::KEYP_ITLKISR1, EClearToEnable}, |
|
150 /*46*/{ Register::KEYP_IMR1, Register::KEYP_IMR1, Register::KEYP_ISR1, KEYP_IMR1::KEYP_ITKPISR1, EClearToEnable}, |
|
151 |
|
152 /*46*/{ Register::USB_INT_EN_RISE_SET, Register::USB_INT_EN_RISE_CLR, Register::USB_INT_STS, USB_INT_STS::USB_INTSTS_IDGND, ESetToEnable }, |
|
153 /*47*/{ Register::USB_INT_EN_RISE_SET, Register::USB_INT_EN_RISE_CLR, Register::USB_INT_STS, USB_INT_STS::USB_INTSTS_SESSEND, ESetToEnable }, |
|
154 /*48*/{ Register::USB_INT_EN_RISE_SET, Register::USB_INT_EN_RISE_CLR, Register::USB_INT_STS, USB_INT_STS::USB_INTSTS_SESSVALID, ESetToEnable }, |
|
155 /*49*/{ Register::USB_INT_EN_RISE_SET, Register::USB_INT_EN_RISE_CLR, Register::USB_INT_STS, USB_INT_STS::USB_INTSTS_VBUSVALID, ESetToEnable }, |
|
156 /*50*/{ Register::USB_INT_EN_RISE_SET, Register::USB_INT_EN_RISE_CLR, Register::USB_INT_STS, USB_INT_STS::USB_INTSTS_HOSTDISCONNECT, ESetToEnable }, |
|
157 |
|
158 /*51*/{ Register::CARKIT_INT_EN_SET, Register::CARKIT_INT_EN_CLR, Register::CARKIT_INT_STS, CARKIT_INT_STS::CARKIT_CARDP, ESetToEnable }, |
|
159 /*52*/{ Register::CARKIT_INT_EN_SET, Register::CARKIT_INT_EN_CLR, Register::CARKIT_INT_STS, CARKIT_INT_STS::CARKIT_CARINTDET, ESetToEnable }, |
|
160 /*53*/{ Register::CARKIT_INT_EN_SET, Register::CARKIT_INT_EN_CLR, Register::CARKIT_INT_STS, CARKIT_INT_STS::CARKIT_IDFLOAT, ESetToEnable }, |
|
161 |
|
162 /*54*/{ Register::OTHER_INT_EN_RISE_SET, Register::OTHER_INT_EN_RISE_CLR, Register::OTHER_INT_STS, OTHER_INT_STS::OTHER_INT_VB_SESS_VLD, ESetToEnable }, |
|
163 /*55*/{ Register::OTHER_INT_EN_RISE_SET, Register::OTHER_INT_EN_RISE_CLR, Register::OTHER_INT_STS, OTHER_INT_STS::OTHER_INT_DM_HI, ESetToEnable }, |
|
164 /*56*/{ Register::OTHER_INT_EN_RISE_SET, Register::OTHER_INT_EN_RISE_CLR, Register::OTHER_INT_STS, OTHER_INT_STS::OTHER_INT_DP_HI, ESetToEnable }, |
|
165 /*57*/{ Register::OTHER_INT_EN_RISE_SET, Register::OTHER_INT_EN_RISE_CLR, Register::OTHER_INT_STS, OTHER_INT_STS::OTHER_INT_MANU, ESetToEnable }, |
|
166 /*58*/{ Register::OTHER_INT_EN_RISE_SET, Register::OTHER_INT_EN_RISE_CLR, Register::OTHER_INT_STS, OTHER_INT_STS::OTHER_INT_ABNORMAL_STRESS, ESetToEnable }, |
|
167 |
|
168 /*59*/{ Register::ID_INT_EN_RISE_SET, Register::ID_INT_EN_RISE_CLR, Register::ID_INT_STS, ID_INT_STS::ID_INTID_RES_FLOAT, ESetToEnable }, |
|
169 /*60*/{ Register::ID_INT_EN_RISE_SET, Register::ID_INT_EN_RISE_CLR, Register::ID_INT_STS, ID_INT_STS::ID_INTID_RES_440K, ESetToEnable }, |
|
170 /*61*/{ Register::ID_INT_EN_RISE_SET, Register::ID_INT_EN_RISE_CLR, Register::ID_INT_STS, ID_INT_STS::ID_INTID_RES_200K, ESetToEnable }, |
|
171 /*62*/{ Register::ID_INT_EN_RISE_SET, Register::ID_INT_EN_RISE_CLR, Register::ID_INT_STS, ID_INT_STS::ID_INTID_RES_102K, ESetToEnable }, |
|
172 |
|
173 /*63*/ { Register::CARKIT_SM_1_INT_EN_SET, Register::CARKIT_SM_1_INT_EN_CLR, Register::CARKIT_SM_1_INT_STS, CARKIT_SM_1_INT_STS::CARKIT_SM_1_PSM_ERROR, ESetToEnable }, |
|
174 /*64*/ { Register::CARKIT_SM_1_INT_EN_SET, Register::CARKIT_SM_1_INT_EN_CLR, Register::CARKIT_SM_1_INT_STS, CARKIT_SM_1_INT_STS::CARKIT_SM_1_PH_ACC, ESetToEnable }, |
|
175 /*65*/ { Register::CARKIT_SM_1_INT_EN_SET, Register::CARKIT_SM_1_INT_EN_CLR, Register::CARKIT_SM_1_INT_STS, CARKIT_SM_1_INT_STS::CARKIT_SM_1_CHARGER, ESetToEnable }, |
|
176 /*66*/ { Register::CARKIT_SM_1_INT_EN_SET, Register::CARKIT_SM_1_INT_EN_CLR, Register::CARKIT_SM_1_INT_STS, CARKIT_SM_1_INT_STS::CARKIT_SM_1_USB_HOST, ESetToEnable }, |
|
177 /*67*/ { Register::CARKIT_SM_1_INT_EN_SET, Register::CARKIT_SM_1_INT_EN_CLR, Register::CARKIT_SM_1_INT_STS, CARKIT_SM_1_INT_STS::CARKIT_SM_1_USB_OTG_B, ESetToEnable }, |
|
178 /*68*/ { Register::CARKIT_SM_1_INT_EN_SET, Register::CARKIT_SM_1_INT_EN_CLR, Register::CARKIT_SM_1_INT_STS, CARKIT_SM_1_INT_STS::CARKIT_SM_1_CARKIT, ESetToEnable }, |
|
179 /*69*/ { Register::CARKIT_SM_1_INT_EN_SET, Register::CARKIT_SM_1_INT_EN_CLR, Register::CARKIT_SM_1_INT_STS, CARKIT_SM_1_INT_STS::CARKIT_SM_1_DISCONNECTED, ESetToEnable }, |
|
180 |
|
181 /*70*/ { Register::CARKIT_SM_2_INT_EN_SET, Register::CARKIT_SM_2_INT_EN_CLR, Register::CARKIT_SM_2_INT_STS, CARKIT_SM_2_INT_STS::CARKIT_SM_2_STOP_PLS_MISS, ESetToEnable }, |
|
182 /*71*/ { Register::CARKIT_SM_2_INT_EN_SET, Register::CARKIT_SM_2_INT_EN_CLR, Register::CARKIT_SM_2_INT_STS, CARKIT_SM_2_INT_STS::CARKIT_SM_2_STEREO_TO_MONO, ESetToEnable }, |
|
183 /*72*/ { Register::CARKIT_SM_2_INT_EN_SET, Register::CARKIT_SM_2_INT_EN_CLR, Register::CARKIT_SM_2_INT_STS, CARKIT_SM_2_INT_STS::CARKIT_SM_2_PHONE_UART, ESetToEnable }, |
|
184 /*73*/ { Register::CARKIT_SM_2_INT_EN_SET, Register::CARKIT_SM_2_INT_EN_CLR, Register::CARKIT_SM_2_INT_STS, CARKIT_SM_2_INT_STS::CARKIT_SM_2_PH_NO_ACK, ESetToEnable } |
|
185 }; |
|
186 |
|
187 |
|
188 const static TInterruptBank pwrBank = { |
|
189 ETPS65950_IRQ_PWR_CHG_PWRONS, |
|
190 ETPS65950_IRQ_PWR_CHG_PRES, |
|
191 ETPS65950_IRQ_PWR_USB_PRES, |
|
192 ETPS65950_IRQ_PWR_RTC_IT, |
|
193 ETPS65950_IRQ_PWR_HOT_DIE, |
|
194 ETPS65950_IRQ_PWR_PWROK_TIMEOUT, |
|
195 ETPS65950_IRQ_PWR_MBCHG, |
|
196 ETPS65950_IRQ_PWR_SC_DETECT, |
|
197 }; |
|
198 |
|
199 const static TInterruptBank madcBank = { |
|
200 ETPS65950_IRQ_MADC_RT_ISR1, |
|
201 ETPS65950_IRQ_MADC_SW1_ISR1, |
|
202 ETPS65950_IRQ_MADC_SW2_ISR1, |
|
203 ETPS65950_IRQ_MADC_USB_ISR1, |
|
204 }; |
|
205 |
|
206 const static TInterruptBank gpioBank0 = { |
|
207 ETPS65950_IRQ_GPIO_0ISR1, |
|
208 ETPS65950_IRQ_GPIO_1ISR1, |
|
209 ETPS65950_IRQ_GPIO_2ISR1, |
|
210 ETPS65950_IRQ_GPIO_3ISR1, |
|
211 ETPS65950_IRQ_GPIO_4ISR1, |
|
212 ETPS65950_IRQ_GPIO_5ISR1, |
|
213 ETPS65950_IRQ_GPIO_6ISR1, |
|
214 ETPS65950_IRQ_GPIO_7ISR2 |
|
215 }; |
|
216 |
|
217 const static TInterruptBank gpioBank1 = { |
|
218 ETPS65950_IRQ_GPIO_8ISR2, |
|
219 ETPS65950_IRQ_GPIO_9ISR2, |
|
220 ETPS65950_IRQ_GPIO_10ISR2, |
|
221 ETPS65950_IRQ_GPIO_11ISR2, |
|
222 ETPS65950_IRQ_GPIO_12ISR2, |
|
223 ETPS65950_IRQ_GPIO_13ISR2, |
|
224 ETPS65950_IRQ_GPIO_14ISR2, |
|
225 ETPS65950_IRQ_GPIO_15ISR2 |
|
226 }; |
|
227 |
|
228 const static TInterruptBank gpioBank2 = { |
|
229 ETPS65950_IRQ_GPIO16ISR3, |
|
230 ETPS65950_IRQ_GPIO17ISR3 |
|
231 }; |
|
232 |
|
233 const static TInterruptBank bciBank0 = { |
|
234 ETPS65950_IRQ_BCI_WOVF_ISR1, |
|
235 ETPS65950_IRQ_BCI_TMOVF_ISR1, |
|
236 ETPS65950_IRQ_BCI_IICHGHIGH_ISR1, |
|
237 ETPS65950_IRQ_BCI_ICHGLOW_ISR1ASTO, |
|
238 ETPS65950_IRQ_BCI_ICHGEOC_ISR1, |
|
239 ETPS65950_IRQ_BCI_TBATOR2_ISR1, |
|
240 ETPS65950_IRQ_BCI_TBATOR1_ISR1, |
|
241 ETPS65950_IRQ_BCI_BATSTS_ISR1 |
|
242 }; |
|
243 |
|
244 const static TInterruptBank bciBank1 = { |
|
245 ETPS65950_IRQ_BCI_VBATLVL_ISR1, |
|
246 ETPS65950_IRQ_BCI_VBATOV_ISR1, |
|
247 ETPS65950_IRQ_BCI_VBUSOV_ISR1, |
|
248 ETPS65950_IRQ_BCI_ACCHGOV_ISR1 |
|
249 }; |
|
250 |
|
251 const static TInterruptBank keypBank = { |
|
252 ETPS65950_IRQ_KEYP_ITKPISR1, |
|
253 ETPS65950_IRQ_KEYP_ITLKISR1, |
|
254 ETPS65950_IRQ_KEYP_ITTOISR1, |
|
255 ETPS65950_IRQ_KEYP_ITMISR1, |
|
256 }; |
|
257 |
|
258 const static TInterruptBank usbINTSTSBank = { |
|
259 ETPS65950_IRQ_USB_INTSTS_IDGND, |
|
260 ETPS65950_IRQ_USB_INTSTS_SESSEND, |
|
261 ETPS65950_IRQ_USB_INTSTS_SESSVALID, |
|
262 ETPS65950_IRQ_USB_INTSTS_VBUSVALID, |
|
263 ETPS65950_IRQ_USB_INTSTS_HOSTDISCONNECT |
|
264 }; |
|
265 |
|
266 const static TInterruptBank usbCARKITBank = { |
|
267 ETPS65950_IRQ_USB_CARKIT_CARDP, |
|
268 ETPS65950_IRQ_USB_CARKIT_CARINTDET, |
|
269 ETPS65950_IRQ_USB_CARKIT_IDFLOAT |
|
270 }; |
|
271 |
|
272 const static TInterruptBank usbOTHERBank = { |
|
273 ETPS65950_IRQ_USB_OTHER_INT_VB_SESS_VLD, |
|
274 ETPS65950_IRQ_USB_OTHER_INT_DM_HI, |
|
275 ETPS65950_IRQ_USB_OTHER_INT_DP_HI, |
|
276 ETPS65950_IRQ_USB_OTHER_INT_MANU, |
|
277 ETPS65950_IRQ_USB_OTHER_INT_ABNORMAL_STRESS |
|
278 }; |
|
279 |
|
280 const static TInterruptBank usbIDINTBank = { |
|
281 ETPS65950_IRQ_USB_ID_INT_ID_RES_FLOAT, |
|
282 ETPS65950_IRQ_USB_ID_INT_ID_RES_440K, |
|
283 ETPS65950_IRQ_USB_ID_INT_ID_RES_200K, |
|
284 ETPS65950_IRQ_USB_ID_INT_ID_RES_102K |
|
285 }; |
|
286 |
|
287 const static TInterruptBank usbSM1Bank = { |
|
288 ETPS65950_IRQ_USB_CARKIT_SM_1_PSM_ERROR, |
|
289 ETPS65950_IRQ_USB_CARKIT_SM_1_PH_ACC, |
|
290 ETPS65950_IRQ_USB_CARKIT_SM_1_CHARGER, |
|
291 ETPS65950_IRQ_USB_CARKIT_SM_1_USB_HOST, |
|
292 ETPS65950_IRQ_USB_CARKIT_SM_1_USB_OTG_B, |
|
293 ETPS65950_IRQ_USB_CARKIT_SM_1_CARKIT |
|
294 }; |
|
295 |
|
296 const static TInterruptBank usbSM2Bank = { |
|
297 ETPS65950_IRQ_USB_CARKIT_SM_2_STOP_PLS_MISS, |
|
298 ETPS65950_IRQ_USB_CARKIT_SM_2_STEREO_TO_MONO, |
|
299 ETPS65950_IRQ_USB_CARKIT_SM_2_PHONE_UART, |
|
300 ETPS65950_IRQ_USB_CARKIT_SM_2_PH_NO_ACK |
|
301 }; |
|
302 |
|
303 const static TInterruptBank* TheMapTable [6][6] = { |
|
304 //maps against PIH_ISR bits |
|
305 //reg banks sub modules |
|
306 {&gpioBank0, &gpioBank1, &gpioBank2, NULL, NULL, NULL}, |
|
307 {&keypBank, NULL, NULL, NULL, NULL, NULL}, |
|
308 {&bciBank0, &bciBank1, NULL, NULL, NULL, NULL}, |
|
309 {&madcBank, NULL, NULL, NULL, NULL, NULL}, |
|
310 {&usbINTSTSBank, &usbCARKITBank, &usbOTHERBank, &usbIDINTBank, &usbSM1Bank, &usbSM2Bank}, |
|
311 {&pwrBank, NULL, NULL, NULL, NULL, NULL} |
|
312 }; |
|
313 |
|
314 const static TSubInterruptBank subBank[6] = { |
|
315 /*gpio*/{3,{Register::GPIO_ISR1A,Register::GPIO_ISR2A,Register::GPIO_ISR3A,NULL,NULL,NULL}}, |
|
316 /*keyp*/{1,{Register::KEYP_ISR1,NULL,NULL,NULL,NULL,NULL}}, |
|
317 /*bci*/ {2,{Register::BCIISR1A,Register::BCIISR2A,NULL,NULL,NULL,NULL}}, |
|
318 /*madc*/{1,{Register::MADC_ISR1,NULL,NULL,NULL,NULL,NULL}}, |
|
319 /*usb*/ {6,{Register::USB_INT_STS,Register::CARKIT_INT_STS,Register::OTHER_INT_STS,Register::ID_INT_STS, Register::CARKIT_SM_1_INT_STS, Register::CARKIT_SM_2_INT_STS}}, |
|
320 /*pwr*/ {1,{Register::PWR_ISR1,NULL,NULL,NULL,NULL,NULL}}, |
|
321 }; |
|
322 |
|
323 |
|
324 TPS65950Int::TPS65950Int() |
|
325 : iDfc( Dfc, this, KDfcPriority ) |
|
326 { |
|
327 for( TInt i = 0; i < TPS65950::KNumTPSInts; ++i ) |
|
328 { |
|
329 TheHandlers[ i ].iIsr = Spurious; |
|
330 TheHandlers[ i ].iPtr = (TAny*)( KTPS65950IrqFirst + i ); |
|
331 } |
|
332 } |
|
333 |
|
334 TInt TPS65950Int::Init() |
|
335 { |
|
336 iDfc.SetDfcQ( TheInterruptDfcQue ); |
|
337 |
|
338 TInt r = InitialiseTPS65950IntController(); |
|
339 |
|
340 if( KErrNone == r ) |
|
341 { |
|
342 TInt r = Interrupt::Bind( EOmap3530_IRQ7_SYS_NIRQ, Dispatch, this ); |
|
343 if( KErrNone == r ) |
|
344 { |
|
345 r = Interrupt::Enable( EOmap3530_IRQ7_SYS_NIRQ ); |
|
346 } |
|
347 } |
|
348 |
|
349 if( KErrNone == r ) |
|
350 { |
|
351 Register( EIrqRangeBasePsu ); |
|
352 } |
|
353 return r; |
|
354 } |
|
355 |
|
356 |
|
357 TInt TPS65950Int::InitialiseTPS65950IntController() |
|
358 { |
|
359 __KTRACE_OPT(KTPS65950,Kern::Printf("+TPS65950Int:InitIntController")); |
|
360 |
|
361 struct TInitRegList |
|
362 { |
|
363 TUint16 iReg; |
|
364 TUint8 iValue; |
|
365 }; |
|
366 |
|
367 static const TInitRegList KInitList[] = |
|
368 { |
|
369 { GPIO_SIH_CTRL::Addr, GPIO_SIH_CTRL::SIH_PENDDIS | GPIO_SIH_CTRL::SIH_COR | GPIO_SIH_CTRL::SIH_EXCLEN }, |
|
370 // { Register::GPIO_CTRL, 0x00 }, |
|
371 { Register::GPIO_IMR1A , 0xff }, |
|
372 { Register::GPIO_IMR2A , 0xff }, |
|
373 { Register::GPIO_IMR3A , 0xff }, |
|
374 { Register::GPIO_IMR1B , 0xff }, |
|
375 { Register::GPIO_IMR2B , 0xff }, |
|
376 { Register::GPIO_IMR3B , 0xff }, |
|
377 { Register::GPIO_EDR1, 0x00 }, |
|
378 { Register::GPIO_EDR2, 0x00 }, |
|
379 { Register::GPIO_EDR3, 0x00 }, |
|
380 { Register::GPIO_EDR4, 0x00 }, |
|
381 { Register::GPIO_EDR5, 0x00 }, |
|
382 { Register::USB_INT_EN_RISE_CLR, 0x1f }, |
|
383 { Register::USB_INT_EN_FALL_CLR, 0x1f }, |
|
384 { Register::CARKIT_INT_EN_CLR, 0x1f }, |
|
385 { Register::OTHER_INT_EN_RISE_CLR,0xe3 }, |
|
386 { Register::OTHER_INT_EN_FALL_CLR,0xe3 }, |
|
387 { Register::ID_INT_EN_RISE_CLR, 0x0f }, |
|
388 { Register::ID_INT_EN_FALL_CLR, 0x0f }, |
|
389 { Register::CARKIT_SM_1_INT_EN_CLR,0xff }, |
|
390 { Register::CARKIT_SM_2_INT_EN_CLR,0xff }, |
|
391 { KEYP_SIH_CTRL::Addr, KEYP_SIH_CTRL::SIH_PENDDIS | KEYP_SIH_CTRL::SIH_COR | KEYP_SIH_CTRL::SIH_EXCLEN }, |
|
392 { Register::KEYP_IMR1, 0x0f }, |
|
393 { Register::KEYP_IMR2, 0x0f }, |
|
394 { Register::KEYP_EDR, FULL_RISING_EDGEMASK }, |
|
395 { BCISIHCTRL::Addr, BCISIHCTRL::SIH_PENDDIS | BCISIHCTRL::SIH_COR | BCISIHCTRL::SIH_EXCLEN }, |
|
396 { Register::BCIIMR1A, 0xff }, |
|
397 { Register::BCIIMR2A, 0xff }, |
|
398 { Register::BCIIMR1B, 0xff }, |
|
399 { Register::BCIIMR2B, 0xff }, |
|
400 { Register::BCIEDR1, FULL_RISING_EDGEMASK }, |
|
401 { Register::BCIEDR2, FULL_RISING_EDGEMASK }, |
|
402 { Register::BCIEDR3, FULL_RISING_EDGEMASK }, |
|
403 { MADC_SIH_CTRL::Addr, MADC_SIH_CTRL::SIH_PENDDIS | MADC_SIH_CTRL::SIH_COR | MADC_SIH_CTRL::SIH_EXCLEN }, |
|
404 { Register::MADC_IMR1, 0x0f }, |
|
405 { Register::MADC_IMR2, 0x0f }, |
|
406 { Register::MADC_EDR, FULL_RISING_EDGEMASK }, |
|
407 { PWR_SIH_CTRL::Addr, PWR_SIH_CTRL::SIH_PENDDIS | PWR_SIH_CTRL::SIH_COR | PWR_SIH_CTRL::SIH_EXCLEN }, |
|
408 { Register::PWR_IMR1, 0xff }, |
|
409 { Register::PWR_IMR2, 0xff }, |
|
410 { Register::PWR_EDR1, FULL_FALLING_EDGEMASK }, |
|
411 { Register::PWR_EDR2, FULL_FALLING_EDGEMASK } |
|
412 }; |
|
413 |
|
414 const TInt KInitListCount = (sizeof( KInitList ) / sizeof( KInitList[0] ) ); |
|
415 |
|
416 static const TUint16 KClearList[] = |
|
417 { |
|
418 Register::CARKIT_INT_LATCH, |
|
419 Register::USB_INT_LATCH, |
|
420 Register::OTHER_INT_LATCH, |
|
421 Register::ID_INT_LATCH, |
|
422 Register::CARKIT_SM_1_INT_LATCH, |
|
423 Register::CARKIT_SM_2_INT_LATCH, |
|
424 Register::GPIO_ISR1A, |
|
425 Register::GPIO_ISR2A, |
|
426 Register::GPIO_ISR3A, |
|
427 Register::KEYP_ISR1, |
|
428 Register::BCIISR1A, |
|
429 Register::BCIISR2A, |
|
430 Register::MADC_ISR1, |
|
431 Register::PWR_ISR1 |
|
432 }; |
|
433 |
|
434 const TInt KClearListCount = (sizeof( KClearList ) / sizeof( KClearList[0] ) ); |
|
435 |
|
436 |
|
437 TInt r = KErrNone; |
|
438 |
|
439 // Disable all interrupts |
|
440 for( TInt i = 0; (i < KInitListCount) && (KErrNone == r); ++i ) |
|
441 { |
|
442 r = WriteSync( KInitList[i].iReg, KInitList[i].iValue ); |
|
443 } |
|
444 |
|
445 // Clear all interrupts |
|
446 for( TInt i = 0; (i < KClearListCount) && (KErrNone == r); ++i ) |
|
447 { |
|
448 TUint8 dummy; |
|
449 r = ReadSync( KClearList[i], dummy ); |
|
450 } |
|
451 |
|
452 __KTRACE_OPT(KTPS65950,Kern::Printf("-TPS65950Int:InitIntController:%d", r)); |
|
453 |
|
454 return r; |
|
455 } |
|
456 |
|
457 |
|
458 void TPS65950Int::Spurious( TAny* aParam ) |
|
459 { |
|
460 Kern::Fault("TPS65950SpurioustInt", (TInt)aParam ); |
|
461 } |
|
462 |
|
463 TInt TPS65950Int::Bind(TInt aId, TIsr aIsr, TAny* aPtr) |
|
464 { |
|
465 __KTRACE_OPT(KTPS65950,Kern::Printf("+tps65950:Bind:%x->%x", aId, aIsr )); |
|
466 |
|
467 TInt r = KErrNone; |
|
468 |
|
469 if( (TUint)aId < KTPS65950IrqLast ) |
|
470 { |
|
471 TUint tblOffset = aId - KTPS65950IrqFirst; |
|
472 |
|
473 TInt irq=__SPIN_LOCK_IRQSAVE_W(BeagleExtIVTLock); |
|
474 TheHandlers[tblOffset ].iIsr = aIsr; |
|
475 TheHandlers[tblOffset].iPtr = aPtr; |
|
476 __SPIN_UNLOCK_IRQRESTORE_W(BeagleExtIVTLock,irq); |
|
477 |
|
478 } |
|
479 else |
|
480 { |
|
481 r = KErrArgument; |
|
482 } |
|
483 |
|
484 __KTRACE_OPT(KTPS65950,Kern::Printf("-tps65950:Bind:%x:%d", aId, r )); |
|
485 return r; |
|
486 } |
|
487 |
|
488 TInt TPS65950Int::Unbind(TInt aId) |
|
489 { |
|
490 __KTRACE_OPT(KTPS65950,Kern::Printf("+tps65950:Unbind:%x", aId )); |
|
491 |
|
492 TInt r = KErrNone; |
|
493 |
|
494 if( (TUint)aId < KTPS65950IrqLast ) |
|
495 { |
|
496 TUint tblOffset = aId - KTPS65950IrqFirst; |
|
497 TInt irq=__SPIN_LOCK_IRQSAVE_W(BeagleExtIVTLock); |
|
498 TheHandlers[tblOffset ].iIsr = Spurious; |
|
499 TheHandlers[tblOffset ].iPtr = NULL; |
|
500 __SPIN_UNLOCK_IRQRESTORE_W(BeagleExtIVTLock,irq); |
|
501 } |
|
502 else |
|
503 { |
|
504 r = KErrArgument; |
|
505 } |
|
506 |
|
507 __KTRACE_OPT(KTPS65950,Kern::Printf("-tps65950:Unbind:%x:%d", aId, r )); |
|
508 return r; |
|
509 } |
|
510 |
|
511 TInt TPS65950Int::Enable(TInt aId) |
|
512 { |
|
513 __KTRACE_OPT(KTPS65950,Kern::Printf("+tps65950:Enable:%x", aId )); |
|
514 |
|
515 TInt r = KErrNone; |
|
516 |
|
517 if( (TUint)aId < KTPS65950IrqLast ) |
|
518 { |
|
519 CHECK_PRECONDITIONS(MASK_NOT_ISR | MASK_NOT_IDFC,"tps65950::InterruptEnable Cant enable a slow src in ISR Context"); |
|
520 |
|
521 TUint tblOffset = aId - KTPS65950IrqFirst; |
|
522 |
|
523 TInt irq=__SPIN_LOCK_IRQSAVE_R(BeagleExtIVTLock); |
|
524 if( TheHandlers[ tblOffset ].iIsr == Spurious ) |
|
525 { |
|
526 r = KErrNotReady; |
|
527 } |
|
528 __SPIN_UNLOCK_IRQRESTORE_R(BeagleExtIVTLock,irq); |
|
529 |
|
530 if( r != KErrNone ) |
|
531 { |
|
532 __KTRACE_OPT(KTPS65950,Kern::Printf("=tps65950:Enable:%d NOT BOUND", aId )); |
|
533 } |
|
534 else |
|
535 { |
|
536 const TControl& control = KControl[ tblOffset ]; |
|
537 |
|
538 TUint8 val; |
|
539 ReadSync( control.iSetReg, val ); |
|
540 if( EClearToEnable == control.iPolarity ) |
|
541 { |
|
542 ClearSetSync( control.iSetReg, control.iBitMask, KSetNone ); |
|
543 } |
|
544 else |
|
545 { |
|
546 ClearSetSync( control.iSetReg, KClearNone, control.iBitMask ); |
|
547 } |
|
548 ReadSync( control.iSetReg, val ); |
|
549 } |
|
550 } |
|
551 else |
|
552 { |
|
553 r = KErrArgument; |
|
554 } |
|
555 |
|
556 __KTRACE_OPT(KTPS65950,Kern::Printf("-tps65950:Enable:%x:%d", aId, r )); |
|
557 return r; |
|
558 } |
|
559 |
|
560 TInt TPS65950Int::Disable(TInt aId) |
|
561 { |
|
562 __KTRACE_OPT(KTPS65950,Kern::Printf("+tps65950:Disable:%x", aId )); |
|
563 |
|
564 TInt r = KErrNone; |
|
565 |
|
566 if( (TUint)aId < KTPS65950IrqLast ) |
|
567 { |
|
568 CHECK_PRECONDITIONS(MASK_NOT_ISR | MASK_NOT_IDFC,"tps65950::InterruptDisable Cant disable a slow src in ISR Context"); |
|
569 |
|
570 TUint tblOffset = aId - KTPS65950IrqFirst; |
|
571 |
|
572 TInt irq=__SPIN_LOCK_IRQSAVE_R(BeagleExtIVTLock); |
|
573 if( TheHandlers[ tblOffset ].iIsr == Spurious ) |
|
574 { |
|
575 r = KErrNotReady; |
|
576 } |
|
577 __SPIN_UNLOCK_IRQRESTORE_R(BeagleExtIVTLock,irq); |
|
578 |
|
579 if( r != KErrNone ) |
|
580 { |
|
581 __KTRACE_OPT(KTPS65950,Kern::Printf("=tps65950:Disable:%d NOT BOUND", aId )); |
|
582 } |
|
583 else |
|
584 { |
|
585 const TControl& control = KControl[ tblOffset ]; |
|
586 |
|
587 if( EClearToEnable == control.iPolarity ) |
|
588 { |
|
589 ClearSetSync( control.iClrReg, KClearNone, control.iBitMask ); |
|
590 } |
|
591 else |
|
592 { |
|
593 ClearSetSync( control.iSetReg, control.iBitMask, KSetNone ); |
|
594 } |
|
595 } |
|
596 } |
|
597 else |
|
598 { |
|
599 r = KErrArgument; |
|
600 } |
|
601 |
|
602 __KTRACE_OPT(KTPS65950,Kern::Printf("-tps65950:Disable:%x:%d", aId, r )); |
|
603 return r; |
|
604 } |
|
605 |
|
606 TInt TPS65950Int::Clear(TInt aId) |
|
607 { |
|
608 __KTRACE_OPT(KTPS65950,Kern::Printf("+tps65950:Clear:%x", aId )); |
|
609 |
|
610 TInt r = KErrNone; |
|
611 |
|
612 if( (TUint)aId < KTPS65950IrqLast ) |
|
613 { |
|
614 CHECK_PRECONDITIONS(MASK_NOT_ISR,"tps65950::InterruptClear Cant clear a slow src in ISR Context"); |
|
615 |
|
616 TUint tblOffset = aId - KTPS65950IrqFirst; |
|
617 TUint8 value; |
|
618 //clear on read ! //we may lose some of the other ints if many enabled |
|
619 ReadSync( KControl[ tblOffset ].iStatReg, value ); |
|
620 } |
|
621 else |
|
622 { |
|
623 r = KErrArgument; |
|
624 } |
|
625 |
|
626 __KTRACE_OPT(KTPS65950,Kern::Printf("-tps65950:Clear:%x:%d", aId, r )); |
|
627 return r; |
|
628 } |
|
629 |
|
630 TInt TPS65950Int::SetPriority(TInt aId, TInt aPriority) |
|
631 { |
|
632 __KTRACE_OPT(KTPS65950,Kern::Printf("tps65950:SetPriority:%x", aId )); |
|
633 return KErrNotSupported; |
|
634 } |
|
635 |
|
636 |
|
637 void TPS65950Int::Dispatch(TAny * aParam ) |
|
638 { |
|
639 Interrupt::Disable(EOmap3530_IRQ7_SYS_NIRQ); |
|
640 reinterpret_cast<TPS65950Int*>(aParam)->iDfc.Add(); |
|
641 } |
|
642 |
|
643 void TPS65950Int::Dfc( TAny* aParam ) |
|
644 { |
|
645 __KTRACE_OPT(KTPS65950,Kern::Printf("+tps65950Int:Dfc" )); |
|
646 |
|
647 TUint8 highVectors=0; |
|
648 TUint8 subVector=0; |
|
649 |
|
650 ReadSync( PIH_ISR_P1::Addr, highVectors ); |
|
651 __ASSERT_DEBUG( highVectors != 0,Kern::Fault("tps65950 int signalled but no vector ",highVectors)); |
|
652 |
|
653 for(TInt i=0; i<=5;i++,highVectors >>=1) |
|
654 { |
|
655 if(highVectors & 0x1) |
|
656 { |
|
657 for(TInt8 j=0;j<subBank[i].iLen;j++) |
|
658 { |
|
659 ReadSync( subBank[i].iRegs[j], subVector ); |
|
660 for(TInt k=0;k < 8;k++) |
|
661 { |
|
662 if(subVector & 0x1) |
|
663 { |
|
664 TInt tblOffset = TheMapTable[i][j]->iBit[k] - KTPS65950IrqFirst; |
|
665 |
|
666 __KTRACE_OPT(KTPS65950,Kern::Printf("=tps65950:Dfc:BIT_%d HIGH on REG %x VECTOR is %x ISR %x", |
|
667 k,subBank[i].iRegs[j], tblOffset, TheHandlers[tblOffset].iIsr)); |
|
668 |
|
669 (TheHandlers[tblOffset].iIsr)(TheHandlers[tblOffset].iPtr); |
|
670 } |
|
671 subVector >>= 1; |
|
672 } |
|
673 } |
|
674 } |
|
675 } |
|
676 Interrupt::Enable(EOmap3530_IRQ7_SYS_NIRQ); |
|
677 |
|
678 __KTRACE_OPT(KTPS65950,Kern::Printf("-tps65950:Dfc" )); |
|
679 } |
|
680 |
|
681 |
|
682 } // namespace TPS65950 |
|
683 |
|
684 |
|
685 GLDEF_C TInt InitInterrupts() |
|
686 { |
|
687 TInt r = Kern::DfcQCreate( TheInterruptDfcQue, KInterruptDfcQuePriority, &KInterruptDfcQueName ); |
|
688 if( KErrNone == r ) |
|
689 { |
|
690 r = KErrNoMemory; |
|
691 TPS65950::TPS65950Int* dispatcher = new TPS65950::TPS65950Int; |
|
692 if( dispatcher ) |
|
693 { |
|
694 r = dispatcher->Init(); |
|
695 } |
|
696 } |
|
697 return r; |
|
698 } |
|
699 |
|
700 |