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1 // Copyright (c) 2009 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of the License "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: |
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14 // |
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15 |
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16 #ifndef TPS65950_REGISTERS_H |
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17 #define TPS65950_REGISTERS_H |
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18 |
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19 #include <e32cmn.h> |
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20 |
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21 namespace TPS65950 |
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22 { |
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23 |
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24 namespace Register |
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25 { |
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26 const TUint KGroupShift = 8; |
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27 const TUint KRegisterMask = 0xFF; |
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28 const TUint KGroupMask = 0xFF00; |
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29 |
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30 enum TGroup |
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31 { |
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32 EGroup12 = (0 << KGroupShift), |
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33 EGroup48 = (1 << KGroupShift), |
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34 EGroup49 = (2 << KGroupShift), |
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35 EGroup4a = (3 << KGroupShift), |
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36 EGroup4b = (4 << KGroupShift) |
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37 }; |
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38 |
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39 enum TGroup12Registers |
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40 { |
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41 VDD1_SR_CONTROL = EGroup12, |
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42 VDD2_SR_CONTROL |
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43 }; |
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44 |
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45 |
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46 enum TGroup48Registers |
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47 { |
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48 VENDOR_ID_LO = EGroup48, |
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49 VENDOR_ID_HI, |
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50 PRODUCT_ID_LO, |
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51 PRODUCT_ID_HI, |
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52 FUNC_CTRL, |
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53 FUNC_CTRL_SET, |
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54 FUNC_CTRL_CLR, |
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55 IFC_CTRL, |
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56 IFC_CTRL_SET, |
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57 IFC_CTRL_CLR, |
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58 OTG_CTRL, |
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59 OTG_CTRL_SET, |
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60 OTG_CTRL_CLR, |
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61 USB_INT_EN_RISE, |
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62 USB_INT_EN_RISE_SET, |
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63 USB_INT_EN_RISE_CLR, |
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64 USB_INT_EN_FALL, |
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65 USB_INT_EN_FALL_SET, |
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66 USB_INT_EN_FALL_CLR, |
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67 USB_INT_STS, |
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68 USB_INT_LATCH, |
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69 DEBUG, |
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70 SCRATCH_REG, |
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71 SCRATCH_REG_SET, |
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72 SCRATCH_REG_CLR, |
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73 CARKIT_CTRL, |
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74 CARKIT_CTRL_SET, |
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75 CARKIT_CTRL_CLR, |
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76 CARKIT_INT_DELAY, |
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77 CARKIT_INT_EN, |
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78 CARKIT_INT_EN_SET, |
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79 CARKIT_INT_EN_CLR, |
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80 CARKIT_INT_STS, |
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81 CARKIT_INT_LATCH, |
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82 CARKIT_PLS_CTRL, |
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83 CARKIT_PLS_CTRL_SET, |
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84 CARKIT_PLS_CTRL_CLR, |
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85 TRANS_POS_WIDTH, |
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86 TRANS_NEG_WIDTH, |
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87 RCV_PLTY_RECOVERY, |
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88 MCPC_CTRL = 0x30, |
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89 MCPC_CTRL_SET, |
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90 MCPC_CTRL_CLR, |
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91 MCPC_IO_CTRL, |
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92 MCPC_IO_CTRL_SET, |
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93 MCPC_IO_CTRL_CLR, |
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94 MCPC_CTRL2, |
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95 MCPC_CTRL2_SET, |
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96 MCPC_CTRL2_CLR, |
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97 OTHER_FUNC_CTRL = EGroup48 + 0x80, |
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98 OTHER_FUNC_CTRL_SET, |
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99 OTHER_FUNC_CTRL_CLR, |
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100 OTHER_IFC_CTRL, |
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101 OTHER_IFC_CTRL_SET, |
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102 OTHER_IFC_CTRL_CLR, |
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103 OTHER_INT_EN_RISE, |
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104 OTHER_INT_EN_RISE_SET, |
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105 OTHER_INT_EN_RISE_CLR, |
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106 OTHER_INT_EN_FALL, |
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107 OTHER_INT_EN_FALL_SET, |
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108 OTHER_INT_EN_FALL_CLR, |
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109 OTHER_INT_STS, |
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110 OTHER_INT_LATCH, |
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111 ID_INT_EN_RISE, |
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112 ID_INT_EN_RISE_SET, |
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113 ID_INT_EN_RISE_CLR, |
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114 ID_INT_EN_FALL, |
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115 ID_INT_EN_FALL_SET, |
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116 ID_INT_EN_FALL_CLR, |
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117 ID_INT_STS, |
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118 ID_INT_LATCH, |
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119 ID_STATUS, |
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120 CARKIT_SM_1_INT_EN, |
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121 CARKIT_SM_1_INT_EN_SET, |
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122 CARKIT_SM_1_INT_EN_CLR, |
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123 CARKIT_SM_1_INT_STS, |
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124 CARKIT_SM_1_INT_LATCH, |
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125 CARKIT_SM_2_INT_EN, |
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126 CARKIT_SM_2_INT_EN_SET, |
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127 CARKIT_SM_2_INT_EN_CLR, |
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128 CARKIT_SM_2_INT_STS, |
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129 CARKIT_SM_2_INT_LATCH, |
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130 CARKIT_SM_CTRL, |
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131 CARKIT_SM_CTRL_SET, |
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132 CARKIT_SM_CTRL_CLR, |
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133 CARKIT_SM_CMD, |
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134 CARKIT_SM_CMD_SET, |
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135 CARKIT_SM_CMD_CLR, |
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136 CARKIT_SM_CMD_STS, |
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137 CARKIT_SM_STATUS, |
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138 CARKIT_SM_NEXT_STATUS, |
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139 CARKIT_SM_ERR_STATUS, |
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140 CARKIT_SM_CTRL_STATE, |
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141 POWER_CTRL, |
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142 POWER_CTRL_SET, |
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143 POWER_CTRL_CLR, |
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144 OTHER_IFC_CTRL2, |
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145 OTHER_IFC_CTRL2_SET, |
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146 OTHER_IFC_CTRL2_CLR, |
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147 REG_CTRL_EN, |
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148 REG_CTRL_EN_SET, |
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149 REG_CTRL_EN_CLR, |
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150 REG_CTRL_ERROR, |
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151 OTHER_FUNC_CTRL2, |
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152 OTHER_FUNC_CTRL2_SET, |
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153 OTHER_FUNC_CTRL2_CLR, |
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154 CARKIT_ANA_CTRL, |
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155 CARKIT_ANA_CTRL_SET, |
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156 CARKIT_ANA_CTRL_CLR, |
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157 VBUS_DEBOUNCE = EGroup48 + 0xC0, |
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158 ID_DEBOUNCE, |
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159 TPH_DP_CON_MIN, |
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160 TPH_DP_CON_MAX, |
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161 TCR_DP_CON_MIN, |
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162 TCR_DP_CON_MAX, |
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163 TPH_DP_PD_SHORT, |
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164 TPH_CMD_DLY, |
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165 TPH_DET_RST, |
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166 TPH_AUD_BIAS, |
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167 TCR_UART_DET_MIN, |
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168 TCR_UART_DET_MAX, |
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169 TPH_ID_INT_PW = EGroup48 + 0xCC, |
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170 TACC_ID_INT_WAIT, |
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171 TACC_ID_INT_PW, |
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172 TPH_CMD_WAIT = EGroup48 + 0xD0, |
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173 TPH_ACK_WAIT, |
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174 TPH_DP_DISC_DET, |
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175 VBAT_TIMER, |
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176 CARKIT_4W_DEBUG = EGroup48 + 0xE0, |
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177 CARKIT_5W_DEBUG, |
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178 TEST_CTRL_CLR = EGroup48 + 0xEB, |
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179 TEST_CARKIT_SET, |
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180 TEST_CARKIT_CLR, |
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181 TEST_POWER_SET, |
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182 TEST_POWER_CLR, |
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183 TEST_ULPI, |
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184 TXVR_EN_TEST_SET, |
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185 TXVR_EN_TEST_CLR, |
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186 VBUS_EN_TEST, |
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187 ID_EN_TEST, |
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188 PSM_EN_TEST_SET, |
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189 PSM_EN_TEST_CLR, |
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190 PHY_TRIM_CTRL = EGroup48 + 0xFC, |
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191 PHY_PWR_CTRL, |
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192 PHY_CLK_CTRL, |
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193 PHY_CLK_CTRL_STS // 0x000000ff |
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194 }; |
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195 |
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196 |
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197 enum TGroup49Registers |
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198 { |
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199 CODEC_MODE = EGroup49 + 1, |
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200 OPTION , |
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201 MICBIAS_CTL = EGroup49 + 0x04, |
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202 ANAMICL, |
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203 ANAMICR, |
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204 AVADC_CTL, |
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205 ADCMICSEL, |
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206 DIGMIXING, |
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207 ATXL1PGA, |
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208 ATXR1PGA, |
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209 AVTXL2PGA, |
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210 AVTXR2PGA, |
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211 AUDIO_IF, |
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212 VOICE_IF, |
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213 ARXR1PGA, |
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214 ARXL1PGA, |
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215 ARXR2PGA, |
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216 ARXL2PGA, |
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217 VRXPGA, |
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218 VSTPGA, |
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219 VRX2ARXPGA, |
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220 AVDAC_CTL, |
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221 ARX2VTXPGA, |
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222 ARXL1_APGA_CTL, |
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223 ARXR1_APGA_CTL, |
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224 ARXL2_APGA_CTL, |
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225 ARXR2_APGA_CTL, |
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226 ATX2ARXPGA, |
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227 BT_IF, |
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228 BTPGA, |
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229 BTSTPGA, |
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230 EAR_CTL, |
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231 HS_SEL, |
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232 HS_GAIN_SET, |
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233 HS_POPN_SET, |
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234 PREDL_CTL, |
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235 PREDR_CTL, |
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236 PRECKL_CTL, |
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237 PRECKR_CTL, |
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238 HFL_CTL, |
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239 HFR_CTL, |
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240 ALC_CTL, |
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241 ALC_SET1, |
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242 ALC_SET2, |
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243 BOOST_CTL, |
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244 SOFTVOL_CTL, |
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245 DTMF_FREQSEL, |
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246 DTMF_TONEXT1H, |
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247 DTMF_TONEXT1L, |
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248 DTMF_TONEXT2H, |
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249 DTMF_TONEXT2L, |
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250 DTMF_TONOFF, |
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251 DTMF_WANONOFF,// 8 0x0000 0036 |
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252 |
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253 I2S_RX_SCRAMBLE_H, |
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254 I2S_RX_SCRAMBLE_M, |
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255 I2S_RX_SCRAMBLE_L, |
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256 APLL_CTL, |
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257 DTMF_CTL, |
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258 DTMF_PGA_CTL2, |
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259 DTMF_PGA_CTL1, |
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260 MISC_SET_1, |
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261 PCMBTMUX, |
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262 RX_PATH_SEL, |
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263 VDL_APGA_CTL, |
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264 VIBRA_CTL, |
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265 VIBRA_SET, |
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266 ANAMIC_GAIN, |
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267 MISC_SET_2,// RW 8 0x0000 0049 |
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268 |
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269 AUDIO_TEST_CTL = EGroup49 + 0x0000004C, |
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270 INT_TEST_CTL, |
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271 DAC_ADC_TEST_CTL, |
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272 RXTX_TRIM_IB, |
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273 CLD_CONTROL, |
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274 CLD_MODE_TIMING, |
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275 CLD_TRIM_RAMP, |
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276 CLD_TESTV_CTL, |
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277 APLL_TEST_CTL, |
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278 APLL_TEST_DIV, |
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279 APLL_TEST_CTL2, |
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280 APLL_TEST_CUR, |
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281 DIGMIC_BIAS1_CTL, |
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282 DIGMIC_BIAS2_CTL, |
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283 RX_OFFSET_VOICE, |
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284 RX_OFFSET_AL1, |
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285 RX_OFFSET_AR1, |
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286 RX_OFFSET_AL2, |
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287 RX_OFFSET_AR2, |
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288 OFFSET1, |
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289 OFFSET2, |
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290 |
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291 |
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292 GPIODATAIN1 = EGroup49 + 0x00000098, |
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293 GPIODATAIN2, |
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294 GPIODATAIN3, |
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295 GPIODATADIR1, |
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296 GPIODATADIR2, |
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297 GPIODATADIR3, |
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298 GPIODATAOUT1, |
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299 GPIODATAOUT2, |
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300 GPIODATAOUT3, |
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301 CLEARGPIODATAOUT1, |
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302 CLEARGPIODATAOUT2, |
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303 CLEARGPIODATAOUT3, |
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304 SETGPIODATAOUT1, |
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305 SETGPIODATAOUT2, |
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306 SETGPIODATAOUT3, |
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307 GPIO_DEBEN1, |
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308 GPIO_DEBEN3, |
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309 GPIO_CTRL , |
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310 GPIOPUPDCTR1, |
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311 GPIOPUPDCTR2, |
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312 GPIOPUPDCTR3, |
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313 GPIOPUPDCTR4, |
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314 GPIOPUPDCTR5, |
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315 GPIO_TEST, |
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316 GPIO_ISR1A = EGroup49 + 0xb1, |
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317 GPIO_ISR2A, |
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318 GPIO_ISR3A, |
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319 GPIO_IMR1A, // |
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320 GPIO_IMR2A, |
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321 GPIO_IMR3A, |
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322 GPIO_ISR1B, |
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323 GPIO_ISR2B, |
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324 GPIO_ISR3B, |
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325 GPIO_IMR1B, |
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326 GPIO_IMR2B, |
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327 GPIO_IMR3B, |
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328 GPIO_SIR1, |
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329 GPIO_SIR2, |
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330 GPIO_SIR3, |
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331 GPIO_EDR1, |
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332 GPIO_EDR2, |
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333 GPIO_EDR3, |
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334 GPIO_EDR4, |
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335 GPIO_EDR5, |
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336 GPIO_SIH_CTRL, |
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337 |
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338 PIH_ISR_P1 = EGroup49 + 0x00000081, |
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339 PIH_ISR_P2, |
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340 PIH_SIR , |
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341 IDCODE_7_0 = EGroup49 + 0x00000085, |
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342 IDCODE_15_8, |
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343 IDCODE_23_16, |
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344 IDCODE_31_24, |
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345 DIEID_7_0, |
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346 DIEID_15_8, |
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347 DIEID_23_16, |
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348 DIEID_31_24, |
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349 DIEID_39_32, |
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350 DIEID_47_40, |
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351 DIEID_55_48, |
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352 DIEID_63_56, |
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353 GPBR1, |
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354 PMBR1, |
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355 PMBR2, |
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356 GPPUPDCTR1, |
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357 GPPUPDCTR2, |
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358 GPPUPDCTR3, |
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359 UNLOCK_TEST_REG, |
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360 }; |
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361 |
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362 |
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363 |
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364 /* |
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365 Note: Access to the following registers is protected: |
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366 · IDCODE_7_0 |
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367 · IDCODE_15_8 |
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368 · IDCODE_23_16 |
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369 · IDCODE_31_24 |
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370 · DIEID_7_0 |
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371 · DIEID_15_8 |
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372 · DIEID_23_16 |
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373 · DIEID_31_24 |
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374 · DIEID_39_32 |
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375 · DIEID_47_40 |
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376 · DIEID_55_48 |
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377 · DIEID_63_56 |
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378 To read these registers, the UNLOCK_TEST_REG register must first be written with 0x49. |
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379 Table 2-29. GPPUPDCTR1 |
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380 Address Offset 0x0F |
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381 Physical Address 0x0000 0094 Instance INT_SCINTBR |
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382 */ |
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383 |
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384 enum TGroup4aRegisters |
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385 { |
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386 CTRL1 = EGroup4a + 0, |
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387 CTRL2, |
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388 RTSELECT_LSB, |
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389 RTSELECT_MSB, |
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390 RTAVERAGE_LSB, |
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391 RTAVERAGE_MSB, |
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392 SW1SELECT_LSB, |
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393 SW1SELECT_MSB, |
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394 SW1AVERAGE_LSB, |
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395 SW1AVERAGE_MSB, |
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396 SW2SELECT_LSB, |
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397 SW2SELECT_MSB, |
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398 SW2AVERAGE_LSB, |
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399 SW2AVERAGE_MSB, |
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400 BCI_USBAVERAGE, |
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401 ACQUISITION, |
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402 USBREF_LSB, |
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403 USBREF_MSB, |
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404 CTRL_SW1, |
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405 CTRL_SW2, |
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406 MADC_TEST, |
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407 GP_MADC_TEST1, |
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408 GP_MADC_TEST2, |
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409 RTCH0_LSB, |
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410 RTCH0_MSB, |
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411 RTCH1_LSB, |
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412 RTCH1_MSB, |
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413 RTCH2_LSB, |
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414 RTCH2_MSB, |
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415 RTCH3_LSB, |
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416 RTCH3_MSB, |
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417 RTCH4_LSB, |
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418 RTCH4_MSB, |
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419 RTCH5_LSB, |
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420 RTCH5_MSB, |
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421 RTCH6_LSB, |
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422 RTCH6_MSB, |
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423 RTCH7_LSB, |
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424 RTCH7_MSB, |
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425 RTCH8_LSB, |
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426 RTCH8_MSB, |
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427 RTCH9_LSB, |
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428 RTCH9_MSB, |
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429 RTCH10_LSB, |
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430 RTCH10_MSB, |
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431 RTCH11_LSB, |
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432 RTCH11_MSB, |
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433 RTCH12_LSB, |
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434 RTCH12_MSB, |
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435 RTCH13_LSB, |
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436 RTCH13_MSB, |
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437 RTCH14_LSB, |
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438 RTCH14_MSB, |
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439 RTCH15_LSB, |
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440 RTCH15_MSB, |
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441 GPCH0_LSB, |
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442 GPCH0_MSB, |
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443 GPCH1_LSB, |
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444 GPCH1_MSB, |
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445 GPCH2_LSB, |
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446 GPCH2_MSB, |
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447 GPCH3_LSB, |
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448 GPCH3_MSB, |
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449 GPCH4_LSB, |
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450 GPCH4_MSB, |
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451 GPCH5_LSB, |
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452 GPCH5_MSB, |
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453 GPCH6_LSB, |
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454 GPCH6_MSB, |
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455 GPCH7_LSB, |
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456 GPCH7_MSB, |
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457 GPCH8_LSB, |
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458 GPCH8_MSB, |
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459 GPCH9_LSB, |
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460 GPCH9_MSB, |
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461 GPCH10_LSB, |
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462 GPCH10_MSB, |
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463 GPCH11_LSB, |
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464 GPCH11_MSB, |
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465 GPCH12_LSB, |
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466 GPCH12_MSB, |
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467 GPCH13_LSB, |
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468 GPCH13_MSB, |
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469 GPCH14_LSB, |
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470 GPCH14_MSB, |
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471 GPCH15_LSB, |
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472 GPCH15_MSB, |
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473 BCICH0_LSB, |
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474 BCICH0_MSB, |
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475 BCICH1_LSB, |
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476 BCICH1_MSB, |
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477 BCICH2_LSB, |
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478 BCICH2_MSB, |
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479 BCICH3_LSB, |
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480 BCICH3_MSB, |
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481 BCICH4_LSB, |
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482 BCICH4_MSB, |
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483 MADC_ISR1, |
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484 MADC_IMR1, |
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485 MADC_ISR2, |
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486 MADC_IMR2, |
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487 MADC_SIR, |
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488 MADC_EDR, |
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489 MADC_SIH_CTRL, |
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490 BCIMDEN, |
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491 BCIMDKEY, |
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492 BCIMSTATEC, |
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493 BCIMSTATEP, |
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494 BCIVBAT1, |
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495 BCIVBAT2, |
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496 BCITBAT1, |
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497 BCITBAT2, |
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498 BCIICHG1, |
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499 BCIICHG2, |
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500 BCIVAC1, |
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501 BCIVAC2, |
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502 BCIVBUS1, |
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503 BCIVBUS2, |
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504 BCIMFSTS2, |
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505 BCIMFSTS3, |
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506 BCIMFSTS4, |
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507 BCIMFKEY, |
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508 BCIMFEN1, |
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509 BCIMFEN2, |
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510 BCIMFEN3, |
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511 BCIMFEN4, |
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512 BCIMFTH1, |
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513 BCIMFTH2, |
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514 BCIMFTH3, |
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515 BCIMFTH4, |
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516 BCIMFTH5, |
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517 BCIMFTH6, |
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518 BCIMFTH7, |
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519 BCIMFTH8, |
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520 BCIMFTH9, |
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521 BCITIMER1, |
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522 BCITIMER2, |
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523 BCIWDKEY, |
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524 BCIWD, |
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525 BCICTL1, |
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526 BCICTL2, |
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527 BCIVREF1, |
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528 BCIVREF2, |
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529 BCIIREF1, |
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530 BCIIREF2, |
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531 BCIPWM2, |
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532 BCIPWM1, |
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533 BCITRIM1, |
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534 BCITRIM2, |
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535 BCITRIM3, |
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536 BCITRIM4, |
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537 BCIVREFCOMB1, |
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538 BCIVREFCOMB2, |
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539 BCIIREFCOMB1, |
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540 BCIIREFCOMB2, |
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541 |
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542 BCIISR1A = EGroup4a + 0x000000B9, |
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543 BCIISR2A, |
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544 BCIIMR1A, |
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545 BCIIMR2A, |
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546 BCIISR1B, |
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547 BCIISR2B, |
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548 BCIIMR1B, |
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549 BCIIMR2B, //0x000000c0 |
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550 |
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551 BCIEDR1 = EGroup4a + 0x000000c3, |
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552 BCIEDR2, |
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553 BCIEDR3, |
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554 BCISIHCTRL, // c6 |
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555 |
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556 KEYP_CTRL_REG = EGroup4a + 0x000000D2, |
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557 KEY_DEB_REG, |
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558 LONG_KEY_REG1, |
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559 LK_PTV_REG, |
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560 TIME_OUT_REG1, |
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561 TIME_OUT_REG2, |
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562 KBC_REG, |
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563 KBR_REG, |
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564 KEYP_SMS, |
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565 FULL_CODE_7_0, |
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566 FULL_CODE_15_8, |
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567 FULL_CODE_23_16, |
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568 FULL_CODE_31_24, |
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569 FULL_CODE_39_32, |
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570 FULL_CODE_47_40, |
|
571 FULL_CODE_55_48, |
|
572 FULL_CODE_63_56, |
|
573 KEYP_ISR1, |
|
574 KEYP_IMR1, |
|
575 KEYP_ISR2, |
|
576 KEYP_IMR2, |
|
577 KEYP_SIR, |
|
578 KEYP_EDR, |
|
579 KEYP_SIH_CTRL, |
|
580 |
|
581 LEDEN = EGroup4a + 0x000000EE, |
|
582 PWMAON, |
|
583 PWMAOFF, |
|
584 PWMBON, |
|
585 PWMBOFF, |
|
586 |
|
587 PWM1ON= EGroup4a + 0x000000FB, |
|
588 PWM1OFF, |
|
589 PWM0ON = EGroup4a + 0x000000F8, |
|
590 PWM0OFF, |
|
591 }; |
|
592 |
|
593 enum TGroup4bRegisters |
|
594 { |
|
595 SECURED_REG_A = EGroup4b + 0, |
|
596 SECURED_REG_B, |
|
597 SECURED_REG_C, |
|
598 SECURED_REG_D, |
|
599 SECURED_REG_E, |
|
600 SECURED_REG_F, |
|
601 SECURED_REG_G, |
|
602 SECURED_REG_H, |
|
603 SECURED_REG_I, |
|
604 SECURED_REG_J, |
|
605 SECURED_REG_K, |
|
606 SECURED_REG_L, |
|
607 SECURED_REG_M, |
|
608 SECURED_REG_N, |
|
609 SECURED_REG_O, |
|
610 SECURED_REG_P, |
|
611 SECURED_REG_Q, |
|
612 SECURED_REG_R, |
|
613 SECURED_REG_S, |
|
614 SECURED_REG_U, |
|
615 BACKUP_REG_A, |
|
616 BACKUP_REG_B, |
|
617 BACKUP_REG_C, |
|
618 BACKUP_REG_D, |
|
619 BACKUP_REG_E, |
|
620 BACKUP_REG_F, |
|
621 BACKUP_REG_G, |
|
622 BACKUP_REG_H, |
|
623 PWR_ISR1 = EGroup4b + 0x2e, |
|
624 PWR_IMR1, |
|
625 PWR_ISR2, |
|
626 PWR_IMR2, |
|
627 PWR_SIR, |
|
628 PWR_EDR1, |
|
629 PWR_EDR2, |
|
630 PWR_SIH_CTRL, |
|
631 CFG_P1_TRANSITION, |
|
632 CFG_P2_TRANSITION, |
|
633 CFG_P3_TRANSITION, |
|
634 CFG_P123_TRANSITION, |
|
635 STS_BOOT, |
|
636 CFG_BOOT, |
|
637 SHUNDAN, |
|
638 BOOT_BCI, |
|
639 CFG_PWRANA1, |
|
640 CFG_PWRANA2, |
|
641 BGAP_TRIM, |
|
642 BACKUP_MISC_STS, |
|
643 BACKUP_MISC_CFG, |
|
644 BACKUP_MISC_TST, |
|
645 PROTECT_KEY, |
|
646 STS_HW_CONDITIONS, |
|
647 P1_SW_EVENTS, |
|
648 P2_SW_EVENTS, |
|
649 P3_SW_EVENTS, |
|
650 STS_P123_STATE, |
|
651 PB_CFG, |
|
652 PB_WORD_MSB, |
|
653 PB_WORD_LSB, |
|
654 RESERVED_A, |
|
655 RESERVED_B, |
|
656 RESERVED_C, |
|
657 RESERVED_D, |
|
658 RESERVED_E, |
|
659 SEQ_ADD_W2P, |
|
660 SEQ_ADD_P2A, |
|
661 SEQ_ADD_A2W, |
|
662 SEQ_ADD_A2S, |
|
663 SEQ_ADD_S2A12, |
|
664 SEQ_ADD_S2A3, |
|
665 SEQ_ADD_WARM, |
|
666 MEMORY_ADDRESS, |
|
667 MEMORY_DATA, |
|
668 SC_CONFIG, |
|
669 SC_DETECT1, |
|
670 SC_DETECT2, |
|
671 WATCHDOG_CFG, |
|
672 IT_CHECK_CFG, |
|
673 VIBRATOR_CFG, |
|
674 DCDC_GLOBAL_CFG, |
|
675 VDD1_TRIM1, |
|
676 VDD1_TRIM2, |
|
677 VDD2_TRIM1, |
|
678 VDD2_TRIM2, |
|
679 VIO_TRIM1, |
|
680 VIO_TRIM2, |
|
681 MISC_CFG, |
|
682 LS_TST_A, |
|
683 LS_TST_B, |
|
684 LS_TST_C, |
|
685 LS_TST_D, |
|
686 BB_CFG, |
|
687 MISC_TST, |
|
688 TRIM1, |
|
689 TRIM2, |
|
690 DCDC_TIMEOUT, |
|
691 VAUX1_DEV_GRP, |
|
692 VAUX1_TYPE, |
|
693 VAUX1_REMAP, |
|
694 VAUX1_DEDICATED, |
|
695 VAUX2_DEV_GRP, |
|
696 VAUX2_TYPE, |
|
697 VAUX2_REMAP, |
|
698 VAUX2_DEDICATED, |
|
699 VAUX3_DEV_GRP, |
|
700 VAUX3_TYPE, |
|
701 VAUX3_REMAP, |
|
702 VAUX3_DEDICATED, |
|
703 VAUX4_DEV_GRP, |
|
704 VAUX4_TYPE, |
|
705 VAUX4_REMAP, |
|
706 VAUX4_DEDICATED, |
|
707 VMMC1_DEV_GRP, |
|
708 VMMC1_TYPE, |
|
709 VMMC1_REMAP, |
|
710 VMMC1_DEDICATED, |
|
711 VMMC2_DEV_GRP, |
|
712 VMMC2_TYPE, |
|
713 VMMC2_REMAP, |
|
714 VMMC2_DEDICATED, |
|
715 VPLL1_DEV_GRP, |
|
716 VPLL1_TYPE, |
|
717 VPLL1_REMAP, |
|
718 VPLL1_DEDICATED, |
|
719 VPLL2_DEV_GRP, |
|
720 VPLL2_TYPE, |
|
721 VPLL2_REMAP, |
|
722 VPLL2_DEDICATED, |
|
723 VSIM_DEV_GRP, |
|
724 VSIM_TYPE, |
|
725 VSIM_REMAP, |
|
726 VSIM_DEDICATED, |
|
727 VDAC_DEV_GRP, |
|
728 VDAC_TYPE, |
|
729 VDAC_REMAP, |
|
730 VDAC_DEDICATED, |
|
731 VINTANA1_DEV_GRP, |
|
732 VINTANA1_TYPE, |
|
733 VINTANA1_REMAP, |
|
734 VINTANA1_DEDICATED, |
|
735 VINTANA2_DEV_GRP, |
|
736 VINTANA2_TYPE, |
|
737 VINTANA2_REMAP, |
|
738 VINTANA2_DEDICATED, |
|
739 VINTDIG_DEV_GRP, |
|
740 VINTDIG_TYPE, |
|
741 VINTDIG_REMAP, |
|
742 VINTDIG_DEDICATED, |
|
743 VIO_DEV_GRP, |
|
744 VIO_TYPE, |
|
745 VIO_REMAP, |
|
746 VIO_CFG, |
|
747 VIO_MISC_CFG, |
|
748 VIO_TEST1, |
|
749 VIO_TEST2, |
|
750 VIO_OSC, |
|
751 VIO_RESERVED, |
|
752 VIO_VSEL, |
|
753 VDD1_DEV_GRP, |
|
754 VDD1_TYPE, |
|
755 VDD1_REMAP, |
|
756 VDD1_CFG, |
|
757 VDD1_MISC_CFG, |
|
758 VDD1_TEST1, |
|
759 VDD1_TEST2, |
|
760 VDD1_OSC, |
|
761 VDD1_RESERVED, |
|
762 VDD1_VSEL, |
|
763 VDD1_VMODE_CFG, |
|
764 VDD1_VFLOOR, |
|
765 VDD1_VROOF, |
|
766 VDD1_STEP, |
|
767 VDD2_DEV_GRP, |
|
768 VDD2_TYPE, |
|
769 VDD2_REMAP, |
|
770 VDD2_CFG, |
|
771 VDD2_MISC_CFG, |
|
772 VDD2_TEST1, |
|
773 VDD2_TEST2, |
|
774 VDD2_OSC, |
|
775 VDD2_RESERVED, |
|
776 VDD2_VSEL, |
|
777 VDD2_VMODE_CFG, |
|
778 VDD2_VFLOOR, |
|
779 VDD2_VROOF, |
|
780 VDD2_STEP, |
|
781 VUSB1V5_DEV_GRP, |
|
782 VUSB1V5_TYPE, |
|
783 VUSB1V5_REMAP, |
|
784 VUSB1V8_DEV_GRP, |
|
785 VUSB1V8_TYPE, |
|
786 VUSB1V8_REMAP, |
|
787 VUSB3V1_DEV_GRP, |
|
788 VUSB3V1_TYPE, |
|
789 VUSB3V1_REMAP, |
|
790 VUSBCP_DEV_GRP, |
|
791 VUSBCP_TYPE, |
|
792 VUSBCP_REMAP, |
|
793 VUSB_DEDICATED1, |
|
794 VUSB_DEDICATED2, |
|
795 REGEN_DEV_GRP, |
|
796 REGEN_TYPE, |
|
797 REGEN_REMAP, |
|
798 NRESPWRON_DEV_GRP, |
|
799 NRESPWRON_TYPE, |
|
800 NRESPWRON_REMAP, |
|
801 CLKEN_DEV_GRP, |
|
802 CLKEN_TYPE, |
|
803 CLKEN_REMAP, |
|
804 SYSEN_DEV_GRP, |
|
805 SYSEN_TYPE, |
|
806 SYSEN_REMAP, |
|
807 HFCLKOUT_DEV_GRP, |
|
808 HFCLKOUT_TYPE, |
|
809 HFCLKOUT_REMAP, |
|
810 E32KCLKOUT_DEV_GRP, |
|
811 E32KCLKOUT_TYPE, |
|
812 E32KCLKOUT_REMAP, |
|
813 TRITON_RESET_DEV_GRP, |
|
814 TRITON_RESET_TYPE, |
|
815 TRITON_RESET_REMAP, |
|
816 MAINREF_DEV_GRP, |
|
817 MAINREF_TYPE, |
|
818 MAINREF_REMAP, |
|
819 SECONDS_REG, |
|
820 MINUTES_REG, |
|
821 HOURS_REG, |
|
822 DAYS_REG, |
|
823 MONTHS_REG, |
|
824 YEARS_REG, |
|
825 WEEKS_REG, |
|
826 ALARM_SECONDS_REG, |
|
827 ALARM_MINUTES_REG, |
|
828 ALARM_HOURS_REG, |
|
829 ALARM_DAYS_REG, |
|
830 ALARM_MONTHS_REG, |
|
831 ALARM_YEARS_REG, |
|
832 RTC_CTRL_REG, |
|
833 RTC_STATUS_REG, |
|
834 RTC_INTERRUPTS_REG, |
|
835 RTC_COMP_LSB_REG, |
|
836 RTC_COMP_MSB_REG, //2d |
|
837 }; |
|
838 } // namespace Register |
|
839 |
|
840 namespace DCDC_GLOBAL_CFG |
|
841 { |
|
842 const TUint16 Addr = Register::DCDC_GLOBAL_CFG; |
|
843 |
|
844 const TUint8 CARD_DETECT_2_LEVEL = KBit7; |
|
845 const TUint8 CARD_DETECT_1_LEVEL = KBit6; |
|
846 const TUint8 REGEN_PU_DISABLE = KBit5; |
|
847 const TUint8 SYSEN_PU_DISABLE = KBit4; |
|
848 const TUint8 SMARTREFLEX_ENABLE = KBit3; |
|
849 const TUint8 CARD_DETECT_CFG = KBit2; |
|
850 const TUint8 CLK_32K_DEGATE = KBit1; |
|
851 const TUint8 CLK_HF_DEGATE = KBit0; |
|
852 }; |
|
853 |
|
854 |
|
855 namespace _VMODE_CFG_ |
|
856 { |
|
857 const TUint8 STS_BUSY = KBit5; |
|
858 const TUint8 STS_ROOF = KBit4; |
|
859 const TUint8 STS_FLOOR = KBit3; |
|
860 const TUint8 DCDC_SLP = KBit2; |
|
861 const TUint8 READ_REG = KBit1; |
|
862 const TUint8 ENABLE_VMODE = KBit0; |
|
863 } |
|
864 |
|
865 namespace VDD1_VMODE_CFG |
|
866 { |
|
867 const TUint16 Addr = Register::VDD1_VMODE_CFG; |
|
868 using namespace _VMODE_CFG_; |
|
869 }; |
|
870 |
|
871 namespace VDD2_VMODE_CFG |
|
872 { |
|
873 const TUint16 Addr = Register::VDD2_VMODE_CFG; |
|
874 using namespace _VMODE_CFG_; |
|
875 }; |
|
876 |
|
877 namespace _VDDx_VSEL_ |
|
878 { |
|
879 namespace Mask |
|
880 { |
|
881 const TUint8 VSEL = 0x7F; |
|
882 } |
|
883 |
|
884 namespace Shift |
|
885 { |
|
886 const TUint VSEL = 0; |
|
887 } |
|
888 } |
|
889 |
|
890 namespace VDD1_VSEL |
|
891 { |
|
892 const TUint16 Addr = Register::VDD1_VSEL; |
|
893 using namespace _VDDx_VSEL_; |
|
894 }; |
|
895 |
|
896 namespace VDD2_VSEL |
|
897 { |
|
898 const TUint16 Addr = Register::VDD2_VSEL; |
|
899 using namespace _VDDx_VSEL_; |
|
900 }; |
|
901 |
|
902 namespace _PWR_I_1_ |
|
903 { |
|
904 const TUint8 PWR_SC_DETECT = KBit7; |
|
905 const TUint8 PWR_MBCHG = KBit6; |
|
906 const TUint8 PWR_PWROK_TIMEOUT = KBit5; |
|
907 const TUint8 PWR_HOT_DIE = KBit4; |
|
908 const TUint8 PWR_RTC_IT = KBit3; |
|
909 const TUint8 PWR_USB_PRES = KBit2; |
|
910 const TUint8 PWR_CHG_PRES = KBit1; |
|
911 const TUint8 PWR_CHG_PWRONS = KBit0; |
|
912 } |
|
913 |
|
914 namespace PWR_IMR1 |
|
915 { |
|
916 const TUint16 Addr = Register::PWR_IMR1; |
|
917 using namespace _PWR_I_1_; |
|
918 } |
|
919 |
|
920 namespace PWR_ISR1 |
|
921 { |
|
922 const TUint16 Addr = Register::PWR_ISR1; |
|
923 using namespace _PWR_I_1_; |
|
924 } |
|
925 |
|
926 namespace _MADC_I_1_ |
|
927 { |
|
928 const TUint8 MADC_USB_ISR1 = KBit3; |
|
929 const TUint8 MADC_SW2_ISR1 = KBit2; |
|
930 const TUint8 MADC_SW1_ISR1 = KBit1; |
|
931 const TUint8 MADC_RT_ISR1 = KBit0; |
|
932 } |
|
933 |
|
934 namespace MADC_IMR1 |
|
935 { |
|
936 const TUint16 Addr = Register::MADC_IMR1; |
|
937 using namespace _MADC_I_1_; |
|
938 } |
|
939 |
|
940 namespace MADC_ISR1 |
|
941 { |
|
942 const TUint16 Addr = Register::MADC_ISR1; |
|
943 using namespace _MADC_I_1_; |
|
944 } |
|
945 |
|
946 namespace _GPIO_I_1A_ |
|
947 { |
|
948 const TUint8 GPIO7ISR1 = KBit7; |
|
949 const TUint8 GPIO6ISR1 = KBit6; |
|
950 const TUint8 GPIO5ISR1 = KBit5; |
|
951 const TUint8 GPIO4ISR1 = KBit4; |
|
952 const TUint8 GPIO3ISR1 = KBit3; |
|
953 const TUint8 GPIO2ISR1 = KBit2; |
|
954 const TUint8 GPIO1ISR1 = KBit1; |
|
955 const TUint8 GPIO0ISR1 = KBit0; |
|
956 } |
|
957 |
|
958 namespace _GPIO_I_2A_ |
|
959 { |
|
960 const TUint8 GPIO15ISR2 = KBit7; |
|
961 const TUint8 GPIO14ISR2 = KBit6; |
|
962 const TUint8 GPIO13ISR2 = KBit5; |
|
963 const TUint8 GPIO12ISR2 = KBit4; |
|
964 const TUint8 GPIO11ISR2 = KBit3; |
|
965 const TUint8 GPIO10ISR2 = KBit2; |
|
966 const TUint8 GPIO9ISR2 = KBit1; |
|
967 const TUint8 GPIO8ISR2 = KBit0; |
|
968 } |
|
969 |
|
970 namespace _GPIO_I_3A_ |
|
971 { |
|
972 const TUint8 GPIO17ISR3 = KBit1; |
|
973 const TUint8 GPIO16ISR3 = KBit0; |
|
974 } |
|
975 |
|
976 namespace GPIO_IMR1A |
|
977 { |
|
978 const TUint16 Addr = Register::GPIO_IMR1A; |
|
979 using namespace _GPIO_I_1A_; |
|
980 } |
|
981 |
|
982 namespace GPIO_ISR1A |
|
983 { |
|
984 const TUint16 Addr = Register::GPIO_ISR1A; |
|
985 using namespace _GPIO_I_1A_; |
|
986 } |
|
987 |
|
988 namespace GPIO_IMR2A |
|
989 { |
|
990 const TUint16 Addr = Register::GPIO_IMR2A; |
|
991 using namespace _GPIO_I_2A_; |
|
992 } |
|
993 |
|
994 namespace GPIO_ISR2A |
|
995 { |
|
996 const TUint16 Addr = Register::GPIO_ISR2A; |
|
997 using namespace _GPIO_I_2A_; |
|
998 } |
|
999 |
|
1000 namespace GPIO_IMR3A |
|
1001 { |
|
1002 const TUint16 Addr = Register::GPIO_IMR3A; |
|
1003 using namespace _GPIO_I_3A_; |
|
1004 } |
|
1005 |
|
1006 namespace GPIO_ISR3A |
|
1007 { |
|
1008 const TUint16 Addr = Register::GPIO_ISR3A; |
|
1009 using namespace _GPIO_I_3A_; |
|
1010 } |
|
1011 |
|
1012 namespace _BCI_I_1_ |
|
1013 { |
|
1014 const TUint8 BCI_BATSTS_ISR1 = KBit7; |
|
1015 const TUint8 BCI_TBATOR1_ISR1 = KBit6; |
|
1016 const TUint8 BCI_TBATOR2_ISR1 = KBit5; |
|
1017 const TUint8 BCI_ICHGEOC_ISR1 = KBit4; |
|
1018 const TUint8 BCI_ICHGLOW_ISR1ASTO = KBit3; |
|
1019 const TUint8 BCI_IICHGHIGH_ISR1 = KBit2; |
|
1020 const TUint8 BCI_TMOVF_ISR1 = KBit1; |
|
1021 const TUint8 BCI_WOVF_ISR1 = KBit0; |
|
1022 } |
|
1023 |
|
1024 namespace _BCI_I_2_ |
|
1025 { |
|
1026 const TUint8 BCI_ACCHGOV_ISR1 = KBit3; |
|
1027 const TUint8 BCI_VBUSOV_ISR1 = KBit2; |
|
1028 const TUint8 BCI_VBATOV_ISR1 = KBit1; |
|
1029 const TUint8 BCI_VBATLVL_ISR1 = KBit0; |
|
1030 } |
|
1031 |
|
1032 namespace BCIIMR1A |
|
1033 { |
|
1034 const TUint16 Addr = Register::BCIIMR1A; |
|
1035 using namespace _BCI_I_1_; |
|
1036 } |
|
1037 |
|
1038 namespace BCIISR1A |
|
1039 { |
|
1040 const TUint16 Addr = Register::BCIISR1A; |
|
1041 using namespace _BCI_I_1_; |
|
1042 } |
|
1043 |
|
1044 namespace BCIIMR2A |
|
1045 { |
|
1046 const TUint16 Addr = Register::BCIIMR2A; |
|
1047 using namespace _BCI_I_2_; |
|
1048 } |
|
1049 |
|
1050 namespace BCIISR2A |
|
1051 { |
|
1052 const TUint16 Addr = Register::BCIISR2A; |
|
1053 using namespace _BCI_I_2_; |
|
1054 } |
|
1055 |
|
1056 namespace _KEYP_I_ |
|
1057 { |
|
1058 const TUint8 KEYP_ITMISR1 = KBit3; |
|
1059 const TUint8 KEYP_ITTOISR1 = KBit2; |
|
1060 const TUint8 KEYP_ITLKISR1 = KBit1; |
|
1061 const TUint8 KEYP_ITKPISR1 = KBit0; |
|
1062 } |
|
1063 |
|
1064 namespace KEYP_IMR1 |
|
1065 { |
|
1066 const TUint16 Addr = Register::KEYP_IMR1; |
|
1067 using namespace _KEYP_I_; |
|
1068 } |
|
1069 |
|
1070 namespace KEYP_ISR1 |
|
1071 { |
|
1072 const TUint16 Addr = Register::KEYP_ISR1; |
|
1073 using namespace _KEYP_I_; |
|
1074 } |
|
1075 |
|
1076 namespace _USB_INT_EN_ |
|
1077 { |
|
1078 const TUint8 USB_INTSTS_IDGND = KBit4; |
|
1079 const TUint8 USB_INTSTS_SESSEND = KBit3; |
|
1080 const TUint8 USB_INTSTS_SESSVALID = KBit2; |
|
1081 const TUint8 USB_INTSTS_VBUSVALID = KBit1; |
|
1082 const TUint8 USB_INTSTS_HOSTDISCONNECT = KBit0; |
|
1083 } |
|
1084 |
|
1085 namespace USB_INT_EN_RISE_SET |
|
1086 { |
|
1087 const TUint16 Addr = Register::USB_INT_EN_RISE_SET; |
|
1088 using namespace _USB_INT_EN_; |
|
1089 } |
|
1090 |
|
1091 namespace USB_INT_EN_RISE_CLR |
|
1092 { |
|
1093 const TUint16 Addr = Register::USB_INT_EN_RISE_CLR; |
|
1094 using namespace _USB_INT_EN_; |
|
1095 } |
|
1096 |
|
1097 namespace USB_INT_STS |
|
1098 { |
|
1099 const TUint16 Addr = Register::USB_INT_STS; |
|
1100 using namespace _USB_INT_EN_; |
|
1101 } |
|
1102 |
|
1103 namespace _OTHER_INT_ |
|
1104 { |
|
1105 const TUint8 OTHER_INT_VB_SESS_VLD = KBit7; |
|
1106 const TUint8 OTHER_INT_DM_HI = KBit6; |
|
1107 const TUint8 OTHER_INT_DP_HI = KBit5; |
|
1108 const TUint8 OTHER_INT_MANU = KBit1; |
|
1109 const TUint8 OTHER_INT_ABNORMAL_STRESS = KBit0; |
|
1110 } |
|
1111 |
|
1112 namespace OTHER_INT_EN_RISE_SET |
|
1113 { |
|
1114 const TUint16 Addr = Register::OTHER_INT_EN_RISE_SET; |
|
1115 using namespace _OTHER_INT_; |
|
1116 } |
|
1117 |
|
1118 namespace OTHER_INT_EN_RISE_CLR |
|
1119 { |
|
1120 const TUint16 Addr = Register::OTHER_INT_EN_RISE_CLR; |
|
1121 using namespace _OTHER_INT_; |
|
1122 } |
|
1123 |
|
1124 namespace OTHER_INT_STS |
|
1125 { |
|
1126 const TUint16 Addr = Register::OTHER_INT_STS; |
|
1127 using namespace _OTHER_INT_; |
|
1128 } |
|
1129 |
|
1130 namespace _CARKIT_INT_ |
|
1131 { |
|
1132 const TUint8 CARKIT_CARDP = KBit2; |
|
1133 const TUint8 CARKIT_CARINTDET = KBit1; |
|
1134 const TUint8 CARKIT_IDFLOAT = KBit0; |
|
1135 } |
|
1136 |
|
1137 namespace CARKIT_INT_EN_SET |
|
1138 { |
|
1139 const TUint16 Addr = Register::CARKIT_INT_EN_SET; |
|
1140 using namespace _CARKIT_INT_; |
|
1141 } |
|
1142 |
|
1143 namespace CARKIT_INT_EN_CLR |
|
1144 { |
|
1145 const TUint16 Addr = Register::CARKIT_INT_EN_CLR; |
|
1146 using namespace _CARKIT_INT_; |
|
1147 } |
|
1148 |
|
1149 namespace CARKIT_INT_STS |
|
1150 { |
|
1151 const TUint16 Addr = Register::CARKIT_INT_STS; |
|
1152 using namespace _CARKIT_INT_; |
|
1153 } |
|
1154 |
|
1155 namespace _ID_INT_ |
|
1156 { |
|
1157 const TUint8 ID_INTID_RES_FLOAT = KBit3; |
|
1158 const TUint8 ID_INTID_RES_440K = KBit2; |
|
1159 const TUint8 ID_INTID_RES_200K = KBit1; |
|
1160 const TUint8 ID_INTID_RES_102K = KBit0; |
|
1161 } |
|
1162 |
|
1163 namespace ID_INT_EN_RISE_SET |
|
1164 { |
|
1165 const TUint16 Addr = Register::ID_INT_EN_RISE_SET; |
|
1166 using namespace _ID_INT_; |
|
1167 } |
|
1168 |
|
1169 namespace ID_INT_EN_RISE_CLR |
|
1170 { |
|
1171 const TUint16 Addr = Register::ID_INT_EN_RISE_CLR; |
|
1172 using namespace _ID_INT_; |
|
1173 } |
|
1174 |
|
1175 namespace ID_INT_STS |
|
1176 { |
|
1177 const TUint16 Addr = Register::ID_INT_STS; |
|
1178 using namespace _ID_INT_; |
|
1179 } |
|
1180 |
|
1181 namespace _CARKIT_SM_1_INT_ |
|
1182 { |
|
1183 const TUint8 CARKIT_SM_1_PSM_ERROR = KBit6; |
|
1184 const TUint8 CARKIT_SM_1_PH_ACC = KBit5; |
|
1185 const TUint8 CARKIT_SM_1_CHARGER = KBit4; |
|
1186 const TUint8 CARKIT_SM_1_USB_HOST = KBit3; |
|
1187 const TUint8 CARKIT_SM_1_USB_OTG_B = KBit2; |
|
1188 const TUint8 CARKIT_SM_1_CARKIT = KBit1; |
|
1189 const TUint8 CARKIT_SM_1_DISCONNECTED = KBit0; |
|
1190 } |
|
1191 |
|
1192 namespace _CARKIT_SM_2_INT_ |
|
1193 { |
|
1194 const TUint8 CARKIT_SM_2_STOP_PLS_MISS = KBit7; |
|
1195 const TUint8 CARKIT_SM_2_STEREO_TO_MONO = KBit3; |
|
1196 const TUint8 CARKIT_SM_2_PHONE_UART = KBit1; |
|
1197 const TUint8 CARKIT_SM_2_PH_NO_ACK = KBit0; |
|
1198 } |
|
1199 |
|
1200 namespace CARKIT_SM_1_INT_EN_SET |
|
1201 { |
|
1202 const TUint16 Addr = Register::CARKIT_SM_1_INT_EN_SET; |
|
1203 using namespace _CARKIT_SM_1_INT_; |
|
1204 } |
|
1205 |
|
1206 namespace CARKIT_SM_1_INT_EN_CLR |
|
1207 { |
|
1208 const TUint16 Addr = Register::CARKIT_SM_1_INT_EN_CLR; |
|
1209 using namespace _CARKIT_SM_1_INT_; |
|
1210 } |
|
1211 |
|
1212 namespace CARKIT_SM_1_INT_STS |
|
1213 { |
|
1214 const TUint16 Addr = Register::CARKIT_SM_1_INT_STS; |
|
1215 using namespace _CARKIT_SM_1_INT_; |
|
1216 } |
|
1217 |
|
1218 namespace CARKIT_SM_2_INT_EN_SET |
|
1219 { |
|
1220 const TUint16 Addr = Register::CARKIT_SM_2_INT_EN_SET; |
|
1221 using namespace _CARKIT_SM_2_INT_; |
|
1222 } |
|
1223 |
|
1224 namespace CARKIT_SM_2_INT_EN_CLR |
|
1225 { |
|
1226 const TUint16 Addr = Register::CARKIT_SM_2_INT_EN_CLR; |
|
1227 using namespace _CARKIT_SM_2_INT_; |
|
1228 } |
|
1229 |
|
1230 namespace CARKIT_SM_2_INT_STS |
|
1231 { |
|
1232 const TUint16 Addr = Register::CARKIT_SM_2_INT_STS; |
|
1233 using namespace _CARKIT_SM_2_INT_; |
|
1234 } |
|
1235 |
|
1236 namespace _PIH_ |
|
1237 { |
|
1238 const TUint8 PIH_PWR_INT = KBit5; |
|
1239 const TUint8 PIH_USB_INT = KBit4; |
|
1240 const TUint8 PIH_MADC_INT = KBit3; |
|
1241 const TUint8 PIH_BCI_INT = KBit2; |
|
1242 const TUint8 PIH_KEYP_INT = KBit1; |
|
1243 const TUint8 PIH_GPIO_INT = KBit0; |
|
1244 } |
|
1245 |
|
1246 namespace PIH_ISR_P1 |
|
1247 { |
|
1248 const TUint Addr = Register::PIH_ISR_P1; |
|
1249 |
|
1250 const TUint8 PIH_ISR7 = KBit7; |
|
1251 const TUint8 PIH_ISR6 = KBit6; |
|
1252 const TUint8 PIH_ISR5 = KBit5; |
|
1253 const TUint8 PIH_ISR4 = KBit4; |
|
1254 const TUint8 PIH_ISR3 = KBit3; |
|
1255 const TUint8 PIH_ISR2 = KBit2; |
|
1256 const TUint8 PIH_ISR1 = KBit1; |
|
1257 const TUint8 PIH_ISR0 = KBit0; |
|
1258 } |
|
1259 |
|
1260 namespace _SIH_CTRL_ |
|
1261 { |
|
1262 const TUint8 SIH_EXCLEN = KBit0; |
|
1263 const TUint8 SIH_PENDDIS = KBit1; |
|
1264 const TUint8 SIH_COR = KBit2; |
|
1265 } |
|
1266 |
|
1267 namespace GPIO_SIH_CTRL |
|
1268 { |
|
1269 const TUint16 Addr = Register::GPIO_SIH_CTRL; |
|
1270 using namespace _SIH_CTRL_; |
|
1271 } |
|
1272 |
|
1273 namespace KEYP_SIH_CTRL |
|
1274 { |
|
1275 const TUint16 Addr = Register::KEYP_SIH_CTRL; |
|
1276 using namespace _SIH_CTRL_; |
|
1277 } |
|
1278 |
|
1279 namespace BCISIHCTRL |
|
1280 { |
|
1281 const TUint16 Addr = Register::BCISIHCTRL; |
|
1282 using namespace _SIH_CTRL_; |
|
1283 } |
|
1284 |
|
1285 namespace MADC_SIH_CTRL |
|
1286 { |
|
1287 const TUint16 Addr = Register::MADC_SIH_CTRL; |
|
1288 using namespace _SIH_CTRL_; |
|
1289 } |
|
1290 |
|
1291 namespace PWR_SIH_CTRL |
|
1292 { |
|
1293 const TUint16 Addr = Register::PWR_SIH_CTRL; |
|
1294 using namespace _SIH_CTRL_; |
|
1295 } |
|
1296 |
|
1297 namespace PROTECT_KEY |
|
1298 { |
|
1299 const TUint16 Addr = Register::PROTECT_KEY; |
|
1300 |
|
1301 const TUint8 KEY_TEST = KBit0; |
|
1302 const TUint8 KEY_CFG = KBit1; |
|
1303 } |
|
1304 |
|
1305 namespace RTC_CTRL_REG |
|
1306 { |
|
1307 const TUint16 Addr = Register::RTC_CTRL_REG; |
|
1308 |
|
1309 const TUint8 STOP_RTC = KBit0; |
|
1310 const TUint8 ROUND_30S = KBit1; |
|
1311 const TUint8 AUTO_COMP = KBit2; |
|
1312 const TUint8 MODE_12_24 = KBit3; |
|
1313 const TUint8 TEST_MODE = KBit4; |
|
1314 const TUint8 SET_32_COUNTER = KBit5; |
|
1315 const TUint8 GET_TIME = KBit6; |
|
1316 } |
|
1317 |
|
1318 } // namespace TPS65950 |
|
1319 |
|
1320 #endif // define TPS65950_REGISTERS_H |