/*

* Copyright (c) 2008-2010 Nokia Corporation and/or its subsidiary(-ies).

* All rights reserved.

* This component and the accompanying materials are made available

* under the terms of "Eclipse Public License v1.0"

* which accompanies this distribution, and is available

* at the URL "http://www.eclipse.org/legal/epl-v10.html".

*

* Initial Contributors:

* Nokia Corporation - initial contribution.

*

* Contributors:

*

* Description:  

* naviengine_assp\dmapsl.cpp

* DMA Platform Specific Layer (PSL) for Navi Engine.

*

*/

#include <kernel/kern_priv.h>

#include <assp.h>

#include <naviengine_priv.h>

#include <navienginedma.h>	

#include <dma.h>

// Debug support

static const char KDmaPanicCat[] = "DMA PSL";

static const TInt KDesCount = 1024;	// DMA descriptor count - sufficient to serve all channels at the time. 

/* Maps logical DMA channels into physical ones */

static const TDMAChannelLocator KDMAChannelLocator[EDmaChannelCount]=

    {

  // controller, 	 group,	subchannel   DCHS (exc. SEL) TransferShiftSize

	{EDMACtrl32  	,2     ,2			,KHvDMACHC_SDR,		1}, //EDMAChannelSD0,

	{EDMACtrl32  	,2     ,3			,KHvDMACHC_SDW,		1},	//EDMAChannelSD1,

	{EDMACtrl32  	,3     ,0			,KHvDMACHC_I2SR,	1},	//EDMAChannelI2S0RX,

	{EDMACtrl32  	,3     ,1			,KHvDMACHC_I2SW,	1},	//EDMAChannelI2S0TX,

	{EDMACtrl32  	,3     ,2			,KHvDMACHC_I2SR,	1},	//EDMAChannelI2S1RX,

	{EDMACtrl32  	,3     ,3			,KHvDMACHC_I2SW,	1},	//EDMAChannelI2S1TX,

	{EDMACtrl32  	,3     ,4			,KHvDMACHC_I2SR,	1},	//EDMAChannelI2S2RX,

	{EDMACtrl32  	,3     ,5			,KHvDMACHC_I2SW,	1},	//EDMAChannelI2S2TX,

	{EDMACtrl32  	,3     ,6			,KHvDMACHC_I2SR,	1},	//EDMAChannelI2S3RX,

	{EDMACtrl32  	,3     ,7			,KHvDMACHC_I2SW,	1},	//EDMAChannelI2S3TX,

	{EDMACtrl32  	,0     ,2			,KHvDMACHC_SW,		2},	//EDMAChannelUART0RX,

	{EDMACtrl32  	,0     ,3			,KHvDMACHC_SW,		2},	//EDMAChannelUART0TX,

	{EDMACtrl32  	,0     ,4			,KHvDMACHC_SW,		2},	//EDMAChannelUART1RX,

	{EDMACtrl32  	,0     ,5			,KHvDMACHC_SW,		2},	//EDMAChannelUART1TX,

	{EDMACtrl32  	,0     ,6			,KHvDMACHC_SW,		2},	//EDMAChannelUART2RX,

	{EDMACtrl32  	,0     ,7			,KHvDMACHC_SW,		2},	//EDMAChannelUART2TX,

	{EDMACtrl32  	,0     ,0			,KHvDMACHC_SW,		2},	//EDmaMemToMem0,

	{EDMACtrl32		,0     ,1			,KHvDMACHC_SW,		2},	//EDmaMemToMem1,

	{EDMACtrl32		,2     ,4			,KHvDMACHC_SW,		2},	//EDmaMemToMem2,

	{EDMACtrl32		,2     ,5			,KHvDMACHC_SW,		2},	//EDmaMemToMem3,

    };

/* Maps physical EDMACtrl32 channels into logical ones */

static const int DMAC32_HWChannelsLocator[KDmaHWCtrl32Count][KDmaCtrl32HWSubChannelCount] = 

	{

	{EDmaMemToMem0,EDmaMemToMem1,EDMAChannelUART0RX,EDMAChannelUART0TX,

								EDMAChannelUART1RX,EDMAChannelUART1TX,EDMAChannelUART2RX,EDMAChannelUART2TX},

	{-1,-1,-1,-1,-1,-1,-1,-1},

	{-1,-1,EDMAChannelSD0,EDMAChannelSD1,EDmaMemToMem2,EDmaMemToMem3,-1,-1},

	{ EDMAChannelI2S0RX,EDMAChannelI2S0TX,EDMAChannelI2S1RX,EDMAChannelI2S1TX,

									EDMAChannelI2S2RX,EDMAChannelI2S2TX,EDMAChannelI2S3RX,EDMAChannelI2S3TX},

	{-1,-1,-1,-1,-1,-1,-1,-1},

	};

class TDmaDesc

//

// Hardware DMA descriptor

//

	{

public:

	TPhysAddr iSrcAddr;

	TPhysAddr iDestAddr;

	TInt iCount;	      //Transfer counter in bytes

	};

//

// Test Support

//

//The list of S/W channels to be tested by t_dma

TUint32 TestNEChannels[] = { EDmaMemToMem0, EDmaMemToMem1, EDmaMemToMem2, EDmaMemToMem3};

TDmaTestInfo TestInfo =

	{

	4*KMaxDMAUnitTransferLen, //a word is a unit of transfer for mem-to-mem DMA

	3,	// Word alignement applies fow S/W (mem-to-mem) transfer

	0,  // No need for cookie.

	4,	// The number of S/W DMA channels to test

	TestNEChannels,

	0,

	NULL,

	0,

	NULL

	};

EXPORT_C const TDmaTestInfo& DmaTestInfo()

	{

	return TestInfo;

	}

//

// Helper Functions

//

inline TBool IsHwDesAligned(TAny* aDes)

//

// We do no need H/W descriptors to be aligned as Navi Engine DMA32 cotroller doesn't

// support linked descriptors. Instead, they are linked by S/W. Therefore, the ordinary

// word alignement applies (which is enforced by compiler).

//

	{

	return ((TLinAddr)aDes & 0x3) == 0;

	}

// Channel class.

// For double buffering, we cannot use the provided TDmaDbChannel class because 

// NE DMA has two sets of registers (base & work) - wich is not supported by TDmaDbChannel.

#if defined(NE1_DMA_DOUBLE_BUFFER)

class TNE1DmaChannel : public TDmaChannel

#else

class TNE1DmaChannel : public TDmaSbChannel

#endif

	{

public:

	TNE1DmaChannel();

	void ProcessIrq();

	void ProcessErrorIrq();

	void StopTransfer();

	void Close();

	inline TBool IsIdle() const;

private:

#if defined(NE1_DMA_DOUBLE_BUFFER)

	virtual void DoQueue(DDmaRequest& aReq);

	virtual void DoCancelAll();

	virtual void DoDfc(DDmaRequest& aCurReq, SDmaDesHdr*& aCompletedHdr);

private:

	enum { EIdle = 0, ETransferring, ETransferringLast } iState;

#endif

	virtual void QueuedRequestCountChanged();

	inline void ProcessTC(TBool aClearStatus);

	inline void ProcessEnd(TBool aClearStatus);

	inline void ClearStatus(TUint32 aBitmask);

	inline void HandleIsr(TBool aIsComplete);

public:

	TInt iHWCtrlBase;// Base address of H/W registers for this channel.

	TInt iSubChannel;// Subchannel number (0-7) within H/W controller.

	TInt iDMACHCReg; // The content of configuration (CHC) register for this channel.

	TInt iTransferDataShift;//log2 of basic unit of transfer. See TDMAChannelLocator::iTransferShiftSize

	// The following members are public so that they can be

	// modified by the TNaviEngineDmac class

	/**

	This flag is set when the base register set is filled

	It allows the ISR to detect the case where a base to work

	register set changeover has happened (END interrupt) but has been masked by

	the completion of the work register set

	*/

	TBool iBaseValidSet;

	/**

	This counter is incremented each time a LaunchTransfer is started

	and decremented when the ISR handles the transfer complete (TC

	bit). Ie. it does not keep count of the number of times the base

	register set is filled. This allows missed TC interrupts to be

	detected.

	*/

	TInt iTcIrqCount;

	/**

	This spinlock is used to protect both the iBaseValidSet and iTcIrqCount

	variables. It synchronises access between threads and the ISR.

	For the ISR the setting of iBaseValidSet must appear to be atomic with

	the launch of the transfer.

	For iTcIrqCount The spinlock makes the transfer launch and subsequent

	increase of the count appear atomic to the ISR. Otherwise it could

	observe a completed transfer before the count was incremented or

	vice-versa

	*/

	TSpinLock iIsrLock;

	};

//

// Derived Controller Class

//

class TNaviEngineDmac : public TDmac

	{

public:

	TNaviEngineDmac();

	TInt Create();

	friend void TNE1DmaChannel::HandleIsr(TBool); // Allow channel HandleIsr to call TDmac::HandleIsr

private:

	// from TDmac (PIL pure virtual)

	virtual void Transfer(const TDmaChannel& aChannel, const SDmaDesHdr& aHdr);

	virtual void StopTransfer(const TDmaChannel& aChannel);

	virtual TBool IsIdle(const TDmaChannel& aChannel);

	virtual TInt MaxTransferSize(TDmaChannel& aChannel, TUint aFlags, TUint32 aPslInfo);

	virtual TUint MemAlignMask(TDmaChannel& aChannel, TUint aFlags, TUint32 aPslInfo);

	// from TDmac (PIL virtual)

	virtual void InitHwDes(const SDmaDesHdr& aHdr, TUint32 aSrc, TUint32 aDest, TInt aCount,

 						   TUint aFlags, TUint32 aPslInfo, TUint32 aCookie);

	virtual void ChainHwDes(const SDmaDesHdr& aHdr, const SDmaDesHdr& aNextHdr);

	virtual void AppendHwDes(const TDmaChannel& aChannel, const SDmaDesHdr& aLastHdr,

							 const SDmaDesHdr& aNewHdr);

	virtual void UnlinkHwDes(const TDmaChannel& aChannel, SDmaDesHdr& aHdr);

	// other

	static void DMAC32_Isr(TAny* aThis, TInt aController, TInt aTcsMask, TInt aCompleted);

	static void DMAC32_0_End_Isr(TAny* aThis);

	static void DMAC32_0_Err_Isr(TAny* aThis);

	static void DMAC32_2_End_Isr(TAny* aThis);

	static void DMAC32_2_Err_Isr(TAny* aThis);

	static void DMAC32_3_End_Isr(TAny* aThis);

	static void DMAC32_3_Err_Isr(TAny* aThis);

	static void InitHWChannel (ENaviEngineDmaController aNEController, TInt aGroup, TInt aSubChannel);

	static void InitAllHWChannels ();

	inline TDmaDesc* HdrToHwDes(const SDmaDesHdr& aHdr);

private:

	static const SCreateInfo KInfo;

public:

	void PopulateWorkSet(TNE1DmaChannel& aChannel, const SDmaDesHdr& aHdr);

	void LaunchTransfer(TNE1DmaChannel& aChannel, TBool aBaseSetValid);

#if defined(NE1_DMA_DOUBLE_BUFFER)

	void PopulateBaseSet(TNE1DmaChannel& aChannel, const SDmaDesHdr& aHdr);

	void ContinueTransfer(TNE1DmaChannel& aChannel, TBool aBaseSetValid);

#endif

	TNE1DmaChannel iChannels[EDmaChannelCount];

	};

static TNaviEngineDmac Controller;

const TDmac::SCreateInfo TNaviEngineDmac::KInfo =

	{

	EDmaChannelCount,

	KDesCount,

	TDmac::KCapsBitHwDes,

	sizeof(TDmaDesc),

	EMapAttrSupRw | EMapAttrFullyBlocking //??

	};

TNaviEngineDmac::TNaviEngineDmac()

//

// Constructor.

//

	: TDmac(KInfo)

	{}

TInt TNaviEngineDmac::Create()

//

// Second phase construction.

//

	{

	TInt r = TDmac::Create(KInfo);							// Base class Create()

	if (r == KErrNone)

		{

		__DMA_ASSERTA(ReserveSetOfDes(EDmaChannelCount) == KErrNone);

		//Read KDMAChannelLocator constants and populate the values in channel objects.

		for (TInt i=0; i < EDmaChannelCount; ++i)

			{

			TUint ctrlBase = 0;

			switch (KDMAChannelLocator[i].iDMACtrl)

				{

				case EDmaCtrlExBus: ctrlBase = KDMACExBusBase; break;

				case EDMACtrl32:	ctrlBase = KDMAC32Base;	   break;

				default:			__DMA_CANT_HAPPEN();

				}

			iChannels[i].iHWCtrlBase = ctrlBase + KDMAChannelLocator[i].iGroup * KDMAGroupOffset + 

														KDMAChannelLocator[i].iSubChannel * KDMAChannelOffset;

			iChannels[i].iSubChannel = KDMAChannelLocator[i].iSubChannel;

			iChannels[i].iDMACHCReg = KDMAChannelLocator[i].iDMACHCReg | iChannels[i].iSubChannel;

			iChannels[i].iTransferDataShift = KDMAChannelLocator[i].iTransferShiftSize;

			iFreeHdr = iFreeHdr->iNext;

			}

		//Bind DMA interrupt for channels we support

		TInt irqh0 = Interrupt::Bind(KIntDMAC32_0_End, DMAC32_0_End_Isr, this); __DMA_ASSERTA(irqh0>=0); 

		TInt irqh1 = Interrupt::Bind(KIntDMAC32_0_Err, DMAC32_0_Err_Isr, this); __DMA_ASSERTA(irqh1>=0); 

		TInt irqh2 = Interrupt::Bind(KIntDMAC32_2_End, DMAC32_2_End_Isr, this); __DMA_ASSERTA(irqh2>=0); 

		TInt irqh3 = Interrupt::Bind(KIntDMAC32_2_Err, DMAC32_2_Err_Isr, this); __DMA_ASSERTA(irqh3>=0); 

		TInt irqh4 = Interrupt::Bind(KIntDMAC32_3_End, DMAC32_3_End_Isr, this); __DMA_ASSERTA(irqh4>=0); 

		TInt irqh5 = Interrupt::Bind(KIntDMAC32_3_Err, DMAC32_3_Err_Isr, this); __DMA_ASSERTA(irqh5>=0); 

		if (r == KErrNone)

			{

			InitAllHWChannels();

			r = Interrupt::Enable(irqh0); __DMA_ASSERTA(r==KErrNone);

			r = Interrupt::Enable(irqh1); __DMA_ASSERTA(r==KErrNone);

			r = Interrupt::Enable(irqh2); __DMA_ASSERTA(r==KErrNone);

			r = Interrupt::Enable(irqh3); __DMA_ASSERTA(r==KErrNone);

			r = Interrupt::Enable(irqh4); __DMA_ASSERTA(r==KErrNone);

			r = Interrupt::Enable(irqh5); __DMA_ASSERTA(r==KErrNone);

			}

		}

	return r;

	}

// Initialises all H/W channels. This will make sure they are off on soft restart.

void TNaviEngineDmac::InitAllHWChannels()

	{

	int i,j;

	for (i=0;i<KDmaHWCtrl32Count;i++)

		{

		for (j=0;j<KDmaCtrl32HWSubChannelCount; j++) InitHWChannel(EDMACtrl32, i, j);

		AsspRegister::Write32(KDMAC32Base+i*KDMAGroupOffset+KHoDMACONT, 0);

		}

	}

//Initialises a single H/W channel

void TNaviEngineDmac::InitHWChannel (ENaviEngineDmaController aNEController, TInt aGroup, TInt aSubChannel)

	{

	TUint neCtrlBase = 0;

	switch(aNEController)

		{

		case EDMACtrl32: 	neCtrlBase = KDMAC32Base   ; break;

		default:			__DMA_CANT_HAPPEN();

		}

	neCtrlBase += aGroup*KDMAGroupOffset + aSubChannel*KDMAChannelOffset;

	AsspRegister::Write32(neCtrlBase+KHoDMACHS, KHtDMACHS_EN_EN);	//disable channel

	}

#if defined(NE1_DMA_DOUBLE_BUFFER)

#ifdef _DEBUG

//These values indicate whether all corner cases are running.

//Proper test shouldn't leave any of these values to zero.

TInt InterruptCounter_DMA32 = 0;	// Interrupt counter

TInt Transfer_IdleOnStart = 0;	    // DMA channel is idle on the start of Transfer.

TInt Transfer_NotIdleOnStart = 0;   // DMA channel is not idle on the start of Transfer.

TInt Transfer_MatchWorkSetTrue = 0; // Descriptor matches "work set" registers

TInt Transfer_MatchWorkSetFalse = 0;// Descriptor doesn't match "work set" descriptor.

#endif

void TNaviEngineDmac::Transfer(const TDmaChannel& aChannel, const SDmaDesHdr& aHdr)

//

// Initiates a (previously constructed) request on a specific channel.

//

	{

	TDmaChannel& mutableChannel = const_cast<TDmaChannel&>(aChannel);

	TNE1DmaChannel& channel = static_cast<TNE1DmaChannel&>(mutableChannel);

	const TInt irq =  __SPIN_LOCK_IRQSAVE(channel.iIsrLock);

	// The fragment descriptor (src/dest address, size) should be placed into either "Work Set" or "Base Set"

	// depending on the actual state of the H/W

	if (IsIdle(channel))

		{

		// The channel is idle, for the (most likely) reason that both "Work Set" and "Base Set" transfers are

		// completed since the last time we run this function. 

		#ifdef _DEBUG

		Transfer_IdleOnStart++;

		#endif

		PopulateWorkSet(channel, aHdr); // Populate "Work Set"

		LaunchTransfer(channel, EFalse);   // Start the transfer, base set is invalid

		}

	else

		{

		// "Work Set" transfer is still going on. It seems we will manage to place

		// the next fragment in time for continious traffic flow.

		#ifdef _DEBUG

		Transfer_NotIdleOnStart++;

		#endif

		PopulateBaseSet(channel, aHdr);  // Populate "Base Set"

		ContinueTransfer(channel, ETrue);// Indicate Base Set is valid (bvalid = ETrue)

		// We should expect here that the "work set" traffic is still in progress.

		// Once it is completed, "Base Set" content is copied into "Work Set" and the traffic will go on.

		// However, there is a corner case where we configure "Base Set" too late.

		// Therefore, check if transfer is still active.

		if (IsIdle(channel))

			{

			// There is no DMA traffic. There could be two reason for that. Either,

			// 1. The transfer we have just configured in "Base Set" has already completed, or

			// 2. We configured base set too late, after "Work Set" transfer has already finished.

			// Check BVALID bit

			// if its now clear, then it was set in time, if it's

			// still set it was set too late

			const TUint32 dchs = AsspRegister::Read32(channel.iHWCtrlBase+KHoDMACHS);

			const TBool bvalidSet = dchs & KHtDMACHS_BVALID;

			if (!bvalidSet)

				{

				DMA_PSL_CHAN_TRACE_STATIC(channel, "Base set transferred already");

				#ifdef _DEBUG

				Transfer_MatchWorkSetTrue++;

				#endif

				}

			else

				{

				DMA_PSL_CHAN_TRACE_STATIC(channel, "Too late for base set");

				// BVALID bit was set after "Work Set" transfer completed, and DMA H/W didn't

				// copy the content of "Base Set" into "Work Set". We have to re-launch the transfer.

				// This time we have to configure "Work Set"

				#ifdef _DEBUG

				Transfer_MatchWorkSetFalse++;

				#endif

				PopulateWorkSet(channel, aHdr); // Populate "Work Set".

				LaunchTransfer(channel, EFalse);   // Start the transfer, "Base Set" is invalid.

				}

			}

		}

	__SPIN_UNLOCK_IRQRESTORE(channel.iIsrLock, irq);

	}

#else

void TNaviEngineDmac::Transfer(const TDmaChannel& aChannel, const SDmaDesHdr& aHdr)

//

// Initiates a (previously constructed) request on a specific channel.

//

	{

	TDmaChannel& mutableChannel = const_cast<TDmaChannel&>(aChannel);

	TNE1DmaChannel& channel = static_cast<TNE1DmaChannel&>(mutableChannel);

	DMA_PSL_CHAN_TRACE_STATIC1(channel, ">TNaviEngineDmac::Transfer des=0x%08X", HdrToHwDes(aHdr));

	const TInt irq =  __SPIN_LOCK_IRQSAVE(channel.iIsrLock);

	// The fragment descriptor (src/dest address, size) should be placed into either "Work Set" or "Base Set"

	// depending on the actual state of the H/W

	__NK_ASSERT_ALWAYS(IsIdle(channel));

	PopulateWorkSet(channel, aHdr); // Populate "Work Set"

	LaunchTransfer(channel, EFalse);   // Start the transfer, base set is invalid

	__SPIN_UNLOCK_IRQRESTORE(channel.iIsrLock, irq);

	}

#endif

void TNaviEngineDmac::StopTransfer(const TDmaChannel& aChannel)

//

// Stops a running channel.

//

	{

	TDmaChannel& mutableChannel = const_cast<TDmaChannel&>(aChannel);

	TNE1DmaChannel& channel = static_cast<TNE1DmaChannel&>(mutableChannel);

	__KTRACE_OPT(KDMA, Kern::Printf(">TNaviEngineDmac::StopTransfer channel=%d", channel.PslId()));

	channel.StopTransfer();

	__KTRACE_OPT(KDMA, Kern::Printf("<TNaviEngineDmac::StopTransfer channel=%d", channel.PslId()));

	}

TBool TNaviEngineDmac::IsIdle(const TDmaChannel& aChannel)

	{

	TDmaChannel& mutableChannel = const_cast<TDmaChannel&>(aChannel);

	TNE1DmaChannel& channel = static_cast<TNE1DmaChannel&>(mutableChannel);

	const TBool idle = channel.IsIdle();

	__KTRACE_OPT(KDMA, Kern::Printf(">Dmac::IsIdle channel=%d, idle=%d", channel.PslId(), idle));

	return idle;

	}

// Places the descriptor into "Work Set"

void TNaviEngineDmac::PopulateWorkSet(TNE1DmaChannel& aChannel, const SDmaDesHdr& aHdr)

	{

	TDmaDesc* pD = HdrToHwDes(aHdr);

	__KTRACE_OPT(KDMA, Kern::Printf(">TNaviEngineDmac::PopulateWorkSet channel=%d des=0x%08X", aChannel.PslId(), pD));

	AsspRegister::Write32(aChannel.iHWCtrlBase+KHoDMACHC, aChannel.iDMACHCReg);	//configure channel

	AsspRegister::Write32(aChannel.iHWCtrlBase+KHoDMASAW, pD->iSrcAddr); 		//source addr 

	AsspRegister::Write32(aChannel.iHWCtrlBase+KHoDMADAW, pD->iDestAddr);		//dest addr

	AsspRegister::Write32(aChannel.iHWCtrlBase+KHoDMATCW, (pD->iCount>>aChannel.iTransferDataShift)-1);	//transfer counter

	}

// Starts the transfer.

// @pre The chanel is idle.

// @arg aBaseSetValid if true, BVALID bit should be set.

// @pre iIsrLock must be held

void TNaviEngineDmac::LaunchTransfer(TNE1DmaChannel& aChannel, TBool aBaseSetValid)

	{

	__KTRACE_OPT(KDMA, Kern::Printf(">TNaviEngineDmac::LaunchTransfer channel=%d", aChannel.PslId()));

	TInt val = KHtDMACHS_EN|KHtDMACHS_EN_EN;

	if (TUint(aChannel.iDMACHCReg ^ aChannel.iSubChannel) == (TUint)KHvDMACHC_SW)

		val |=KHtDMACHS_STG;

	if (aBaseSetValid)

		val|=KHtDMACHS_BVALID;

	aChannel.iBaseValidSet = aBaseSetValid;

	AsspRegister::Write32(aChannel.iHWCtrlBase+KHoDMACHS, val);

	aChannel.iTcIrqCount++;

	DMA_PSL_CHAN_TRACE_STATIC1(aChannel, "inc iTcIrqCount to %d", aChannel.iTcIrqCount);

	}

#if defined(NE1_DMA_DOUBLE_BUFFER)

// Places the descriptor into "Base Set"

void TNaviEngineDmac::PopulateBaseSet(TNE1DmaChannel& aChannel, const SDmaDesHdr& aHdr)

	{

	TDmaDesc* pD = HdrToHwDes(aHdr);

	__KTRACE_OPT(KDMA, Kern::Printf(">TNaviEngineDmac::PopulateBaseSet channel=%d des=0x%08X", aChannel.PslId(), pD));

	AsspRegister::Write32(aChannel.iHWCtrlBase+KHoDMASAB, pD->iSrcAddr); 								// Source addr

	AsspRegister::Write32(aChannel.iHWCtrlBase+KHoDMADAB, pD->iDestAddr);								// Dest addr

	AsspRegister::Write32(aChannel.iHWCtrlBase+KHoDMATCB, (pD->iCount>>aChannel.iTransferDataShift)-1); // Transfer counter

	}

// @pre DMA transfer is in progress.

// @arg aBaseSetValid if true, BVALID bit should be set.

// @pre iIsrLock must be held

void TNaviEngineDmac::ContinueTransfer(TNE1DmaChannel& aChannel, TBool aBaseSetValid)

	{

	__KTRACE_OPT(KDMA, Kern::Printf(">TNaviEngineDmac::ContinueTransfer channel=%d", aChannel.PslId()));

	TInt val = 0;

	if (TUint(aChannel.iDMACHCReg ^ aChannel.iSubChannel) == (TUint)KHvDMACHC_SW)

		val |=KHtDMACHS_STG;	// Set software trigger

	if (aBaseSetValid)

		{

		__NK_ASSERT_DEBUG(!aChannel.iBaseValidSet);