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1 ; |
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2 ; Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies). |
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3 ; All rights reserved. |
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4 ; This component and the accompanying materials are made available |
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5 ; under the terms of "Eclipse Public License v1.0" |
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6 ; which accompanies this distribution, and is available |
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7 ; at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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8 ; |
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9 ; Initial Contributors: |
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10 ; Nokia Corporation - initial contribution. |
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11 ; |
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12 ; Contributors: |
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13 ; |
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14 ; Description: |
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15 ; |
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16 |
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17 ; |
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18 ; NE1_TBVariant bootstrap configuration file |
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19 |
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20 ; Include to enable tracing |
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21 ; GBLL CFG_DebugBootRom |
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22 |
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23 ; Include to initialise debug port in bootstrap without enabling bootstrap |
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24 ; trace. Useful for __EARLY_DEBUG__ mode. |
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25 ; GBLL CFG_InitDebugPort |
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26 |
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27 ; Include one of these to select the CPU |
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28 GBLL CFG_CPU_ARM11MP |
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29 |
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30 ; Include the following line if this is a bootloader bootstrap |
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31 ; GBLL CFG_BootLoader |
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32 |
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33 ; Use the alternate entrypoint into the bootstrap code |
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34 GBLL CFG_AlternateEntryPoint |
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35 |
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36 ; Defining CFG_CopyRomToAddress will trigger the generic bootstrap code to copy the rom to the nominated location. |
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37 INIT_NUMERIC_CONSTANT CFG_CopyRomToAddress, 0x86000000 |
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38 |
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39 ; If you want to supply a custom set of initial vectors (including reset vector) include the following line |
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40 ; GBLL CFG_CustomVectors |
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41 ; |
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42 ; and provide a custom_vectors.inc file |
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43 |
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44 ; Variant Number |
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45 INIT_NUMERIC_CONSTANT CFG_HWVD, 0x09080001 |
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46 |
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47 ; Include the following line if default memory mapping should use shared memory. |
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48 ; Should be defined on multicore (SMP) devices. |
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49 GBLL CFG_USE_SHARED_MEMORY |
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50 |
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51 ; On ARM architecture 6 processors, include the following line to override the threshold |
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52 ; on total physical RAM size at which the multiple memory model switches into large address space mode |
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53 ; i.e. size>threshold -> 2Gb per process, size<=threshold -> 1Gb per process |
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54 ; Defaults to 32Mb. |
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55 ; INIT_NUMERIC_CONSTANT CFG_ARMV6_LARGE_CONFIG_THRESHOLD, <value> |
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56 |
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57 ; For the direct memory model only, include the following line if you wish the exception vectors at the |
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58 ; start of the bootstrap to be used at all times. This is only relevant if an MMU is present - this option |
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59 ; is mandatory if not. |
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60 ; GBLL CFG_UseBootstrapVectors |
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61 ; |
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62 ; If the above option is in use (including if no MMU is present) the following symbol should be defined |
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63 ; to specify the offset from the bootstrap to the kernel image. |
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64 INIT_NUMERIC_CONSTANT KernelCodeOffset, 0x4000 |
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65 |
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66 ; Include the following line if you wish to include the ROM autodetection code based on data bus |
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67 ; capacitance and image repeats. |
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68 ; GBLL CFG_AutoDetectROM |
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69 |
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70 ; Include the following line to minimise the initial kernel heap size |
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71 ; On the direct memory model the size of the kernel data area (super page to end of kernel heap) |
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72 ; is rounded up to the next 1Mb if this is not included, 4K if it is. |
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73 ; On the moving and multiple models, the size of the initial kernel heap area is rounded up to |
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74 ; the next 64K if this is not included, 4K if it is. |
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75 ; GBLL CFG_MinimiseKernelHeap |
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76 |
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77 ; On the moving or multiple memory models, include either or both of the following lines to |
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78 ; specify the size of the initial kernel heap |
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79 ; INIT_NUMERIC_CONSTANT CFG_KernelHeapMultiplier, <multiplier> |
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80 ; INIT_NUMERIC_CONSTANT CFG_KernelHeapBaseSize, <base> |
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81 ; |
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82 ; The initial kernel heap size is MAX( <base> + <multiplier> * N / 16, value specified in ROMBUILD ) |
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83 ; where N is the total physical RAM size in pages. |
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84 ; <base> defaults to 24K and <multiplier> defaults to 9*16 (ie 9 bytes per page). |
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85 |
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86 ; Uncomment if using ARM1136 processor and ARM1136 Erratum 353494 |
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87 ; "Rare conditions can cause corruption of the Instruction Cache" |
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88 ; is fixed on this hardware. |
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89 ; |
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90 ; NOTE: The boot table should use this macro to determine whether RONO or RORO permissions |
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91 ; are used for the exception vectors. If the erratum is not fixed, RORO must be used. |
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92 ; |
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93 ; GBLL CFG_CPU_ARM1136_ERRATUM_353494_FIXED |
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94 |
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95 ; Uncomment if using ARM1136 processor and ARM1136 Erratum 364296 |
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96 ; "Possible Cache Data Corruption with Hit-Under-Miss" |
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97 ; is fixed on this hardware. |
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98 ; |
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99 ; GBLL CFG_CPU_ARM1136_ERRATUM_364296_FIXED |
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100 |
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101 ; Uncomment if using ARM1136 processor and ARM1136 Erratum 399234 |
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102 ; "Write back data cache entry evicted by write through entry causes data corruption" |
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103 ; is fixed on this hardware. |
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104 ; Workaround |
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105 ; The erratum may be avoided by marking all cacheable memory as one of write through or write back. |
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106 ; This requires the memory attributes described in the translation tables to be modified by software |
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107 ; appropriately, or the use of the remapping capability to remap write through regions to non cacheable. |
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108 ; |
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109 ; If this macro is enabled, it should be accompanied by: |
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110 ; "#define __CPU_ARM1136_ERRATUM_399234_FIXED" in variant.mmh |
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111 ; GBLL CFG_CPU_ARM1136_ERRATUM_399234_FIXED |
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112 |
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113 |
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114 ; Uncomment if: |
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115 ; 1) using ARM1136 processor and ARM1136 Erratum 411920: "Invalidate Entire Instruction Cache |
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116 ; operation might fail to invalidate some lines if coincident with linefill" |
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117 ; is fixed on this hardware, or |
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118 ; 2) using ARM1176 processor and ARM1176 Erratum 415045: "Invalidate Entire Instruction Cache |
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119 ; operation might fail to invalidate some lines if coincident with linefill |
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120 ; is fixed on this hardware. |
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121 ; Workaround: |
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122 ; 1) Disables the use of of prefetch range cache operations by setting RV bit in Auxiliary Ctrl Reg. |
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123 ; 2) Replaces Invalidate ICache operation with the sequence defined in the errata document. |
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124 ; If this macro is enabled, it should be accompanied by: |
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125 ; "#define __CPU_ARM1136_ERRATUM_411920_FIXED" in variant.mmh |
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126 ; |
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127 ; GBLL CFG_CPU_ARM1136_ERRATUM_411920_FIXED |
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128 |
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129 |
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130 ; Uncomment if using ARM1136 processor and ARM1136 Erratum 415662: "Invalidate Instruction Cache by |
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131 ; Index might corrupt cache when used with background prefetch range" is fixed on this hardware. |
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132 ; Workaround: |
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133 ; Disables the use of of prefetch range cache operations by setting RV bit in Auxiliary Ctrl Reg. |
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134 ; |
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135 ; GBLL CFG_CPU_ARM1136_ERRATUM_415662_FIXED |
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136 |
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137 |
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138 ; Uncomment if this variant config needs to support the Shadow Memory Regions |
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139 ; (SMR) feature in the kernel. Basically allows media based images to be copied |
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140 ; into memory which is later reserved by the Kernel RAM Allocator. |
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141 ; One user of the SMR feature is the HCR component when used with media based |
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142 ; setting repository. Thus variant configs that support the new MHA HCR |
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143 ; component and expect media based settings must define this macro e.g. NAND |
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144 ; Core Image ROM, but not BootLoader ROM etc. |
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145 ; |
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146 ; GBLL CFG_ENABLE_SMR_SUPPORT |
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147 |
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148 |
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149 ; These are deduced from the supplied configuration |
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150 ; CFG_ARMV6 |
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151 ; CFG_MMUPresent |
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152 ; CFG_CachePresent |
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153 ; CFG_WriteBufferPresent |
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154 ; CFG_SplitCache |
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155 ; CFG_SplitTLB |
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156 ; CFG_AltDCachePresent |
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157 ; CFG_WriteBackCache |
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158 ; CFG_CacheWriteAllocate |
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159 ; CFG_CachePhysicalTag |
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160 ; CFG_CacheFlushByDataRead |
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161 ; CFG_CacheFlushByWaySetIndex |
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162 ; CFG_CacheFlushByLineAlloc |
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163 ; CFG_CachePolicyInPTE |
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164 ; CFG_TEX |
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165 ; CFG_SingleEntryDCacheFlush |
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166 ; CFG_SingleEntryICacheFlush |
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167 ; CFG_SingleEntryITLBFlush |
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168 ; CFG_SingleEntryTLBFlush |
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169 ; CFG_CacheTypeReg |
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170 ; CFG_BTBPresent |
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171 ; CFG_CARPresent |
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172 ; CFG_PrefetchBuffer |
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173 ; CFG_FCSE_Present |
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174 ; CFG_ASID_Present |
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175 ; CFG_IncludeRAMAllocator |
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176 |
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177 END |