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1 /* |
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2 * Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies). |
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3 * All rights reserved. |
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4 * This component and the accompanying materials are made available |
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5 * under the terms of "Eclipse Public License v1.0" |
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6 * which accompanies this distribution, and is available |
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7 * at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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8 * |
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9 * Initial Contributors: |
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10 * Nokia Corporation - initial contribution. |
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11 * |
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12 * Contributors: |
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13 * |
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14 * Description: |
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15 * naviengine_assp\assp.cpp |
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16 * |
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17 */ |
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18 |
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19 |
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20 |
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21 #include <naviengine_priv.h> |
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22 #include <upd35001_timer.h> |
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23 |
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24 NaviEngineAssp* NaviEngineAssp::Variant=NULL; |
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25 TPhysAddr NaviEngineAssp::VideoRamPhys; |
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26 |
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27 |
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28 DECLARE_STANDARD_ASSP() |
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29 |
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30 EXPORT_C NaviEngineAssp::NaviEngineAssp() |
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31 { |
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32 NaviEngineAssp::Variant=this; |
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33 iDebugInitialised = EFalse; |
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34 |
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35 /* Initialize timers 1 and 2 to generate the system timestamp counter */ |
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36 NETimer& T1 = NETimer::Timer(1); |
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37 NETimer& T2 = NETimer::Timer(2); |
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38 |
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39 T1.iTimerCtrl = 0; // stop and reset timer 1 |
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40 T1.iGTICtrl = 0; // disable timer 1 capture modes |
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41 T2.iTimerCtrl = 0; // stop and reset timer 2 |
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42 T2.iGTICtrl = 0; // disable timer 2 capture modes |
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43 __e32_io_completion_barrier(); |
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44 #ifdef __SMP__ |
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45 T1.iPrescaler = KNETimerPrescaleBy1; // Timer 1 prescaled by 1 (=66.667MHz) |
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46 T2.iPrescaler = KNETimerPrescaleBy1; // Timer 2 prescaled by 1 (=66.667MHz) |
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47 #else |
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48 T1.iPrescaler = KNETimerPrescaleBy32; // Timer 1 prescaled by 32 (=2.0833MHz) |
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49 T2.iPrescaler = KNETimerPrescaleBy32; // Timer 2 prescaled by 32 (=2.0833MHz) |
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50 #endif |
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51 __e32_io_completion_barrier(); |
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52 T1.iGTInterruptEnable = 0; |
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53 T2.iGTInterruptEnable = 0; |
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54 __e32_io_completion_barrier(); |
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55 T1.iGTInterrupt = KNETimerGTIInt_All; |
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56 T2.iGTInterrupt = KNETimerGTIInt_All; |
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57 __e32_io_completion_barrier(); |
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58 T1.iTimerCtrl = KNETimerCtrl_CE; // deassert reset for timer 1, count still stopped |
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59 T2.iTimerCtrl = KNETimerCtrl_CE; // deassert reset for timer 2, count still stopped |
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60 __e32_io_completion_barrier(); |
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61 T1.iTimerReset = 0xfffffeffu; // timer 1 wraps after 2^32-256 counts |
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62 T2.iTimerReset = 0xffffffffu; // timer 2 wraps after 2^32 counts |
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63 __e32_io_completion_barrier(); |
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64 T1.iTimerCtrl = KNETimerCtrl_CE | KNETimerCtrl_CAE; // start timer 1 |
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65 __e32_io_completion_barrier(); // make sure timer 1 started before timer 2 |
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66 T2.iTimerCtrl = KNETimerCtrl_CE | KNETimerCtrl_CAE; // start timer 2 |
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67 __e32_io_completion_barrier(); |
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68 |
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69 // Each time T1 wraps, (T1-T2) increases by 256 after starting at 0 |
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70 // t1=T1; t2=T2; n=(t1-t2)>>8; time = t1 + n * (2^32-256) |
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71 |
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72 } |
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73 |
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74 extern void MsTimerTick(TAny* aPtr); |
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75 |
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76 |
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77 EXPORT_C TMachineStartupType NaviEngineAssp::StartupReason() |
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78 { |
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79 __KTRACE_OPT(KBOOT,Kern::Printf("NaviEngineAssp::StartupReason")); |
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80 #ifdef _DEBUG // REMOVE THIS |
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81 TUint s = Kern::SuperPage().iHwStartupReason; |
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82 __KTRACE_OPT(KBOOT,Kern::Printf("CPU page value %08x", s)); |
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83 #endif // REMOVE THIS |
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84 // |
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85 // TO DO: (mandatory) |
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86 // |
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87 // Map the startup reason read from the Super Page to one of TMachineStartupType enumerated values |
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88 // and return this |
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89 // |
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90 return EStartupCold; // EXAMPLE ONLY |
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91 } |
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92 |
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93 EXPORT_C void NaviEngineAssp::Init1() |
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94 { |
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95 __KTRACE_OPT(KBOOT,Kern::Printf("NaviEngineAssp::Init1()")); |
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96 // |
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97 // TO DO: (optional) |
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98 // |
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99 NaviEngineInterrupt::Init1(); // initialise the ASSP interrupt controller |
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100 |
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101 // |
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102 // TO DO: (optional) |
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103 // |
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104 // Initialises any hardware blocks which require early initialisation, e.g. enable and power the LCD, set up |
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105 // RTC clocks, disable DMA controllers. etc. |
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106 // |
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107 TNaviEngine::Init1(); |
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108 } |
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109 |
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110 |
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111 EXPORT_C void NaviEngineAssp::Init3() |
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112 { |
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113 __KTRACE_OPT(KBOOT,Kern::Printf("NaviEngineAssp::Init3()")); |
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114 |
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115 TNaviEngine::Init3(); |
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116 |
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117 #ifdef TOGLE_UART_DTR_LINE |
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118 AsspRegister::Write32(KHwRwGpio_Port_Control_Enable, 1<<9); |
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119 #endif |
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120 |
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121 |
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122 NTimerQ& m=*(NTimerQ*)NTimerQ::TimerAddress(); |
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123 iTimerQ=&m; |
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124 |
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125 // Initialize timer 0 to generate the 1ms periodic system tick |
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126 NETimer& NET = NETimer::Timer(0); |
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127 NET.iTimerCtrl = 0; // reset counter |
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128 NET.iGTICtrl = 0; // disable input capture |
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129 __e32_io_completion_barrier(); |
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130 NET.iPrescaler = KNETimerPrescaleBy1; // prescaler divides by 1 |
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131 __e32_io_completion_barrier(); |
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132 NET.iTimerCtrl = KNETimerCtrl_CE; // take timer out of reset |
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133 __e32_io_completion_barrier(); |
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134 NET.iTimerReset = 66666; // clocks before timer reset (66.666MHz clock frequency) |
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135 __e32_io_completion_barrier(); |
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136 NET.iGTInterrupt = KNETimerGTIInt_All; // clear any pending interrupts |
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137 __e32_io_completion_barrier(); |
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138 NET.iGTInterruptEnable = KNETimerGTIIntE_TCE; // enable counter reset interrupt |
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139 __e32_io_completion_barrier(); |
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140 NET.iTimerCtrl = KNETimerCtrl_CE | KNETimerCtrl_CAE; // start counter |
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141 __e32_io_completion_barrier(); |
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142 |
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143 // |
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144 // TO DO: (mandatory) |
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145 // |
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146 // If Hardware Timer used for System Ticks cannot give exactly the period required store the initial rounding value |
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147 // here which is updated every time a match occurrs. Note this leads to "wobbly" timers whose exact period change |
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148 // but averages exactly the required value |
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149 // e.g. |
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150 // m.iRounding=-5; |
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151 // |
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152 |
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153 TInt r=Interrupt::Bind(KIntIdOstMatchMsTimer,MsTimerTick,&m); // bind the System Tick interrupt |
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154 if (r<0) |
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155 Kern::Fault("BindMsTick",r); |
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156 |
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157 // |
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158 // TO DO: (mandatory) |
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159 // |
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160 // Clear any pending OST interrupts and enable any OST match registers. |
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161 // If possible may reset the OST here (to start counting from a full period). Set the harwdare to produce an |
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162 // interrupt on full count |
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163 // |
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164 |
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165 r=Interrupt::Enable(r); // enable the System Tick interrupt |
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166 if (r!=KErrNone) |
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167 Kern::Fault("EnbMsTick",r); |
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168 |
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169 // Allocate physical RAM for video buffer. |
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170 TInt vSize=VideoRamSize(); |
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171 r=Epoc::AllocPhysicalRam(2*vSize,NaviEngineAssp::VideoRamPhys); //Alloc memory for both secure and non-secure display. |
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172 if (r!=KErrNone) |
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173 Kern::Fault("AllocVRam",r); |
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174 } |
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175 |
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176 EXPORT_C TInt NaviEngineAssp::MsTickPeriod() |
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177 { |
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178 // Return the OST tick period (System Tick) |
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179 return 1000; |
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180 } |
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181 |
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182 EXPORT_C TInt NaviEngineAssp::SystemTimeInSecondsFrom2000(TInt& aTime) |
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183 { |
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184 aTime=(TInt)TNaviEngine::RtcData(); |
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185 __KTRACE_OPT(KHARDWARE,Kern::Printf("RTC READ: %d",aTime)); |
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186 return KErrNone; |
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187 } |
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188 |
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189 EXPORT_C TInt NaviEngineAssp::SetSystemTimeInSecondsFrom2000(TInt aTime) |
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190 { |
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191 // |
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192 // TO DO: (optional) |
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193 // |
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194 // Check if the RTC is running and is stable |
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195 // |
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196 __KTRACE_OPT(KHARDWARE,Kern::Printf("Set RTC: %d",aTime)); |
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197 TNaviEngine::SetRtcData(aTime); |
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198 __KTRACE_OPT(KHARDWARE,Kern::Printf("RTC: %d",TNaviEngine::RtcData())); |
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199 return KErrNone; |
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200 } |
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201 |
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202 EXPORT_C TUint32 NaviEngineAssp::NanoWaitCalibration() |
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203 { |
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204 // |
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205 // TO DO: (mandatory) |
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206 // |
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207 // Return the minimum time in nano-seconds that it takes to execute the following code: |
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208 // nanowait_loop: |
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209 // subs r0, r0, r1 |
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210 // bhi nanowait_loop |
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211 // |
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212 // If accurate timings are required by the Base Port, then it should provide it's own implementation |
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213 // of NanoWait which uses a hardware counter. (See Kern::SetNanoWaitHandler) |
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214 // |
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215 |
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216 return 0; // EXAMPLE ONLY |
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217 } |
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218 |
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219 EXPORT_C void NaviEngineAssp::DebugOutput(TUint aLetter) |
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220 // |
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221 // Output a character to the debug port |
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222 // |
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223 { |
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224 if (!iDebugInitialised) |
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225 { |
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226 TNaviEngine::InitDebugOutput(); |
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227 iDebugInitialised = ETrue; |
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228 } |
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229 TNaviEngine::DoDebugOutput(aLetter); |
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230 } |
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231 |