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1 /* |
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2 * Copyright (c) 2008-2010 Nokia Corporation and/or its subsidiary(-ies). |
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3 * All rights reserved. |
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4 * This component and the accompanying materials are made available |
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5 * under the terms of "Eclipse Public License v1.0" |
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6 * which accompanies this distribution, and is available |
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7 * at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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8 * |
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9 * Initial Contributors: |
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10 * Nokia Corporation - initial contribution. |
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11 * |
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12 * Contributors: |
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13 * |
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14 * Description: |
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15 * This file is part of the NE1_TB Variant Base Port |
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16 * Hardware Configuration Respoitory compiled repository in-line cpp. |
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17 * |
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18 */ |
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19 |
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20 |
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21 /** |
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22 @file hcr_psl_config_assp.inl |
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23 File provides setting definitions for the ASSP setting values applicable to the |
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24 NEC NaviEngine base port. These definitions also contain the setting value where |
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25 the setting value is no larger than a 32-bit integer. The values for |
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26 larger settings can be found in the peer file hcr_psl_config_assp_lsd.inl. |
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27 |
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28 @internalTechnology |
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29 */ |
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30 |
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31 |
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32 #ifndef HCR_PSL_CONFIG_ASSP_INL |
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33 #define HCR_PSL_CONFIG_ASSP_INL |
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34 |
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35 |
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36 // SSettingC gSettingsList[] = |
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37 // { |
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38 // |
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39 |
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40 /** |
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41 HCR Setting values for ASSP Hardware Block base virtual addresses for FMM and MMM. |
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42 */ |
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43 |
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44 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwBase_Uart0}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwBaseUart0)} } }, |
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45 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwBase_Uart1}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwBaseUart1)} } }, |
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46 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwBase_Uart2}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwBaseUart2)} } }, |
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47 |
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48 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwBase_MPCorePrivate}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwBaseMPCorePrivate)} } }, |
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49 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwBase_SCU}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwBaseSCU)} } }, |
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50 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwBase_IntIf}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwBaseIntIf)} } }, |
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51 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwBase_IntDist}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwBaseGlobalIntDist)} } }, |
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52 |
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53 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwBase_Timers}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwTimersBase)} } }, |
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54 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwBase_Watchdog}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwWatchdog)} } }, |
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55 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwBase_SystemCtrl}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwSystemCtrlBase)} } }, |
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56 |
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57 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwBase_Display}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwDisplayBase)} } }, |
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58 |
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59 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwBase_I2C}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwBaseI2C)} } }, |
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60 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwBase_I2S0}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwBaseI2S0)} } }, |
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61 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwBase_I2S1}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwBaseI2S1)} } }, |
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62 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwBase_I2S2}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwBaseI2S2)} } }, |
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63 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwBase_I2S3}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwBaseI2S3)} } }, |
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64 |
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65 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwBase_FPGA}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwFPGABase)} } }, |
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66 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwBase_CDDisp}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwBaseUart0)} } }, |
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67 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwBase_TSP}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwBaseUart0)} } }, |
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68 |
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69 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwBase_SPDIF}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwSPDIFBase)} } }, |
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70 |
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71 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwBase_CSI0}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwBaseCSI0)} } }, |
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72 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwBase_CSI1}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwBaseCSI1)} } }, |
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73 |
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74 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwBase_SDCtrl}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwBaseSDCtrl)} } }, |
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75 |
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76 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwBase_KDMACExBus}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KDMACExBusBase)} } }, |
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77 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwBase_KDMAC32}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KDMAC32Base)} } }, |
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78 |
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79 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwBase_Ethernet}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwBaseEthernet)} } }, |
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80 |
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81 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwBase_GPIOBase}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwGPIOBase)} } }, |
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82 |
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83 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwBase_PciBase}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwPciBase)} } }, |
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84 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwBase_PciBridgeExtern}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwPciBridgeExtern)} } }, |
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85 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwBase_PciBridgeUsb}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwPciBridgeUsb)} } }, |
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86 |
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87 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwBase_UsbHWindow}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwUsbHWindow)} } }, |
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88 |
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89 /* |
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90 HCR Setting values for ASSP Physical addresses. |
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91 */ |
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92 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_BaseMPcorePrivate}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwBaseMPcorePrivatePhys)} } }, |
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93 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_DDR2RamBase}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwDDR2RamBasePhys)} } }, |
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94 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_PCI}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwPCIPhys)} } }, |
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95 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_Internal}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwInternal)} } }, |
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96 |
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97 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_AXI64IC2}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwAXI64IC2Phys)} } }, |
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98 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_SATA}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwSATAPhys)} } }, |
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99 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_AXI64DMAC}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwAXI64DMACPhys)} } }, |
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100 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_Video}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwVideoPhys)} } }, |
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101 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_Disp}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwDispPhys)} } }, |
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102 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_SGX}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwSGXPhys)} } }, |
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103 |
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104 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_CFWindow2}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwCFWindow2Phys)} } }, |
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105 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_CFWindow1}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwCFWindow1Phys)} } }, |
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106 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_CFWindow0}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwCFWindow0Phys)} } }, |
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107 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_ATA6CS1}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwATA6_CS1Phys)} } }, |
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108 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_ATA6CS0}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwATA6_CS0Phys)} } }, |
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109 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_USBH}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwUSBHPhys)} } }, |
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110 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_AHB32PCIUSB}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwAHB32PCI_USBPhys)} } }, |
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111 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_AHB32PCIExt}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwAHB32PCI_ExtPhys)} } }, |
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112 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_DDR2Reg}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwDDR2RegPhys)} } }, |
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113 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_AHB0DMAC4}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwAHB0DMAC4Phys)} } }, |
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114 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_AHB0DMAC3}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwAHB0DMAC3Phys)} } }, |
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115 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_AHB0DMAC2}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwAHB0DMAC2Phys)} } }, |
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116 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_AHB0DMAC1}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwAHB0DMAC1Phys)} } }, |
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117 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_AHB0DMAC0}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwAHB0DMAC0Phys)} } }, |
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118 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_AHBEXDMAC}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwAHBEXDMACPhys)} } }, |
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119 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_EXBUS}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwEXBUSPhys)} } }, |
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120 |
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121 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_DTVIf}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwDTVIfPhys)} } }, |
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122 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_APB1}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwAPB1Phys)} } }, |
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123 |
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124 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_PWM7}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwPWM7Phys)} } }, |
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125 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_PWM6}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwPWM6Phys)} } }, |
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126 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_PWM5}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwPWM5Phys)} } }, |
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127 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_PWM4}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwPWM4Phys)} } }, |
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128 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_PWM3}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwPWM3Phys)} } }, |
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129 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_PWM2}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwPWM2Phys)} } }, |
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130 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_PWM1}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwPWM1Phys)} } }, |
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131 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_PWM0}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwPWM0Phys)} } }, |
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132 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_GPIO}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwGPIOPhys)} } }, |
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133 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_SYSCTRL}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwSYSCTRLPhys)} } }, |
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134 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_eWDT}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHweWDTPhys)} } }, |
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135 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_Timer5}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwTimer5Phys)} } }, |
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136 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_Timer4}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwTimer4Phys)} } }, |
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137 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_Timer3}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwTimer3Phys)} } }, |
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138 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_Timer2}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwTimer2Phys)} } }, |
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139 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_Timer1}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwTimer1Phys)} } }, |
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140 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_Timer0}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwTimer0Phys)} } }, |
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141 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_UART7}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwUART7Phys)} } }, |
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142 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_UART6}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwUART6Phys)} } }, |
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143 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_UART5}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwUART5Phys)} } }, |
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144 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_UART4}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwUART4Phys)} } }, |
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145 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_UART3}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwUART3Phys)} } }, |
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146 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_UART2}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwUART2Phys)} } }, |
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147 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_UART1}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwUART1Phys)} } }, |
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148 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_UART0}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwUART0Phys)} } }, |
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149 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_I2S3}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwI2S3Phys)} } }, |
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150 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_I2S2}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwI2S2Phys)} } }, |
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151 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_I2S1}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwI2S1Phys)} } }, |
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152 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_I2S0}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwI2S0Phys)} } }, |
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153 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_I2C}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwI2CPhys)} } }, |
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154 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_CSI1}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwCSI1Phys)} } }, |
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155 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_CSI0}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwCSI0Phys)} } }, |
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156 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_SPDIF}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwSPDIFPhys)} } }, |
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157 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_SD}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwSDPhys)} } }, |
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158 |
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159 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_FPGA}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwFPGAPhys)} } }, |
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160 |
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161 { { {KHcrCat_MHA_HWBASE, KHcrKey_HwPhys_LAN}, ETypeUInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(KHwLANPhys)} } }, |
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162 |
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163 /* |
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164 HCR Setting values for DMA logical channel identifiers. |
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165 */ |
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166 |
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167 { { {KHcrCat_MHA_DMA, KHcrKey_DmaCh_SD0}, ETypeInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(EDMAChannelSD0)} } }, |
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168 { { {KHcrCat_MHA_DMA, KHcrKey_DmaCh_SD1}, ETypeInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(EDMAChannelSD1)} } }, |
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169 |
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170 { { {KHcrCat_MHA_DMA, KHcrKey_DmaCh_I2S0RX}, ETypeInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(EDMAChannelI2S0RX)} } }, |
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171 { { {KHcrCat_MHA_DMA, KHcrKey_DmaCh_I2S0TX}, ETypeInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(EDMAChannelI2S0TX)} } }, |
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172 { { {KHcrCat_MHA_DMA, KHcrKey_DmaCh_I2S1RX}, ETypeInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(EDMAChannelI2S1RX)} } }, |
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173 { { {KHcrCat_MHA_DMA, KHcrKey_DmaCh_I2S1TX}, ETypeInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(EDMAChannelI2S1TX)} } }, |
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174 { { {KHcrCat_MHA_DMA, KHcrKey_DmaCh_I2S2RX}, ETypeInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(EDMAChannelI2S2RX)} } }, |
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175 { { {KHcrCat_MHA_DMA, KHcrKey_DmaCh_I2S2TX}, ETypeInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(EDMAChannelI2S2TX)} } }, |
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176 { { {KHcrCat_MHA_DMA, KHcrKey_DmaCh_I2S3RX}, ETypeInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(EDMAChannelI2S3RX)} } }, |
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177 { { {KHcrCat_MHA_DMA, KHcrKey_DmaCh_I2S3TX}, ETypeInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(EDMAChannelI2S3TX)} } }, |
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178 |
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179 { { {KHcrCat_MHA_DMA, KHcrKey_DmaCh_UART0RX}, ETypeInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(EDMAChannelUART0RX)} } }, |
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180 { { {KHcrCat_MHA_DMA, KHcrKey_DmaCh_UART0TX}, ETypeInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(EDMAChannelUART0TX)} } }, |
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181 { { {KHcrCat_MHA_DMA, KHcrKey_DmaCh_UART1RX}, ETypeInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(EDMAChannelUART1RX)} } }, |
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182 { { {KHcrCat_MHA_DMA, KHcrKey_DmaCh_UART1TX}, ETypeInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(EDMAChannelUART1TX)} } }, |
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183 { { {KHcrCat_MHA_DMA, KHcrKey_DmaCh_UART2RX}, ETypeInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(EDMAChannelUART2RX)} } }, |
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184 { { {KHcrCat_MHA_DMA, KHcrKey_DmaCh_UART2TX}, ETypeInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(EDMAChannelUART2TX)} } }, |
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185 |
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186 { { {KHcrCat_MHA_DMA, KHcrKey_DmaCh_MemToMem0}, ETypeInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(EDmaMemToMem0)} } }, |
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187 { { {KHcrCat_MHA_DMA, KHcrKey_DmaCh_MemToMem1}, ETypeInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(EDmaMemToMem1)} } }, |
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188 { { {KHcrCat_MHA_DMA, KHcrKey_DmaCh_MemToMem2}, ETypeInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(EDmaMemToMem2)} } }, |
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189 { { {KHcrCat_MHA_DMA, KHcrKey_DmaCh_MemToMem3}, ETypeInt32, HCR_FLAGS_NONE, HCR_LEN_NA}, { {HCR_WVALUE(EDmaMemToMem3)} } } |
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190 |
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191 // |
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192 // Last entry must not end in a ',' as it is present in the enclosing file. |
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193 // }; |
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194 |
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195 |
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196 #endif // HCR_PSL_CONFIG_ASSP_INL |
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197 |
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198 |