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1 /* |
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2 * Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies). |
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3 * All rights reserved. |
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4 * This component and the accompanying materials are made available |
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5 * under the terms of "Eclipse Public License v1.0" |
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6 * which accompanies this distribution, and is available |
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7 * at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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8 * |
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9 * Initial Contributors: |
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10 * Nokia Corporation - initial contribution. |
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11 * |
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12 * Contributors: |
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13 * |
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14 * Description: |
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15 * This file is part of the NE1_TB Variant Base Port |
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16 * Hardware Configuration Respoitory Published Setting IDs header. |
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17 * |
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18 */ |
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19 |
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20 |
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21 |
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22 /** |
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23 @file hcrconfig_assp.h |
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24 File provides const uint definitions for the published set of HCR settings |
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25 identifiers applicable to the NEC NaviEngine base port ASSP part. |
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26 |
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27 @publishedPartner |
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28 @prototype |
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29 */ |
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30 |
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31 #ifndef HCRCONFIG_ASSP_H |
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32 #define HCRCONFIG_ASSP_H |
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33 |
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34 |
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35 |
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36 |
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37 // -- INCLUDES ---------------------------------------------------------------- |
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38 |
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39 #include <drivers/hcr.h> |
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40 |
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41 |
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42 |
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43 // -- CATEGORY ---------------------------------------------------------------- |
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44 |
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45 |
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46 |
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47 // -- KEYS -------------------------------------------------------------------- |
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48 |
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49 |
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50 /** |
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51 HCR Setting Keys for ASSP Hardware Block base virtual addresses for FMM and MMM. |
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52 */ |
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53 #define HW_BASE 0x00001000 |
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54 const HCR::TElementId KHcrKey_HwBase_Uart0 = HW_BASE + 11; //< Serial port #0 |
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55 const HCR::TElementId KHcrKey_HwBase_Uart1 = HW_BASE + 12; //< Serial port #1 |
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56 const HCR::TElementId KHcrKey_HwBase_Uart2 = HW_BASE + 13; //< Serial port #2 |
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57 |
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58 const HCR::TElementId KHcrKey_HwBase_MPCorePrivate = HW_BASE + 21; //< 4KB of private MPcore region for SCU and Interrupt controller |
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59 const HCR::TElementId KHcrKey_HwBase_SCU = HW_BASE + 22; //< Snoop Control Unit |
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60 const HCR::TElementId KHcrKey_HwBase_IntIf = HW_BASE + 23; //< CPU interrupt interface |
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61 const HCR::TElementId KHcrKey_HwBase_IntDist = HW_BASE + 24; //< Global Interrupt Distributer |
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62 |
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63 const HCR::TElementId KHcrKey_HwBase_Timers = HW_BASE + 31; //< Six SoC timers |
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64 const HCR::TElementId KHcrKey_HwBase_Watchdog = HW_BASE + 32; //< eWDT (Watchdog Timer) |
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65 const HCR::TElementId KHcrKey_HwBase_SystemCtrl = HW_BASE + 33; //< System control unit |
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66 |
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67 const HCR::TElementId KHcrKey_HwBase_Display = HW_BASE + 41; //< SoC display controller |
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68 |
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69 const HCR::TElementId KHcrKey_HwBase_I2C = HW_BASE + 51; //< I2C |
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70 const HCR::TElementId KHcrKey_HwBase_I2S0 = HW_BASE + 52; //< I2S0 |
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71 const HCR::TElementId KHcrKey_HwBase_I2S1 = HW_BASE + 53; //< I2S1 |
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72 const HCR::TElementId KHcrKey_HwBase_I2S2 = HW_BASE + 54; //< I2S2 |
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73 const HCR::TElementId KHcrKey_HwBase_I2S3 = HW_BASE + 55; //< I2S3 |
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74 |
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75 const HCR::TElementId KHcrKey_HwBase_FPGA = HW_BASE + 61; //< FPGA registers |
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76 const HCR::TElementId KHcrKey_HwBase_CDDisp = HW_BASE + 62; //< LCD display |
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77 const HCR::TElementId KHcrKey_HwBase_TSP = HW_BASE + 63; //< Digitiser |
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78 |
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79 const HCR::TElementId KHcrKey_HwBase_SPDIF = HW_BASE + 64; //< SPDIF |
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80 |
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81 const HCR::TElementId KHcrKey_HwBase_CSI0 = HW_BASE + 71; //< CSI0 |
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82 const HCR::TElementId KHcrKey_HwBase_CSI1 = HW_BASE + 72; //< CSI1 |
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83 |
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84 const HCR::TElementId KHcrKey_HwBase_SDCtrl = HW_BASE + 81; //< SD |
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85 |
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86 const HCR::TElementId KHcrKey_HwBase_KDMACExBus = HW_BASE + 91; //< DMAC(4C) 4KB |
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87 const HCR::TElementId KHcrKey_HwBase_KDMAC32 = HW_BASE + 92; //< DMAC(8C) 20KB |
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88 |
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89 const HCR::TElementId KHcrKey_HwBase_Ethernet = HW_BASE + 101; //< Ethernet0 |
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90 |
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91 const HCR::TElementId KHcrKey_HwBase_GPIOBase = HW_BASE + 111; //< GPIO |
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92 |
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93 const HCR::TElementId KHcrKey_HwBase_PciBase = HW_BASE + 121; //< // PCI Bridges |
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94 const HCR::TElementId KHcrKey_HwBase_PciBridgeExtern = HW_BASE + 122; //< External PCI Bridge |
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95 const HCR::TElementId KHcrKey_HwBase_PciBridgeUsb = HW_BASE + 123; //< UsbHost dedicated PCI Bridge |
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96 |
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97 const HCR::TElementId KHcrKey_HwBase_UsbHWindow = HW_BASE + 131; //< Internal PCI window |
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98 #undef HW_BASE |
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99 |
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100 |
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101 /** |
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102 HCR Settings holding the DMA logical channel identifiers. |
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103 */ |
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104 #define DMA_CH 0x00002000 |
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105 const HCR::TElementId KHcrKey_DmaCh_SD0 = DMA_CH + 11; //< |
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106 const HCR::TElementId KHcrKey_DmaCh_SD1 = DMA_CH + 12; //< |
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107 |
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108 const HCR::TElementId KHcrKey_DmaCh_I2S0RX = DMA_CH + 21; //< |
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109 const HCR::TElementId KHcrKey_DmaCh_I2S0TX = DMA_CH + 22; //< |
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110 const HCR::TElementId KHcrKey_DmaCh_I2S1RX = DMA_CH + 23; //< |
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111 const HCR::TElementId KHcrKey_DmaCh_I2S1TX = DMA_CH + 24; //< |
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112 const HCR::TElementId KHcrKey_DmaCh_I2S2RX = DMA_CH + 25; //< |
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113 const HCR::TElementId KHcrKey_DmaCh_I2S2TX = DMA_CH + 26; //< |
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114 const HCR::TElementId KHcrKey_DmaCh_I2S3RX = DMA_CH + 27; //< |
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115 const HCR::TElementId KHcrKey_DmaCh_I2S3TX = DMA_CH + 28; //< |
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116 |
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117 const HCR::TElementId KHcrKey_DmaCh_UART0RX = DMA_CH + 41; //< |
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118 const HCR::TElementId KHcrKey_DmaCh_UART0TX = DMA_CH + 42; //< |
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119 const HCR::TElementId KHcrKey_DmaCh_UART1RX = DMA_CH + 43; //< |
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120 const HCR::TElementId KHcrKey_DmaCh_UART1TX = DMA_CH + 44; //< |
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121 const HCR::TElementId KHcrKey_DmaCh_UART2RX = DMA_CH + 45; //< |
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122 const HCR::TElementId KHcrKey_DmaCh_UART2TX = DMA_CH + 46; //< |
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123 |
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124 const HCR::TElementId KHcrKey_DmaCh_MemToMem0 = DMA_CH + 61; //< |
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125 const HCR::TElementId KHcrKey_DmaCh_MemToMem1 = DMA_CH + 62; //< |
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126 const HCR::TElementId KHcrKey_DmaCh_MemToMem2 = DMA_CH + 63; //< |
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127 const HCR::TElementId KHcrKey_DmaCh_MemToMem3 = DMA_CH + 64; //< |
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128 #undef DMA_CH |
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129 |
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130 /** |
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131 HCR Settings holding the memory map physical addresses identifiers. |
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132 */ |
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133 #define HW_PHYS 0x00003000 |
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134 const HCR::TElementId KHcrKey_HwPhys_BaseMPcorePrivate = HW_PHYS + 11; //< |
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135 const HCR::TElementId KHcrKey_HwPhys_DDR2RamBase = HW_PHYS + 12; //< |
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136 const HCR::TElementId KHcrKey_HwPhys_PCI = HW_PHYS + 13; //< |
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137 const HCR::TElementId KHcrKey_HwPhys_Internal = HW_PHYS + 14; //< |
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138 |
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139 const HCR::TElementId KHcrKey_HwPhys_AXI64IC2 = HW_PHYS + 21; //< |
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140 const HCR::TElementId KHcrKey_HwPhys_SATA = HW_PHYS + 22; //< |
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141 const HCR::TElementId KHcrKey_HwPhys_AXI64DMAC = HW_PHYS + 23; //< |
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142 const HCR::TElementId KHcrKey_HwPhys_Video = HW_PHYS + 24; //< |
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143 const HCR::TElementId KHcrKey_HwPhys_Disp = HW_PHYS + 25; //< |
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144 const HCR::TElementId KHcrKey_HwPhys_SGX = HW_PHYS + 26; //< |
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145 |
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146 const HCR::TElementId KHcrKey_HwPhys_CFWindow2 = HW_PHYS + 31; //< |
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147 const HCR::TElementId KHcrKey_HwPhys_CFWindow1 = HW_PHYS + 32; //< |
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148 const HCR::TElementId KHcrKey_HwPhys_CFWindow0 = HW_PHYS + 33; //< |
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149 const HCR::TElementId KHcrKey_HwPhys_ATA6CS1 = HW_PHYS + 34; //< |
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150 const HCR::TElementId KHcrKey_HwPhys_ATA6CS0 = HW_PHYS + 35; //< |
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151 const HCR::TElementId KHcrKey_HwPhys_USBH = HW_PHYS + 36; //< |
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152 const HCR::TElementId KHcrKey_HwPhys_AHB32PCIUSB = HW_PHYS + 37; //< |
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153 const HCR::TElementId KHcrKey_HwPhys_AHB32PCIExt = HW_PHYS + 38; //< |
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154 const HCR::TElementId KHcrKey_HwPhys_DDR2Reg = HW_PHYS + 39; //< |
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155 const HCR::TElementId KHcrKey_HwPhys_AHB0DMAC4 = HW_PHYS + 40; //< |
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156 const HCR::TElementId KHcrKey_HwPhys_AHB0DMAC3 = HW_PHYS + 41; //< |
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157 const HCR::TElementId KHcrKey_HwPhys_AHB0DMAC2 = HW_PHYS + 42; //< |
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158 const HCR::TElementId KHcrKey_HwPhys_AHB0DMAC1 = HW_PHYS + 43; //< |
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159 const HCR::TElementId KHcrKey_HwPhys_AHB0DMAC0 = HW_PHYS + 44; //< |
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160 const HCR::TElementId KHcrKey_HwPhys_AHBEXDMAC = HW_PHYS + 45; //< |
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161 const HCR::TElementId KHcrKey_HwPhys_EXBUS = HW_PHYS + 46; //< |
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162 |
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163 const HCR::TElementId KHcrKey_HwPhys_DTVIf = HW_PHYS + 50; //< |
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164 const HCR::TElementId KHcrKey_HwPhys_APB1 = HW_PHYS + 51; //< |
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165 |
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166 const HCR::TElementId KHcrKey_HwPhys_PWM7 = HW_PHYS + 60; //< |
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167 const HCR::TElementId KHcrKey_HwPhys_PWM6 = HW_PHYS + 61; //< |
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168 const HCR::TElementId KHcrKey_HwPhys_PWM5 = HW_PHYS + 62; //< |
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169 const HCR::TElementId KHcrKey_HwPhys_PWM4 = HW_PHYS + 63; //< |
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170 const HCR::TElementId KHcrKey_HwPhys_PWM3 = HW_PHYS + 64; //< |
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171 const HCR::TElementId KHcrKey_HwPhys_PWM2 = HW_PHYS + 65; //< |
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172 const HCR::TElementId KHcrKey_HwPhys_PWM1 = HW_PHYS + 66; //< |
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173 const HCR::TElementId KHcrKey_HwPhys_PWM0 = HW_PHYS + 67; //< |
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174 const HCR::TElementId KHcrKey_HwPhys_GPIO = HW_PHYS + 68; //< |
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175 const HCR::TElementId KHcrKey_HwPhys_SYSCTRL = HW_PHYS + 69; //< |
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176 const HCR::TElementId KHcrKey_HwPhys_eWDT = HW_PHYS + 70; //< |
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177 const HCR::TElementId KHcrKey_HwPhys_Timer5 = HW_PHYS + 71; //< |
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178 const HCR::TElementId KHcrKey_HwPhys_Timer4 = HW_PHYS + 72; //< |
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179 const HCR::TElementId KHcrKey_HwPhys_Timer3 = HW_PHYS + 73; //< |
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180 const HCR::TElementId KHcrKey_HwPhys_Timer2 = HW_PHYS + 74; //< |
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181 const HCR::TElementId KHcrKey_HwPhys_Timer1 = HW_PHYS + 75; //< |
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182 const HCR::TElementId KHcrKey_HwPhys_Timer0 = HW_PHYS + 76; //< |
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183 const HCR::TElementId KHcrKey_HwPhys_UART7 = HW_PHYS + 77; //< |
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184 const HCR::TElementId KHcrKey_HwPhys_UART6 = HW_PHYS + 78; //< |
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185 const HCR::TElementId KHcrKey_HwPhys_UART5 = HW_PHYS + 79; //< |
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186 const HCR::TElementId KHcrKey_HwPhys_UART4 = HW_PHYS + 80; //< |
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187 const HCR::TElementId KHcrKey_HwPhys_UART3 = HW_PHYS + 81; //< |
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188 const HCR::TElementId KHcrKey_HwPhys_UART2 = HW_PHYS + 82; //< |
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189 const HCR::TElementId KHcrKey_HwPhys_UART1 = HW_PHYS + 83; //< |
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190 const HCR::TElementId KHcrKey_HwPhys_UART0 = HW_PHYS + 84; //< |
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191 const HCR::TElementId KHcrKey_HwPhys_I2S3 = HW_PHYS + 85; //< |
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192 const HCR::TElementId KHcrKey_HwPhys_I2S2 = HW_PHYS + 86; //< |
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193 const HCR::TElementId KHcrKey_HwPhys_I2S1 = HW_PHYS + 87; //< |
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194 const HCR::TElementId KHcrKey_HwPhys_I2S0 = HW_PHYS + 88; //< |
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195 const HCR::TElementId KHcrKey_HwPhys_I2C = HW_PHYS + 89; //< |
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196 const HCR::TElementId KHcrKey_HwPhys_CSI1 = HW_PHYS + 90; //< |
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197 const HCR::TElementId KHcrKey_HwPhys_CSI0 = HW_PHYS + 91; //< |
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198 const HCR::TElementId KHcrKey_HwPhys_SPDIF = HW_PHYS + 92; //< |
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199 const HCR::TElementId KHcrKey_HwPhys_SD = HW_PHYS + 93; //< |
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200 |
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201 const HCR::TElementId KHcrKey_HwPhys_FPGA = HW_PHYS + 100; //< |
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202 |
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203 |
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204 const HCR::TElementId KHcrKey_HwPhys_LAN = HW_PHYS + 110; //< |
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205 #undef HW_PHYS |
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206 |
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207 #endif // HCRCONFIG_ASSP_H |