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1 /* |
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2 * Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies). |
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3 * All rights reserved. |
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4 * This component and the accompanying materials are made available |
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5 * under the terms of "Eclipse Public License v1.0" |
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6 * which accompanies this distribution, and is available |
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7 * at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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8 * |
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9 * Initial Contributors: |
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10 * Nokia Corporation - initial contribution. |
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11 * |
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12 * Contributors: |
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13 * |
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14 * Description: |
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15 * bsp\nwip_nec_naviengine\naviengine_assp\i2s\i2s_psl.cpp |
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16 * |
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17 */ |
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18 |
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19 |
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20 |
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21 #include "navi_i2s.h" |
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22 #include <naviengine.h> |
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23 |
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24 #ifdef __SMP__ |
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25 static TSpinLock I2sLock = TSpinLock(TSpinLock::EOrderGenericIrqLow2); |
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26 #endif |
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27 |
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28 // All channels have the same configuration. |
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29 // base for registers are shifted for each channel by 0x400 (1<<10) |
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30 #define HW_CHAN_SHIFT 10 |
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31 |
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32 // Registers |
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33 // these macros will return register address for a given interface |
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34 #define KHwI2SControl(intefaceId) ((KHwBaseI2S0 + KHoI2SCtrl) + (intefaceId << HW_CHAN_SHIFT)) |
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35 #define KHwI2SFifoControl(intefaceId) ((KHwBaseI2S0 + KHoI2SFifoCtrl) + (intefaceId << HW_CHAN_SHIFT)) |
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36 #define KHwI2SFifoStatus(intefaceId) ((KHwBaseI2S0 + KHoI2SFifoSts) + (intefaceId << HW_CHAN_SHIFT)) |
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37 #define KHwI2SInterruptFlag(intefaceId) ((KHwBaseI2S0 + KHoI2SIntFlg) + (intefaceId << HW_CHAN_SHIFT)) |
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38 #define KHwI2SInterruptMask(intefaceId) ((KHwBaseI2S0 + KHoI2SIntMask) + (intefaceId << HW_CHAN_SHIFT)) |
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39 #define KHwI2SDataIn(intefaceId) ((KHwBaseI2S0 + KHoI2SRx) + (intefaceId << HW_CHAN_SHIFT)) |
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40 #define KHwI2SDataOut(intefaceId) ((KHwBaseI2S0 + KHoI2STx) + (intefaceId << HW_CHAN_SHIFT)) |
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41 |
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42 #define AsspIsBitSet(addr, bit) (AsspRegister::Read32(addr)& (bit)) |
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43 #define CLEARMASK(shift,len) (((1 << len) - 1) << shift) |
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44 #define AsspGetBits(w,shift,len) ((AsspRegister::Read32(w) >> shift) & ((1 << (len)) - 1)) |
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45 #define AsspSetBits(w,set,shift,len) (AsspRegister::Modify32(w, (CLEARMASK(shift, len)) , (set << shift))) |
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46 |
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47 |
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48 NONSHARABLE_CLASS(D2sChannelNE1_TB) : public DI2sChannelBase |
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49 { |
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50 public: |
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51 D2sChannelNE1_TB(TInt aInterfaceId); |
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52 |
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53 virtual TInt ConfigureInterface(TDes8* aConfig); |
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54 virtual TInt GetInterfaceConfiguration(TDes8& aConfig); |
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55 virtual TInt SetSamplingRate(TInt aSamplingRate); |
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56 virtual TInt GetSamplingRate(TInt& aSamplingRate); |
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57 virtual TInt SetFrameLengthAndFormat(TInt aFrameLength, TInt aLeftFramePhaseLength); |
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58 virtual TInt GetFrameFormat(TInt& aLeftFramePhaseLength, TInt& aRightFramePhaseLength); |
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59 virtual TInt SetSampleLength(TInt aFramePhase, TInt aSampleLength); |
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60 virtual TInt GetSampleLength(TInt aFramePhase, TInt& aSampleLength); |
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61 virtual TInt SetDelayCycles(TInt aFramePhase, TInt aDelayCycles); |
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62 virtual TInt GetDelayCycles(TInt aFramePhase, TInt& aDelayCycles); |
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63 virtual TInt ReadReceiveRegister(TInt aFramePhase, TInt& aData); |
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64 virtual TInt WriteTransmitRegister(TInt aFramePhase, TInt aData); |
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65 virtual TInt ReadTransmitRegister(TInt aFramePhase, TInt& aData); |
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66 virtual TInt ReadRegisterModeStatus(TInt aFramePhase, TInt& aFlags); |
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67 virtual TInt EnableRegisterInterrupts(TInt aFramePhase, TInt aInterrupt); |
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68 virtual TInt DisableRegisterInterrupts(TInt aFramePhase, TInt aInterrupt); |
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69 virtual TInt IsRegisterInterruptEnabled(TInt aFramePhase, TInt& aEnabled); |
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70 virtual TInt EnableFIFO(TInt aFramePhase, TInt aFifoMask); |
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71 virtual TInt DisableFIFO(TInt aFramePhase, TInt aFifoMask); |
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72 virtual TInt IsFIFOEnabled(TInt aFramePhase, TInt& aEnabled); |
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73 virtual TInt SetFIFOThreshold(TInt aFramePhase, TInt aDirection, TInt aThreshold); |
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74 virtual TInt ReadFIFOModeStatus(TInt aFramePhase, TInt& aFlags); |
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75 virtual TInt EnableFIFOInterrupts(TInt aFramePhase, TInt aInterrupt); |
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76 virtual TInt DisableFIFOInterrupts(TInt aFramePhase, TInt aInterrupt); |
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77 virtual TInt IsFIFOInterruptEnabled(TInt aFramePhase, TInt& aEnabled); |
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78 virtual TInt ReadFIFOLevel(TInt aFramePhase, TInt aDirection, TInt& aLevel); |
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79 virtual TInt EnableDMA(TInt aFifoMask); |
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80 virtual TInt DisableDMA(TInt aFifoMask); |
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81 virtual TInt IsDMAEnabled(TInt& aEnabled); |
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82 virtual TInt Start(TInt aDirection); |
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83 virtual TInt Stop(TInt aDirection); |
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84 virtual TInt IsStarted(TInt aDirection, TBool& aStarted); |
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85 |
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86 private: |
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87 TBool iConfigured; |
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88 TInt iLastPhaseInWriteFifo; |
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89 TInt iLastPhaseInReadFifo; |
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90 }; |
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91 |
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92 // this static method, creates the DI2sChannelBase corresponding |
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93 // to the interfaceId passed and return the channel |
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94 // NB: if each channel was implemented independently (e.g. on a separate file) |
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95 // this function would have to be provided spearately and know how to map |
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96 // the interface ID to the appropriate channel object to be created |
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97 // (e.g. each channel would have a different implementation D2sChannelXXX |
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98 // and this function call the appropriate constructor for each interface Id) |
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99 |
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100 TInt DI2sChannelBase::CreateChannels(DI2sChannelBase*& aChannel, TInt aInterfaceId) |
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101 { |
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102 DI2sChannelBase* chan = new D2sChannelNE1_TB(aInterfaceId); |
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103 if (!chan) |
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104 { |
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105 return KErrNoMemory; |
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106 } |
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107 |
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108 aChannel = chan; |
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109 |
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110 return KErrNone; |
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111 } |
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112 |
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113 |
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114 // Default constructor. |
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115 D2sChannelNE1_TB::D2sChannelNE1_TB(TInt aInterfaceId): |
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116 iConfigured(EFalse), |
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117 iLastPhaseInWriteFifo(I2s::ERight), // the first phase in write fifo should be left, so initialize to right |
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118 iLastPhaseInReadFifo(I2s::ERight) // the first phase in read fifo should be left, so initialize to right |
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119 { |
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120 iInterfaceId=aInterfaceId; |
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121 } |
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122 |
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123 TInt D2sChannelNE1_TB::ConfigureInterface(TDes8 *aConfig) |
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124 { |
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125 __KTRACE_OPT(KDLL, Kern::Printf("DI2sChannelNE1_TB::ConfigureInterfaceInterface (Id: %d)", iInterfaceId)); |
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126 |
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127 if(AsspIsBitSet(KHwI2SControl(iInterfaceId), KHtI2SCtrl_TEN | KHtI2SCtrl_REN)) |
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128 { |
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129 return KErrInUse; |
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130 } |
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131 |
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132 TI2sConfigBufV01 &conf = ((TI2sConfigBufV01&)*aConfig); |
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133 |
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134 // this interface doesn's support EController mode |
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135 if (conf().iType == I2s::EController) |
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136 { |
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137 return KErrNotSupported; |
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138 } |
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139 |
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140 if(conf().iRole == I2s::EMaster) |
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141 { |
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142 AsspRegister::Modify32(KHwI2SControl(iInterfaceId), 0, KHtI2SCtrl_MSMODE); |
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143 } |
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144 |
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145 // copy configuration.. it will be used in Start/Stop |
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146 iConfig = conf(); // ok, thread context only and one client thread per channel |
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147 |
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148 // select I2S format |
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149 AsspSetBits(KHwI2SControl(iInterfaceId), 4, KHsI2SCtrl_FORMAT, 3); |
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150 |
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151 iConfigured = ETrue; // this API can only be called in thread context and we assume that a channel is for use of a single thread |
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152 |
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153 return KErrNone; |
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154 } |
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155 |
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156 TInt D2sChannelNE1_TB::GetInterfaceConfiguration(TDes8 &aConfig) |
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157 { |
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158 if (!iConfigured) // this API can only be called in thread context and we assume that a channel is for use of a single thread |
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159 { |
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160 aConfig.SetLength(0); //no configuration present yet.. |
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161 } |
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162 else |
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163 { |
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164 TPckgBuf<TI2sConfigV01> conf(iConfig); |
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165 aConfig.Copy(conf); |
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166 } |
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167 return KErrNone; |
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168 } |
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169 |
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170 TInt D2sChannelNE1_TB::SetSamplingRate(TInt aSamplingRate) |
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171 { |
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172 if (iConfig.iRole == I2s::ESlave) |
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173 { |
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174 return KErrNotSupported; |
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175 } |
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176 |
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177 if (AsspIsBitSet(KHwI2SControl(iInterfaceId), KHtI2SCtrl_TEN | KHtI2SCtrl_REN)) |
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178 { |
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179 return KErrInUse; |
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180 } |
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181 |
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182 TUint32 val = 0, div = 0; |
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183 |
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184 switch(aSamplingRate) |
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185 { |
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186 case I2s::E8KHz: // 0000: 8 kHz |
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187 div = 1; // MCLK = 24.5760 MHz(1*) |
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188 break; |
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189 |
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190 case I2s::E11_025KHz: // 1000: 11.025 kHz |
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191 val = 8; |
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192 div = 4; // MCLK = 33.8688 MHz(4*) or 22.5792(5*) or 16.9344 MHz(6) |
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193 break; |
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194 |
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195 case I2s::E12KHz: // 0001: 12 kHz |
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196 val = 1; |
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197 div = 1; // MCLK = 24.5760 MHz(1*) or 18.432MHz(2) |
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198 break; |
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199 |
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200 case I2s::E16KHz: // 0010: 16 kHz |
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201 val = 2; |
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202 div = 1; // MCLK = 24.5760 MHz(1*) |
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203 break; |
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204 |
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205 case I2s::E22_05KHz: // 1001: 22.05 kHz |
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206 val = 9; |
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207 div = 4; // MCLK = 33.8688 MHz(4*) or 22.5792(5*) or 16.9344 MHz(6) |
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208 break; |
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209 |
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210 case I2s::E24KHz: // 0011: 24 kHz |
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211 val = 3; |
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212 div = 1; // MCLK = 24.5760 MHz(1*) or 18.432MHz(2) |
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213 break; |
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214 |
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215 case I2s::E32KHz: // 0100: 32 kHz |
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216 val = 4; |
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217 div = 1; // MCLK = 24.5760 MHz |
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218 break; |
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219 |
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220 case I2s::E44_1KHz: // 1010: 44.1 kHz |
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221 val = 10; |
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222 div = 4; // MCLK = 33.8688 MHz(4*) or 22.5792(5*) or 16.9344 MHz(6) |
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223 break; |
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224 |
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225 case I2s::E48KHz: // 0101: 48 kHz |
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226 val = 5; |
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227 div = 2; // MCLK = 24.5760 MHz(1*) or 18.432MHz(2) |
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228 break; |
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229 |
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230 default: |
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231 return KErrNotSupported; |
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232 } |
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233 |
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234 TInt irq=__SPIN_LOCK_IRQSAVE(I2sLock); // seems that we must guarantee the following sequence is uninterrupted... |
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235 // before changing FSCLKSEL and/or FSMODE - mask I2S bit |
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236 // MSK_I2Sx (x=0:3): bits 18:21 in MaskCtrl Register of the System Ctrl Unit |
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237 AsspRegister::Modify32(KHwBaseSCU + KHoSCUClockMaskCtrl, 0, (1<<iInterfaceId)<<18); |
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238 |
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239 // change the divide I2SCLK ctrl value for this channel.. |
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240 AsspRegister::Modify32(KHwSystemCtrlBase+KHoSCUDivideI2SCLKCtrl, 0xf<<(iInterfaceId<<3), div<<(iInterfaceId<<3)); |
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241 |
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242 // update the KHwI2SControl register |
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243 AsspSetBits(KHwI2SControl(iInterfaceId), val, KHsI2SCtrl_FCKLKSEL, 4); |
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244 |
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245 // after changing FSCLKSEL and FSMODE - clear MSK_I2Sx mask bit |
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246 AsspRegister::Modify32(KHwBaseSCU + KHoSCUClockMaskCtrl, (1<<iInterfaceId)<<18, 0); |
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247 __SPIN_UNLOCK_IRQRESTORE(I2sLock,irq); |
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248 |
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249 return KErrNone; |
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250 } |
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251 |
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252 TInt D2sChannelNE1_TB::GetSamplingRate(TInt& aSamplingRate) |
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253 { |
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254 if (iConfig.iRole == I2s::ESlave) |
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255 { |
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256 return KErrNotSupported; |
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257 } |
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258 |
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259 TUint32 val = (AsspRegister::Read32(KHwI2SControl(iInterfaceId))>>KHsI2SCtrl_FCKLKSEL) & 0xf; |
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260 |
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261 switch(val) |
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262 { |
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263 case 0: |
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264 aSamplingRate = I2s::E8KHz; // 0000: 8 kHz |
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265 break; |
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266 |
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267 case 8: |
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268 aSamplingRate = I2s::E11_025KHz; // 1000: 11.025 kHz |
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269 break; |
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270 |
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271 case 1: |
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272 aSamplingRate = I2s::E12KHz; // 0001: 12 kHz |
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273 break; |
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274 |
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275 case 2: |
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276 aSamplingRate = I2s::E16KHz; // 0010: 16 kHz |
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277 break; |
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278 |
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279 case 9: |
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280 aSamplingRate = I2s::E22_05KHz; // 1001: 22.05 kHz |
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281 break; |
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282 |
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283 case 3: |
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284 aSamplingRate = I2s::E24KHz; // 0011: 24 kHz |
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285 break; |
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286 |
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287 case 4: |
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288 aSamplingRate = I2s::E32KHz; // 0100: 32 kHz |
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289 break; |
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290 |
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291 case 10: |
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292 aSamplingRate = I2s::E44_1KHz; // 1010: 44.1 kHz |
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293 break; |
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294 |
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295 case 5: |
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296 aSamplingRate = I2s::E48KHz; // 0101: 48 kHz |
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297 break; |
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298 } |
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299 |
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300 return KErrNone; |
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301 } |
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302 |
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303 TInt D2sChannelNE1_TB::SetFrameLengthAndFormat(TInt aFrameLength, TInt /*aLeftFramePhaseLength*/) |
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304 { |
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305 if (AsspIsBitSet(KHwI2SControl(iInterfaceId), KHtI2SCtrl_TEN | KHtI2SCtrl_REN)) |
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306 { |
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307 return KErrInUse; |
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308 } |
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309 |
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310 TUint32 val=0; |
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311 |
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312 switch(aFrameLength) |
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313 { |
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314 case I2s::EFrame32Bit: |
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315 val = 0; |
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316 break; |
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317 |
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318 case I2s::EFrame48Bit: |
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319 val = 1; |
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320 break; |
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321 |
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322 case I2s::EFrame64Bit: |
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323 val = 2; |
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324 break; |
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325 |
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326 case I2s::EFrame128Bit: |
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327 val = 3; |
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328 break; |
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329 |
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330 default: |
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331 return KErrNotSupported; |
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332 }; |
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333 |
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334 TInt irq=__SPIN_LOCK_IRQSAVE(I2sLock); // seems that we must guarantee the following sequence is uninterrupted |
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335 // before changing FSCLKSEL and/or FSMODE - mask I2S bit |
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336 // MSK_I2Sx (x=0:3): bits 18:21 in MaskCtrl Register of the System Ctrl Unit |
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337 AsspRegister::Modify32(KHwBaseSCU + KHoSCUClockMaskCtrl, 0, (1<<iInterfaceId)<<18); |
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338 |
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339 // update the register (3 bits at KHsI2SCtrl_FSMODE) |
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340 AsspSetBits(KHwI2SControl(iInterfaceId), val, KHsI2SCtrl_FSMODE, 3); |
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341 |
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342 // after changing FSCLKSEL and FSMODE - clear MSK_I2Sx mask bit |
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343 AsspRegister::Modify32(KHwBaseSCU + KHoSCUClockMaskCtrl, (1<<iInterfaceId)<<18, 0); |
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344 __SPIN_UNLOCK_IRQRESTORE(I2sLock,irq); |
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345 |
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346 return KErrNone; |
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347 } |
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348 |
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349 TInt D2sChannelNE1_TB::GetFrameFormat(TInt& aLeftFramePhaseLength, TInt& aRightFramePhaseLength) |
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350 { |
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351 TInt frameLength=0; |
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352 switch(AsspGetBits(KHwI2SControl(iInterfaceId), KHsI2SCtrl_FSMODE, 3)) |
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353 { |
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354 case 0: |
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355 frameLength = I2s::EFrame32Bit; |
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356 break; |
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357 |
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358 case 1: |
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359 frameLength = I2s::EFrame48Bit; |
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360 break; |
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361 |
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362 case 2: |
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363 frameLength = I2s::EFrame64Bit; |
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364 break; |
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365 |
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366 case 3: |
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367 frameLength = I2s::EFrame128Bit; |
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368 break; |
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369 |
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370 default: |
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371 return KErrGeneral; //unexpected value?? |
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372 }; |
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373 |
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374 aLeftFramePhaseLength=aRightFramePhaseLength=frameLength/2; // on NaviEngine frames are symmetrical |
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375 |
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376 return KErrNone; |
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377 } |
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378 |
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379 TInt D2sChannelNE1_TB::SetSampleLength(TInt /*aFramePhase*/, TInt aSampleLength) |
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380 { |
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381 if (AsspIsBitSet(KHwI2SControl(iInterfaceId), KHtI2SCtrl_TEN | KHtI2SCtrl_REN)) |
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382 { |
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383 return KErrInUse; |
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384 } |
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385 |
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386 TUint32 val=0; |
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387 |
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388 switch(aSampleLength) |
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389 { |
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390 case I2s::ESample8Bit: |
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391 val = 0x8; |
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392 break; |
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393 |
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394 case I2s::ESample16Bit: |
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395 val = 0x10; |
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396 break; |
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397 |
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398 case I2s::ESample24Bit: |
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399 val = 0x18; |
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400 break; |
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401 |
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402 case I2s::ESample12Bit: |
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403 case I2s::ESample32Bit: |
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404 return KErrNotSupported; |
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405 } |
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406 |
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407 // update the register.. |
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408 AsspSetBits(KHwI2SControl(iInterfaceId), val, KHsI2SCtrl_DLENGTH,5); // [4:0] sampling data length); |
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409 |
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410 return KErrNone; |
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411 } |
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412 |
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413 TInt D2sChannelNE1_TB::GetSampleLength(TInt /*aFramePhase*/, TInt& aSampleLength) |
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414 { |
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415 // sample length can't be configured separately for left/right channels.. |
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416 // .. in this chip, so aFramePhase is ignored |
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417 |
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418 TUint32 val=AsspRegister::Read32(KHwI2SControl(iInterfaceId)) & 0x1F; |
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419 |
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420 switch(val) |
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421 { |
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422 case 0x8: |
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423 aSampleLength = I2s::ESample8Bit; |
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424 break; |
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425 |
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426 case 0x10: |
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427 aSampleLength = I2s::ESample16Bit; |
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428 break; |
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429 |
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430 case 0x18: |
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431 aSampleLength = I2s::ESample24Bit; |
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432 break; |
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433 } |
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434 |
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435 return KErrNone; |
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436 } |
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437 |
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438 TInt D2sChannelNE1_TB::SetDelayCycles(TInt aFramePhase, TInt aDelayCycles) |
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439 { |
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440 return KErrNotSupported; |
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441 } |
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442 |
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443 TInt D2sChannelNE1_TB::GetDelayCycles(TInt aFramePhase, TInt& aDelayCycles) |
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444 { |
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445 return KErrNotSupported; |
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446 } |
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447 |
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448 TInt D2sChannelNE1_TB::ReadReceiveRegister(TInt aFramePhase, TInt& aData) |
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449 { |
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450 // should check here, if sample length was configured, |
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451 // but once the interface is properly configured, this check would add unnecessary overhead. |
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452 |
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453 // since there is only one fifo for both channels in this chip, |
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454 // we need to read Left and then Right channel data in sequence. |
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455 |
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456 TInt oldFP=__e32_atomic_swp_ord32(&iLastPhaseInReadFifo,aFramePhase); // atomic as this may be used in ISR too |
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457 if(aFramePhase == oldFP) |
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458 { |
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459 return KErrNotSupported; |
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460 } |
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461 |
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462 // and get the current data from the fifo register |
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463 aData = AsspRegister::Read32(KHwI2SDataIn(iInterfaceId)); |
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464 return KErrNone; |
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465 } |
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466 |
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467 TInt D2sChannelNE1_TB::WriteTransmitRegister(TInt aFramePhase, TInt aData) |
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468 { |
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469 // should check here, if sample length was configured, |
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470 // but once the interface is properly configured, this check would add unnecessary overhead. |
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471 |
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472 // since there is only one fifo for both channels in this chip, |
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473 // we need to write Left and then right channel data in sequence. |
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474 |
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475 TInt oldFP=__e32_atomic_swp_ord32(&iLastPhaseInWriteFifo,aFramePhase); // atomic as this may be used in ISR too |
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476 if(aFramePhase == oldFP) |
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477 { |
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478 return KErrNotSupported; |
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479 } |
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480 |
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481 // and update the fifo register |
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482 AsspRegister::Write32(KHwI2SDataOut(iInterfaceId), aData); |
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483 |
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484 return KErrNone; |
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485 } |
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486 |
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487 TInt D2sChannelNE1_TB::ReadTransmitRegister(TInt aFramePhase, TInt& aData) |
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488 { |
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489 // since there is only one fifo for both channels in this chip, |
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490 // we can only read the data for the last written phase (either left or right) |
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491 |
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492 TInt curFp=__e32_atomic_load_acq32(&iLastPhaseInWriteFifo); |
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493 if(aFramePhase != curFp) |
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494 { |
|
495 return KErrArgument; |
|
496 } |
|
497 |
|
498 // read the register |
|
499 aData = AsspRegister::Read32(KHwI2SDataOut(iInterfaceId)); |
|
500 |
|
501 return KErrNone; |
|
502 } |
|
503 |
|
504 TInt D2sChannelNE1_TB::ReadRegisterModeStatus(TInt aFramePhase, TInt& aFlags) |
|
505 { |
|
506 return KErrNotSupported; // register PIO mode not supported (FIFO always present) |
|
507 } |
|
508 |
|
509 TInt D2sChannelNE1_TB::EnableRegisterInterrupts(TInt aFramePhase, TInt aInterrupt) |
|
510 { |
|
511 return KErrNotSupported; // register PIO mode not supported (FIFO always present) |
|
512 } |
|
513 |
|
514 TInt D2sChannelNE1_TB::DisableRegisterInterrupts(TInt aFramePhase, TInt aInterrupt) |
|
515 { |
|
516 return KErrNotSupported; // register PIO mode not supported (FIFO always present) |
|
517 } |
|
518 |
|
519 TInt D2sChannelNE1_TB::IsRegisterInterruptEnabled(TInt aFramePhase, TInt& aEnabled) |
|
520 { |
|
521 return KErrNotSupported; // register PIO mode not supported (FIFO always present) |
|
522 } |
|
523 |
|
524 TInt D2sChannelNE1_TB::EnableFIFO(TInt /*aFramePhase*/, TInt aFifoMask) |
|
525 { |
|
526 TInt val=0; |
|
527 |
|
528 // Set and clear fifo init bits for transmit/receive |
|
529 // tere are only two FIFOs - not separated to phases.. |
|
530 if(aFifoMask & I2s::ETx) |
|
531 val = KHtI2SFifoCtrl_TFIFOCLR; |
|
532 |
|
533 if(aFifoMask & I2s::ERx) |
|
534 val |= KHtI2SFifoCtrl_RFIFOCLR; |
|
535 |
|
536 AsspRegister::Modify32(KHwI2SFifoControl(iInterfaceId), 0, val); |
|
537 AsspRegister::Modify32(KHwI2SFifoControl(iInterfaceId), val, 0); |
|
538 |
|
539 return KErrNone; |
|
540 } |
|
541 |
|
542 TInt D2sChannelNE1_TB::DisableFIFO(TInt aFramePhase, TInt aFifoMask) |
|
543 { |
|
544 // fifo is always enabled in this chip.. |
|
545 return KErrNotSupported; |
|
546 } |
|
547 |
|
548 TInt D2sChannelNE1_TB::IsFIFOEnabled(TInt /*aFramePhase*/, TInt& aEnabled) |
|
549 { |
|
550 // fifo is always enabled in this chip.. |
|
551 aEnabled = I2s::ERx|I2s::ETx; |
|
552 return KErrNone; |
|
553 } |
|
554 |
|
555 TInt D2sChannelNE1_TB::SetFIFOThreshold(TInt aFramePhase, TInt aDirection, TInt aThreshold) |
|
556 { |
|
557 // supported threshold values for this chip: |
|
558 // 011b - 16-word space available |
|
559 // 010b - 8-word space available |
|
560 // 001b - 4-word space available |
|
561 // 000b - 2-word space available |
|
562 if (aThreshold < 0) |
|
563 { |
|
564 return KErrNotSupported; |
|
565 } |
|
566 |
|
567 // Determine, what value was specified, and adjust it down to one |
|
568 // of the possible values |
|
569 TInt i=15; |
|
570 while(i>1) |
|
571 { |
|
572 if ( aThreshold!=(aThreshold & i)) |
|
573 break; |
|
574 i>>=1; |
|
575 } |
|
576 aThreshold = i+1; //this will now contain one of possible values (2-16); |
|
577 |
|
578 // now any of 16/8/4/2, shifted right until == 0 will give us requested register_value+2 |
|
579 // (instead of using 'switch(aThreshold)') |
|
580 i=0; |
|
581 while(aThreshold) |
|
582 { |
|
583 aThreshold>>=1; |
|
584 ++i; |
|
585 } |
|
586 aThreshold = i-2 >= 0 ? i-2 : 0; //if i-2 gives <0 (e.g.for aThreshold<4) -adjust to 0; |
|
587 |
|
588 if (AsspIsBitSet(KHwI2SControl(iInterfaceId), KHtI2SCtrl_TEN | KHtI2SCtrl_REN)) |
|
589 { |
|
590 return KErrInUse; |
|
591 } |
|
592 |
|
593 TUint32 clr, set; |
|
594 if(aDirection & I2s::ERx) // receive fifo.. |
|
595 { |
|
596 if (aFramePhase == I2s::ELeft) |
|
597 { |
|
598 clr = CLEARMASK(KHsI2SFifoCtrl_RFIFOLT, 3); |
|
599 set = (aThreshold << KHsI2SFifoCtrl_RFIFOLT); |
|
600 } |
|
601 |
|
602 else //if (aFramePhase == I2s::ERight) |
|
603 { |
|
604 clr = CLEARMASK(KHsI2SFifoCtrl_RFIFORT, 3); |
|
605 set = (aThreshold << KHsI2SFifoCtrl_RFIFORT); |
|
606 } |
|
607 } |
|
608 else // transmit fifo.. |
|
609 { |
|
610 if (aFramePhase == I2s::ELeft) |
|
611 { |
|
612 clr = CLEARMASK(KHsI2SFifoCtrl_TFIFOLT, 3); |
|
613 set = (aThreshold << KHsI2SFifoCtrl_TFIFOLT); |
|
614 |
|
615 } |
|
616 else // if (aFramePhase == I2s::ERight) |
|
617 { |
|
618 clr = CLEARMASK(KHsI2SFifoCtrl_TFIFORT, 3); |
|
619 set = (aThreshold << KHsI2SFifoCtrl_TFIFORT); |
|
620 } |
|
621 } |
|
622 // updating register with value will also clear FIFO initialization bits.. |
|
623 AsspRegister::Modify32(KHwI2SFifoControl(iInterfaceId), clr, set); |
|
624 |
|
625 return KErrNone; |
|
626 } |
|
627 |
|
628 TInt D2sChannelNE1_TB::ReadFIFOModeStatus(TInt aFramePhase, TInt& aFlags) |
|
629 { |
|
630 aFlags = 0; |
|
631 |
|
632 TInt irq=__SPIN_LOCK_IRQSAVE(I2sLock); // (read and clear), can be used in ISR |
|
633 TUint32 flags = AsspRegister::Read32(KHwI2SInterruptFlag(iInterfaceId)); |
|
634 AsspRegister::Write32(KHwI2SInterruptFlag(iInterfaceId), flags); // clear the status flags (after reading) |
|
635 __SPIN_UNLOCK_IRQRESTORE(I2sLock,irq); |
|
636 |
|
637 if (aFramePhase == I2s::ELeft) |
|
638 { |
|
639 if(flags & KHtI2SIntFlg_TFLURINT) // L-ch transmit FIFO underrun |
|
640 aFlags |= I2s::ETxUnderrun; |
|
641 |
|
642 if(flags & KHtI2SIntFlg_TFLEINT) // L-ch transmit FIFO reached the empty trigger level |
|
643 aFlags |= I2s::ETxEmpty; |
|
644 |
|
645 if(flags & KHtI2SIntFlg_RFLORINT) // L-ch receive FIFO overrun |
|
646 aFlags |= I2s::ERxOverrun; |
|
647 |
|
648 if(flags & KHtI2SIntFlg_RFLFINT) // L-ch receive FIFO reached the full trigger level |
|
649 aFlags |= I2s::ERxFull; |
|
650 } |
|
651 else |
|
652 { |
|
653 if(flags & KHtI2SIntFlg_TFRURINT) // R-ch transmit FIFO underrun |
|
654 aFlags |= I2s::ETxUnderrun; |
|
655 |
|
656 if(flags & KHtI2SIntFlg_TFREINT) // R-ch transmit FIFO reached the empty trigger level |
|
657 aFlags |= I2s::ETxEmpty; |
|
658 |
|
659 if(flags & KHtI2SIntFlg_RFRORINT) // R-ch receive FIFO overrun |
|
660 aFlags |= I2s::ERxOverrun; |
|
661 |
|
662 if(flags & KHtI2SIntFlg_RFRFINT) // R-ch receive FIFO reached the full trigger level |
|
663 aFlags |= I2s::ERxFull; |
|
664 } |
|
665 |
|
666 return KErrNone; |
|
667 } |
|
668 |
|
669 TInt D2sChannelNE1_TB::EnableFIFOInterrupts(TInt aFramePhase, TInt aInterrupt) |
|
670 { |
|
671 TUint32 val=0; |
|
672 |
|
673 if(aInterrupt & I2s::ERxFull) |
|
674 { |
|
675 if (aFramePhase == I2s::ELeft) |
|
676 val |= KHtI2SIntMask_RFLFINT; |
|
677 |
|
678 if (aFramePhase == I2s::ERight) |
|
679 val |= KHtI2SIntMask_RFRFINT; |
|
680 } |
|
681 |
|
682 if(aInterrupt & I2s::ETxEmpty) |
|
683 { |
|
684 if (aFramePhase == I2s::ELeft) |
|
685 val |= KHtI2SIntMask_TFLEINT; |
|
686 |
|
687 if (aFramePhase == I2s::ERight) |
|
688 val |= KHtI2SIntMask_TFREINT; |
|
689 } |
|
690 |
|
691 if(aInterrupt & I2s::ERxOverrun) |
|
692 { |
|
693 if (aFramePhase == I2s::ELeft) |
|
694 val |= KHtI2SIntMask_RFLORINT; |
|
695 |
|
696 if (aFramePhase == I2s::ERight) |
|
697 val |= KHtI2SIntMask_RFRORINT; |
|
698 } |
|
699 |
|
700 if(aInterrupt & I2s::ETxUnderrun) |
|
701 { |
|
702 if (aFramePhase == I2s::ELeft) |
|
703 val |= KHtI2SIntMask_TFLURINT; |
|
704 |
|
705 if (aFramePhase == I2s::ERight) |
|
706 val |= KHtI2SIntMask_TFRURINT; |
|
707 } |
|
708 |
|
709 if(aInterrupt & I2s::EFramingError) |
|
710 { |
|
711 // not supported, do nothing |
|
712 } |
|
713 |
|
714 if (val) |
|
715 { |
|
716 // update the register |
|
717 AsspRegister::Write32(KHwI2SInterruptMask(iInterfaceId), val); |
|
718 } |
|
719 |
|
720 return KErrNone; |
|
721 } |
|
722 |
|
723 TInt D2sChannelNE1_TB::DisableFIFOInterrupts(TInt aFramePhase, TInt aInterrupt) |
|
724 { |
|
725 TUint32 val = KHmI2SIntMask_ALL; |
|
726 |
|
727 if(aInterrupt & I2s::ERxFull) |
|
728 { |
|
729 if (aFramePhase == I2s::ELeft) |
|
730 val &= ~KHtI2SIntMask_RFLFINT; |
|
731 |
|
732 if (aFramePhase == I2s::ERight) |
|
733 val &= ~KHtI2SIntMask_RFRFINT; |
|
734 } |
|
735 |
|
736 if(aInterrupt & I2s::ETxEmpty) |
|
737 { |
|
738 if (aFramePhase == I2s::ELeft) |
|
739 val &= ~KHtI2SIntMask_TFLEINT; |
|
740 |
|
741 if (aFramePhase == I2s::ERight) |
|
742 val &= ~KHtI2SIntMask_TFREINT; |
|
743 } |
|
744 |
|
745 if(aInterrupt & I2s::ERxOverrun) |
|
746 { |
|
747 if (aFramePhase == I2s::ELeft) |
|
748 val &= ~KHtI2SIntMask_RFLORINT; |
|
749 |
|
750 if (aFramePhase == I2s::ERight) |
|
751 val &= ~KHtI2SIntMask_RFRORINT; |
|
752 } |
|
753 |
|
754 if(aInterrupt & I2s::ETxUnderrun) |
|
755 { |
|
756 if (aFramePhase == I2s::ELeft) |
|
757 val &= ~KHtI2SIntMask_TFLURINT; |
|
758 |
|
759 if (aFramePhase == I2s::ERight) |
|
760 val &= ~KHtI2SIntMask_TFRURINT; |
|
761 } |
|
762 |
|
763 if(aInterrupt & I2s::EFramingError) |
|
764 { |
|
765 // not supported, do nothing |
|
766 } |
|
767 |
|
768 TInt irq=__SPIN_LOCK_IRQSAVE(I2sLock); // (read and clear), not used from ISR but made safe nevertheless... |
|
769 TUint32 oldVal = AsspRegister::Read32(KHwI2SInterruptMask(iInterfaceId)); |
|
770 if (val!=oldVal) |
|
771 { |
|
772 // update the register |
|
773 AsspRegister::Write32(KHwI2SInterruptMask(iInterfaceId), val); |
|
774 } |
|
775 __SPIN_UNLOCK_IRQRESTORE(I2sLock,irq); |
|
776 |
|
777 return KErrNone; |
|
778 } |
|
779 |
|
780 TInt D2sChannelNE1_TB::IsFIFOInterruptEnabled(TInt aFramePhase, TInt& aEnabled) |
|
781 { |
|
782 // check, if any interrupt is enabled.. |
|
783 TUint32 val = AsspRegister::Read32(KHwI2SInterruptMask(iInterfaceId)); |
|
784 |
|
785 aEnabled=0; |
|
786 if(aFramePhase== I2s::ELeft) |
|
787 { |
|
788 if(val & KHtI2SIntMask_TFLURINT)// L-ch transmit FIFO underrun int enable |
|
789 aEnabled |= I2s::ETxUnderrun; |
|
790 if(val & KHtI2SIntMask_TFLEINT)// L-ch transmit FIFO reached the empty trigger level int enable |
|
791 aEnabled |= I2s::ETxEmpty; |
|
792 if(val & KHtI2SIntMask_RFLORINT)// L-ch receive FIFO overrun int enable |
|
793 aEnabled |= I2s::ERxOverrun; |
|
794 if(val & KHtI2SIntMask_RFLFINT)// L-ch receive FIFO reached the full trigger level int enable |
|
795 aEnabled |= I2s::ERxFull; |
|
796 } |
|
797 else |
|
798 { |
|
799 if(val & KHtI2SIntMask_TFRURINT)// R-ch transmit FIFO underrun int enable |
|
800 aEnabled |= I2s::ETxUnderrun; |
|
801 if(val & KHtI2SIntMask_TFREINT)// R-ch transmit FIFO reached the empty trigger level int enable |
|
802 aEnabled |= I2s::ETxEmpty; |
|
803 if(val & KHtI2SIntMask_RFRORINT)// R-ch receive FIFO overrun int enable |
|
804 aEnabled |= I2s::ERxOverrun; |
|
805 if(val & KHtI2SIntMask_RFRFINT)// R-ch receive FIFO reached the full trigger level int enable |
|
806 aEnabled |= I2s::ERxFull; |
|
807 } |
|
808 |
|
809 return KErrNone; |
|
810 } |
|
811 |
|
812 TInt D2sChannelNE1_TB::ReadFIFOLevel(TInt aFramePhase, TInt aDirection, TInt& aLevel) |
|
813 { |
|
814 // This device only allows us to see, if the receive FIFO or transmit FIFO is either |
|
815 // empty or full, so return: |
|
816 // TX FIFO: 1-FULL, 0-EMPTY, |
|
817 // RX FIFO: 1-EMPTY, 0-FULL |
|
818 |
|
819 TUint32 val = AsspRegister::Read32(KHwI2SFifoStatus(iInterfaceId)); |
|
820 |
|
821 if(aDirection & I2s::ETx) |
|
822 { |
|
823 if (aFramePhase == I2s::ELeft) |
|
824 { |
|
825 aLevel = (val & KHtI2SFifoSts_TFL_FULL) >> 17; // L-ch transmit FIFO full (bit 17) |
|
826 } |
|
827 else // I2s::ERight |
|
828 { |
|
829 aLevel = (val & KHtI2SFifoSts_TFR_FULL) >> 16; // R-ch transmit FIFO full (bit 16) |
|
830 } |
|
831 } |
|
832 else // I2s::ERx |
|
833 { |
|
834 if (aFramePhase == I2s::ELeft) |
|
835 { |
|
836 aLevel = (val & KHtI2SFifoSts_RFL_EMPTY) >> 1; // L-ch receive FIFO empty (bit 1) |
|
837 } |
|
838 else // I2s::ERight |
|
839 { |
|
840 aLevel = val & KHtI2SFifoSts_RFR_EMPTY; // R-ch receive FIFO empty (bit 0) |
|
841 } |
|
842 } |
|
843 |
|
844 return KErrNone; |
|
845 } |
|
846 |
|
847 TInt D2sChannelNE1_TB::EnableDMA(TInt aFifoMask) |
|
848 { |
|
849 TUint32 val=0; |
|
850 |
|
851 if(aFifoMask & I2s::ETx) |
|
852 val |= KHtI2SFifoCtrl_TDMAEN; |
|
853 |
|
854 if(aFifoMask & I2s::ERx) |
|
855 val |= KHtI2SFifoCtrl_RDMAEN; |
|
856 |
|
857 AsspRegister::Modify32(KHwI2SFifoControl(iInterfaceId), 0, val); |
|
858 |
|
859 return KErrNone; |
|
860 } |
|
861 |
|
862 TInt D2sChannelNE1_TB::DisableDMA(TInt aFifoMask) |
|
863 { |
|
864 TUint32 val=0; |
|
865 |
|
866 if(aFifoMask & I2s::ETx) |
|
867 val |= KHtI2SFifoCtrl_TDMAEN; |
|
868 |
|
869 if(aFifoMask & I2s::ERx) |
|
870 val |= KHtI2SFifoCtrl_RDMAEN; |
|
871 |
|
872 AsspRegister::Modify32(KHwI2SFifoControl(iInterfaceId), val, 0); |
|
873 |
|
874 return KErrNone; |
|
875 } |
|
876 |
|
877 TInt D2sChannelNE1_TB::IsDMAEnabled(TInt& aEnabled) |
|
878 { |
|
879 TUint32 val = AsspRegister::Read32(KHwI2SFifoControl(iInterfaceId)); |
|
880 aEnabled = 0; |
|
881 |
|
882 if(val & KHtI2SFifoCtrl_TDMAEN) |
|
883 aEnabled |= I2s::ETx; |
|
884 |
|
885 if(val & KHtI2SFifoCtrl_RDMAEN) |
|
886 aEnabled |= I2s::ERx; |
|
887 |
|
888 return KErrNone; |
|
889 } |
|
890 |
|
891 TInt D2sChannelNE1_TB::Start(TInt aDirection) |
|
892 { |
|
893 TUint32 val=0; |
|
894 |
|
895 if(aDirection & I2s::ERx) |
|
896 { |
|
897 // check, if the interface was configured for reception.. |
|
898 if (iConfig.iType != I2s::EReceiver && iConfig.iType != I2s::EBidirectional) |
|
899 { |
|
900 return KErrNotSupported; |
|
901 } |
|
902 |
|
903 __KTRACE_OPT(KDLL, Kern::Printf("I2S channel %d: Start Rx", iInterfaceId)); |
|
904 val |= KHtI2SCtrl_REN; |
|
905 } |
|
906 else |
|
907 { |
|
908 // check, if the interface was configured for transmission.. |
|
909 if (iConfig.iType != I2s::ETransmitter && iConfig.iType != I2s::EBidirectional) |
|
910 { |
|
911 return KErrNotSupported; |
|
912 } |
|
913 |
|
914 __KTRACE_OPT(KDLL, Kern::Printf("I2S channel %d: Start Tx", iInterfaceId)); |
|
915 val |= KHtI2SCtrl_TEN; |
|
916 } |
|
917 |
|
918 // update the register |
|
919 AsspRegister::Modify32(KHwI2SControl(iInterfaceId), 0, val); |
|
920 |
|
921 return KErrNone; |
|
922 } |
|
923 |
|
924 TInt D2sChannelNE1_TB::Stop(TInt aDirection) |
|
925 { |
|
926 TUint32 val=0; |
|
927 |
|
928 if(aDirection & I2s::ERx) |
|
929 { |
|
930 __KTRACE_OPT(KDLL, Kern::Printf("I2S channel %d: Stop Rx", iInterfaceId)); |
|
931 val = KHtI2SCtrl_REN; |
|
932 } |
|
933 else |
|
934 { |
|
935 __KTRACE_OPT(KDLL, Kern::Printf("I2S channel %d: Stop Rx", iInterfaceId)); |
|
936 val = KHtI2SCtrl_TEN; |
|
937 } |
|
938 |
|
939 // update the register |
|
940 AsspRegister::Modify32(KHwI2SControl(iInterfaceId), val, 0); |
|
941 |
|
942 return KErrNone; |
|
943 } |
|
944 |
|
945 TInt D2sChannelNE1_TB::IsStarted(TInt aDirection, TBool& aStarted) |
|
946 { |
|
947 TUint32 val=AsspRegister::Read32(KHwI2SControl(iInterfaceId)); |
|
948 |
|
949 if(aDirection & I2s::ERx) |
|
950 { |
|
951 aStarted = (val & KHtI2SCtrl_REN) >> 24; // bit 24 |
|
952 } |
|
953 else |
|
954 { |
|
955 aStarted = (val & KHtI2SCtrl_TEN) >> 25; // bit 25 |
|
956 } |
|
957 return KErrNone; |
|
958 } |
|
959 |
|
960 |