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1 /* |
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2 * Copyright (c) 2008-2010 Nokia Corporation and/or its subsidiary(-ies). |
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3 * All rights reserved. |
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4 * This component and the accompanying materials are made available |
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5 * under the terms of "Eclipse Public License v1.0" |
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6 * which accompanies this distribution, and is available |
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7 * at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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8 * |
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9 * Initial Contributors: |
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10 * Nokia Corporation - initial contribution. |
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11 * |
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12 * Contributors: |
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13 * |
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14 * Description: |
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15 * naviengine_assp\interrupts.cpp |
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16 * NE1_TBVariant ASSP interrupt control and dispatch |
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17 * |
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18 */ |
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19 |
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20 |
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21 |
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22 #include <naviengine_priv.h> |
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23 |
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24 const TUint8 IntIsEdge[96] = |
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25 { |
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26 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, |
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27 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
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28 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 1, 1, 1, 1, |
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29 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
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30 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
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31 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 |
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32 }; |
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33 |
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34 #ifdef __SMP__ |
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35 #include <arm_gic.h> |
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36 |
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37 #ifndef __STANDALONE_NANOKERNEL__ |
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38 #undef DEBUGPRINT |
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39 #define DEBUGPRINT Kern::Printf |
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40 #endif |
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41 |
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42 TUint32 NaviEngineInterrupt::IrqDispatch(TUint32 aVector) |
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43 { |
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44 if (aVector<32 || aVector>127) |
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45 { |
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46 GicCpuIfc& g = *(GicCpuIfc*)KHwBaseIntIf; |
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47 g.iEoi = aVector; |
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48 *(TInt*)0xdeaddead = 0; |
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49 return aVector; |
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50 } |
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51 NKern::Interrupt(aVector - 32); |
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52 return aVector; |
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53 } |
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54 |
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55 void NaviEngineInterrupt::DisableAndClearAll() |
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56 { |
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57 // NKern does all the GIC stuff |
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58 } |
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59 |
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60 void NaviEngineInterrupt::Init1() |
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61 { |
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62 __KTRACE_OPT(KBOOT, DEBUGPRINT(">Interrupt_Init1()")); |
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63 DisableAndClearAll(); |
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64 Arm::SetIrqHandler((TLinAddr)&IrqDispatch); |
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65 Arm::SetFiqHandler((TLinAddr)&FiqDispatch); |
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66 TInt i; |
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67 for (i=32; i<128; ++i) |
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68 { |
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69 TBool edge = IntIsEdge[i-32]; |
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70 TUint32 flags = 0; |
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71 if (i>=36 && i<42) |
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72 flags |= NKern::EIrqInit_Count; // timers count all interrupts |
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73 if (edge) |
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74 flags |= NKern::EIrqInit_RisingEdge; |
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75 else |
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76 flags |= NKern::EIrqInit_LevelHigh; |
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77 TInt r = NKern::InterruptInit(i-32, flags, i, i); |
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78 __KTRACE_OPT(KBOOT, DEBUGPRINT("InterruptInit %d(%02x) -> %d", i-32, i, r)); |
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79 __NK_ASSERT_ALWAYS(r==KErrNone); |
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80 } |
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81 |
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82 __KTRACE_OPT(KBOOT, DEBUGPRINT("<Interrupt_Init1()")); |
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83 } |
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84 |
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85 //extern "C" void Interrupt_Init2AP() |
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86 // { |
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87 // } |
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88 |
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89 void NaviEngineInterrupt::Init3() |
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90 { |
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91 // |
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92 // Any further initialisation of the Hardware Interrupt Controller |
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93 // Note This is not called at the moment. Should be deleted. |
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94 } |
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95 |
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96 EXPORT_C TInt Interrupt::Bind(TInt aId, TIsr aIsr, TAny* aPtr) |
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97 { |
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98 __KTRACE_OPT(KEXTENSION,Kern::Printf("Interrupt::Bind id=%d func=%08x ptr=%08x", aId, aIsr, aPtr)); |
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99 TUint id = (TUint)aId; |
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100 if (id<32 || id>=(TUint)KNumNaviEngineInts) |
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101 return KErrArgument; |
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102 TUint32 flags = 0; |
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103 if (id>=36 && id<=41) |
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104 { |
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105 flags |= NKern::EIrqBind_Count; |
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106 } |
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107 return NKern::InterruptBind(id-32, aIsr, aPtr, flags, 0); |
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108 } |
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109 |
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110 EXPORT_C TInt Interrupt::Unbind(TInt aId) |
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111 { |
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112 __KTRACE_OPT(KEXTENSION,Kern::Printf("Interrupt::Unbind id=%08x",aId)); |
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113 if (aId >= 0x10000) |
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114 return NKern::InterruptUnbind(aId); // aId is a handle not a specific ID |
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115 if (TUint(aId) < TUint(KNumNaviEngineMaxInts)) |
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116 return NKern::InterruptUnbind(aId - 32); // Vector number to nanokernel interrupt number |
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117 return KErrArgument; |
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118 } |
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119 |
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120 EXPORT_C TInt Interrupt::Enable(TInt aId) |
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121 { |
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122 __KTRACE_OPT(KEXTENSION,Kern::Printf("Interrupt::Enable id=%08x",aId)); |
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123 if (aId >= 0x10000) |
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124 return NKern::InterruptEnable(aId); // aId is a handle not a specific ID |
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125 if (TUint(aId) < TUint(KNumNaviEngineMaxInts)) |
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126 return NKern::InterruptEnable(aId - 32); // Vector number to nanokernel interrupt number |
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127 return KErrArgument; |
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128 } |
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129 |
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130 EXPORT_C TInt Interrupt::Disable(TInt aId) |
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131 { |
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132 __KTRACE_OPT(KEXTENSION,Kern::Printf("Interrupt::Disable id=%08x",aId)); |
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133 if (aId >= 0x10000) |
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134 return NKern::InterruptDisable(aId); // aId is a handle not a specific ID |
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135 if (TUint(aId) < TUint(KNumNaviEngineMaxInts)) |
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136 return NKern::InterruptDisable(aId - 32); // Vector number to nanokernel interrupt number |
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137 return KErrArgument; |
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138 } |
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139 |
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140 EXPORT_C TInt Interrupt::Clear(TInt aId) |
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141 { |
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142 __KTRACE_OPT(KEXTENSION,Kern::Printf("Interrupt::Clear id=%08x",aId)); |
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143 if (aId >= 0x10000) |
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144 return NKern::InterruptClear(aId); // aId is a handle not a specific ID |
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145 if (TUint(aId) < TUint(KNumNaviEngineMaxInts)) |
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146 return NKern::InterruptClear(aId - 32); // Vector number to nanokernel interrupt number |
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147 return KErrArgument; |
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148 } |
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149 |
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150 EXPORT_C TInt Interrupt::SetPriority(TInt /*anId*/, TInt /*aPriority*/) |
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151 { |
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152 return KErrNotSupported; |
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153 } |
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154 |
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155 #else |
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156 SInterruptHandler NaviEngineInterrupt::Handlers[KNumNaviEngineInts]; |
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157 |
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158 void NaviEngineInterrupt::DisableAndClearAll() |
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159 { |
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160 //Disable all interrupts |
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161 for(TUint i=0; i<=((KNumNaviEngineInts-1)/32); i++) |
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162 AsspRegister::Write32(KHoGidIntDisableBase+i*4, 0xffffffff); |
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163 //Clear all interrupts |
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164 for(TUint i=0; i<=((KNumNaviEngineInts-1)/32); i++) |
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165 AsspRegister::Write32(KHoGidPendClearBase+i*4, 0xffffffff); |
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166 |
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167 } |
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168 |
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169 void NaviEngineInterrupt::Init1() |
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170 { |
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171 // |
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172 // need to hook the ARM IRQ and FIQ handlers as early as possible and disable and clear all interrupt sources |
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173 // |
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174 __KTRACE_OPT(KBOOT,Kern::Printf("NaviEngineInterrupt::Init1()")); |
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175 TInt i; |
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176 for (i=0; i<KNumNaviEngineInts; i++) |
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177 { |
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178 Handlers[i].iPtr=(TAny*)i; |
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179 Handlers[i].iIsr=Spurious; |
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180 } |
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181 DisableAndClearAll(); |
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182 Arm::SetIrqHandler((TLinAddr)NaviEngineInterrupt::IrqDispatch); |
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183 Arm::SetFiqHandler((TLinAddr)NaviEngineInterrupt::FiqDispatch); |
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184 |
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185 // All interrupts are N-N (LSB = 1) |
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186 // Both edge (MSB = 1) and level triggered (MSB = 0) |
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187 // are present |
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188 for (TInt i=0; i<KNumNaviEngineInts; ++i) |
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189 { |
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190 TUint8 isEdge = 0x0; |
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191 if(i>=32 && i<128) |
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192 { |
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193 isEdge = IntIsEdge[i-32]; |
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194 } |
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195 const TUint8 isNN = 0x1; |
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196 const TUint8 irqConfig = (isEdge << 1) | isNN; |
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197 |
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198 const TInt byteOffset = i/4; |
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199 const TInt shiftForIrq = i%4; |
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200 TUint8 setMask = irqConfig << shiftForIrq; |
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201 AsspRegister::Modify8(KHoGidConfigBase + byteOffset, 0, setMask); |
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202 } |
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203 |
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204 // Set interrupts starting from 32 to this CPU only |
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205 for(TUint i=0; i<=((KNumNaviEngineInts-1)/4); i++) |
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206 AsspRegister::Write32(KHoGidTargetBase+i*4, 0x0f0f0f0f); |
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207 |
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208 // Set priority on all interrupts |
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209 for(TUint i=0; i<=((KNumNaviEngineInts-1)/4); i++) |
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210 AsspRegister::Write32(KHoGidPriorityBase+i*4, 0xA0A0A0A0); |
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211 |
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212 // Set binary point. No-preemption, all bits used |
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213 AsspRegister::Write32(KHwCIIBinPoint, 7); |
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214 |
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215 // Set priority mask |
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216 AsspRegister::Write32(KHwCIIPrioMask, 0xF0); |
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217 |
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218 // Enable Distributor and CPU Interface for IRQ |
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219 AsspRegister::Write32(KHoGidControl, 1); |
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220 AsspRegister::Write32(KHwCIIControl, 1); |
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221 } |
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222 |
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223 void NaviEngineInterrupt::Init3() |
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224 { |
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225 // |
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226 // Any further initialisation of the Hardware Interrupt Controller |
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227 // Note This is not called at the moment. Should be deleted. |
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228 } |
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229 |
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230 void NaviEngineInterrupt::Spurious(TAny* anId) |
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231 { |
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232 Kern::Fault("SpuriousInt", (TInt)anId); |
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233 } |
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234 |
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235 // |
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236 // The APIs below assume ther is a second level Interrupt controller located at Variant level which handles |
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237 // interrupts generated by hardware at that level. |
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238 // |
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239 |
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240 EXPORT_C TInt Interrupt::Bind(TInt anId, TIsr anIsr, TAny* aPtr) |
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241 { |
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242 __KTRACE_OPT(KEXTENSION,Kern::Printf("Interrupt::Bind id=%d func=%08x ptr=%08x",anId,anIsr,aPtr)); |
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243 TInt r = anId; |
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244 // if ID indicates a chained interrupt, call variant... |
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245 // if (anId<0 && ((((TUint)anId)>>16)&0x7fff)<(TUint)KNumNaviEngineInts) |
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246 // r=NaviEngineAssp::Variant->InterruptBind(anId,anIsr,aPtr); |
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247 __NK_ASSERT_ALWAYS(anId>=0); |
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248 if ((TUint)anId >= (TUint)KNumNaviEngineInts) |
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249 r=KErrArgument; |
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250 else |
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251 { |
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252 SInterruptHandler& h=NaviEngineInterrupt::Handlers[anId]; |
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253 TInt irq=NKern::DisableAllInterrupts(); |
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254 if (h.iIsr != NaviEngineInterrupt::Spurious) |
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255 r=KErrInUse; |
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256 else |
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257 { |
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258 h.iPtr=aPtr; |
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259 h.iIsr=anIsr; |
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260 } |
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261 NKern::RestoreInterrupts(irq); |
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262 } |
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263 return r; |
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264 } |
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265 |
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266 EXPORT_C TInt Interrupt::Unbind(TInt anId) |
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267 { |
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268 __KTRACE_OPT(KEXTENSION,Kern::Printf("Interrupt::Unbind id=%d",anId)); |
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269 TInt r=KErrNone; |
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270 // if ID indicates a chained interrupt, call variant... |
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271 if (anId<0 && ((((TUint)anId)>>16)&0x7fff)<(TUint)KNumNaviEngineInts) |
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272 r=NaviEngineAssp::Variant->InterruptUnbind(anId); |
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273 else if ((TUint)anId >= (TUint)KNumNaviEngineInts) |
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274 r=KErrArgument; |
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275 else |
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276 { |
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277 SInterruptHandler& h=NaviEngineInterrupt::Handlers[anId]; |
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278 TInt irq=NKern::DisableAllInterrupts(); |
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279 if (h.iIsr == NaviEngineInterrupt::Spurious) |
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280 r=KErrGeneral; |
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281 else |
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282 { |
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283 h.iPtr=(TAny*)anId; |
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284 h.iIsr=NaviEngineInterrupt::Spurious; |
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285 Disable(anId); |
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286 } |
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287 NKern::RestoreInterrupts(irq); |
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288 } |
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289 return r; |
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290 } |
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291 |
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292 EXPORT_C TInt Interrupt::Enable(TInt anId) |
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293 { |
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294 __KTRACE_OPT(KEXTENSION,Kern::Printf("Interrupt::Enable id=%d",anId)); |
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295 TInt r=KErrNone; |
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296 // if ID indicates a chained interrupt, call variant... |
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297 if (anId<0 && ((((TUint)anId)>>16)&0x7fff)<(TUint)KNumNaviEngineInts) |
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298 r=NaviEngineAssp::Variant->InterruptEnable(anId); |
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299 else if ((TUint)anId>=(TUint)KNumNaviEngineInts) |
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300 r=KErrArgument; |
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301 else if (NaviEngineInterrupt::Handlers[anId].iIsr==NaviEngineInterrupt::Spurious) |
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302 r=KErrNotReady; |
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303 else |
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304 { |
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305 TUint reg = anId/32; |
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306 TUint mask = 1 << (anId - 32*reg); |
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307 AsspRegister::Write32(KHoGidIntEnableBase+reg*4, mask); |
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308 } |
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309 return r; |
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310 } |
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311 |
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312 EXPORT_C TInt Interrupt::Disable(TInt anId) |
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313 { |
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314 __KTRACE_OPT(KEXTENSION,Kern::Printf("Interrupt::Disable id=%d",anId)); |
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315 TInt r=KErrNone; |
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316 // if ID indicates a chained interrupt, call variant... |
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317 if (anId<0 && ((((TUint)anId)>>16)&0x7fff)<(TUint)KNumNaviEngineInts) |
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318 r=NaviEngineAssp::Variant->InterruptDisable(anId); |
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319 else if ((TUint)anId>=(TUint)KNumNaviEngineInts) |
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320 r=KErrArgument; |
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321 else |
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322 { |
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323 TUint reg = anId/32; |
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324 TUint mask = 1 << (anId - 32*reg); |
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325 AsspRegister::Write32(KHoGidIntDisableBase+reg*4, mask); |
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326 } |
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327 return r; |
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328 } |
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329 |
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330 EXPORT_C TInt Interrupt::Clear(TInt anId) |
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331 { |
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332 __KTRACE_OPT(KEXTENSION,Kern::Printf("Interrupt::Clear id=%d",anId)); |
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333 TInt r=KErrNone; |
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334 // if ID indicates a chained interrupt, call variant... |
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335 if (anId<0 && ((((TUint)anId)>>16)&0x7fff)<(TUint)KNumNaviEngineInts) |
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336 r=NaviEngineAssp::Variant->InterruptClear(anId); |
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337 else if ((TUint)anId>=(TUint)KNumNaviEngineInts) |
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338 r=KErrArgument; |
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339 else |
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340 { |
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341 TUint reg = anId/32; |
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342 TUint mask = 1 << (anId - 32*reg); |
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343 AsspRegister::Write32(KHoGidPendClearBase+reg*4, mask); |
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344 } |
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345 return r; |
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346 } |
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347 |
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348 EXPORT_C TInt Interrupt::SetPriority(TInt /*anId*/, TInt /*aPriority*/) |
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349 { |
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350 return KErrNotSupported; |
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351 } |
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352 #endif |