1 /*

     2 * Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies).

     3 * All rights reserved.

     4 * This component and the accompanying materials are made available

     5 * under the terms of "Eclipse Public License v1.0"

     6 * which accompanies this distribution, and is available

     7 * at the URL "http://www.eclipse.org/legal/epl-v10.html".

     8 *

     9 * Initial Contributors:

    10 * Nokia Corporation - initial contribution.

    11 *

    12 * Contributors:

    13 *

    14 * Description:  

    15 * naviengine_assp\naviengine_pci.h

    16 *

    17 */

    18 

    19 

    20 

    21 #ifndef __NAVIENGINE_PCI_H__ 

    22 #define __NAVIENGINE_PCI_H__ 

    23 //----------------------------------------------------------------------------

    24 //PCI Definitions

    25 //----------------------------------------------------------------------------

    26 

    27 //Register Offsets

    28 const TUint KHoPciVid				= 0x0;		//Vendor Id

    29 const TUint KHoPciDid				= 0x2;		//Device Id

    30 const TUint KHoPciCmd				= 0x04;		//PCI Command Register

    31 const TUint KHoPciStatus			= 0x06;		//PCI Status

    32 

    33 const TInt KNeBridgeNumberOfBars	=12;

    34 const TUint KHoBar[KNeBridgeNumberOfBars] = //Defines base address of a window to access AHB space from PCI space

    35 	{

    36 	0x10, //0

    37 	0x14, //1

    38    	0x18, //2

    39    	0x40, //3

    40 	0x48, //4

    41    	0x50, //5

    42    	0x58, //6

    43    	0x60, //7

    44 	0x68, //8

    45 	0x80, //9

    46 	0x90, //10

    47 	0x98  //11

    48 	};

    49 //Each ACR controls size and address conversion for its associated BAR

    50 const TUint KHoAcr[KNeBridgeNumberOfBars] =

    51 	{

    52 	0xA0, //0

    53 	0xA4, //1

    54 	0xA8, //2

    55 	0x44, //3

    56 	0x4C, //4

    57 	0x54, //5

    58 	0x5C, //6

    59 	0x64, //7

    60 	0x6C, //8

    61 	0x84, //9

    62 	0x94, //10

    63 	0x9C  //11

    64 	};

    65 

    66 const TUint KHoError1		= 0xC0;		//Error Register 1

    67 const TUint KHoPciCtrlH		= 0xE4;		//PCI Control Register Hi

    68 const TUint KHoBarEnable	= 0xEC;		// PCIBAREn 

    69 const TUint KHoCnfig_addr 	= 0xF8; 	//PCI Config Address

    70 const TUint KHoCnfig_data 	= 0xFC; 	//PCI Config Data

    71 

    72 //Bit masks

    73 

    74 //KPcicmd

    75 const TUint16 KHtPcicmd_Memen		=  KBit1; //Specifies whether the PCI interface is to acknowkedge a memory access as a PCI target.

    76 const TUint16 KHtPcicmd_Bmasen		=  KBit2; //Specifies whether the PCI interface is to operate as the PCI master. 

    77 const TUint16 KHtPcicmd_Peren		=  KBit6; // Controls the operation of the device in case of a parity error. 1:React, 0:Ignore

    78 const TUint16 KHtPcicmd_Seren		=  KBit8; // Controls the operation of the device in case of a system error. 1:React, 0:Ignore

    79 

    80 //KPciStatus

    81 const TUint16 KHtPciStatus_ParityError		=  KBit15;

    82 const TUint16 KHtPciStatus_SystemError		=  KBit14;

    83 const TUint16 KHtPciStatus_MasterAbrtRcvd 	=  KBit13;

    84 const TUint16 KHtPciStatus_TargetAbrtRcvd 	=  KBit12;

    85 const TUint16 KHtPciStatus_STA				=  KBit11;

    86 const TUint16 KHmPciStatus_DevSe			=  KBit10|KBit9;

    87 const TUint16 KHtPciStatus_DPErrorAsserted	=  KBit8;

    88 const TUint16 KHtPciStatus_FBBC				=  KBit7;

    89 const TUint16 KHtPciStatus_UDF 				=  KBit6;

    90 

    91 

    92 //KAcr(N)

    93 const TUint32 KHmAcr_BarMask				=  KBit8|KBit7|KBit6|KBit5|KBit4;

    94 const TUint32 KHtAcr_P2Ace					=  KBit0;	//Decides whether or not PCI address should be translated before AHB access.

    95 

    96 //KError1

    97 const TUint32 KHtError1_PEEn				=  KBit10;	// If system error occurs on PCI bus report on the AHB64PCI_ERR pin

    98 const TUint32 KHtError1_AMEn				=  KBit9;	//Assert AHB64PCI_ERR if AHB master receives error response.

    99 const TUint32 KHtError1_SystemError			=  KBit6;	//System error has occurred

   100 const TUint32 KHtError1_AMEr				=  KBit5;	//AHB Master has recieved error response

   101 

   102 //KPciCtrlH

   103 const TUint32 KHtPciCtrlH_CnfigDone 		=  KBit28;

   104 const TUint32 KHtPciCtrlH_Aper 				=  KBit21; // Asserts if an address parity error is detected.

   105 const TUint32 KHtPciCtrlH_Dtep 				=  KBit20; // Asserts if the time of the discard timer is out

   106 const TUint32 KHtPciCtrlH_Dper 				=  KBit19; // Asserts if a data parity error occurs

   107 const TUint32 KHtPciCtrlH_Rlex 				=  KBit18; // Asserts if the retry limit is exceed

   108 const TUint32 KHtPciCtrlH_Mabo 				=  KBit17; // Asserts if the PCI interface generates a master abort signal as the PCI master

   109 const TUint32 KHtPciCtrlH_Tabo 				=  KBit16; // Asserts if the PCI interface detects a target abort signal as the PCI master

   110 const TUint32 KHtPciCtrlH_Aerse 			=  KBit13;

   111 const TUint32 KHtPciCtrlH_Dtimse 			=  KBit12;

   112 const TUint32 KHtPciCtrlH_Perse 			=  KBit11;

   113 const TUint32 KHtPciCtrlH_Rtyse 			=  KBit10;

   114 const TUint32 KHtPciCtrlH_Mase 				=  KBit9;

   115 const TUint32 KHtPciCtrlH_Tase 				=  KBit8;

   116 

   117 namespace Initiator

   118 	{

   119 	const TUint	KHoReg1	= 0xF0;		// Pci Initiator 1 - configure how to map AHB-->PCI

   120 	const TUint KHoReg2	= 0xF4; 	// Pci Initiator 2 - configure how to map AHB-->PCI

   121 

   122 	//! The upper bits of inbound AHB address are converted to this value

   123 	const TUint32 KHmA2PCA					= 0xFFFFFC00;

   124 	const TUint32 KHmA2PCAMask				= 0x1F0;

   125 	const TUint32 KHmType					= 0xE;

   126 	const TUint32 KHtConvEnable				= KBit0;

   127 

   128 	const TUint32 KHsA2PCA					= 9;

   129 	const TUint32 KHsA2PCAMask				= 4;

   130 	const TUint32 KHsType					= 1;

   131 	const TUint32 KHsConvEnable				= 0;

   132 	}

   133 

   134 namespace ConfigAddress

   135 	{

   136 	const TUint32 KHtCnfigEnable		= KBit31;	// Must be set for bridge to allow access to KHoCnfig_data register.

   137 

   138 	const TUint32 KHmBus				= 0xFF0000;	// Bits 23:16

   139 	const TUint32 KHmDevice				= 0xF800;	// Bits 15:11

   140 	const TUint32 KHmFunction			= 0x700;	// Bits 10:8

   141 	const TUint32 KHmOffset				= 0xFC;		// Bits 7:2

   142 

   143 	const TUint32 KHsBus				= 16; 

   144 	const TUint32 KHsDevice				= 11;

   145 	const TUint32 KHsFunction           = 8;

   146 	const TUint32 KHsOffset				= 2;

   147 	}

   148 

   149 const TUint32 KHwUSBHInternalPciWindowSize = 0x2000;  // Size of the system to PCI window at KHwUSBHPhys

   150 #endif // __NAVIENGINE_PCI_H__