|
1 /* |
|
2 * Copyright (c) 2008-2010 Nokia Corporation and/or its subsidiary(-ies). |
|
3 * All rights reserved. |
|
4 * This component and the accompanying materials are made available |
|
5 * under the terms of "Eclipse Public License v1.0" |
|
6 * which accompanies this distribution, and is available |
|
7 * at the URL "http://www.eclipse.org/legal/epl-v10.html". |
|
8 * |
|
9 * Initial Contributors: |
|
10 * Nokia Corporation - initial contribution. |
|
11 * |
|
12 * Contributors: |
|
13 * |
|
14 * Description: |
|
15 * naviengine_assp\navienginedma.h |
|
16 * Definitions and constants of NE SoC DMA Controller. |
|
17 * See 2.10 DMA Controllers in NaviEngine User Manual |
|
18 * |
|
19 */ |
|
20 |
|
21 |
|
22 #ifndef __NAVIENGINEDMA_H__ |
|
23 #define __NAVIENGINEDMA_H__ |
|
24 |
|
25 #include <drivers/dma.h> |
|
26 #include <assp/naviengine/naviengine.h> |
|
27 |
|
28 #include <platform.h> |
|
29 |
|
30 |
|
31 #define FUNC_LOG __KTRACE_OPT(KDMA, Kern::Printf(__PRETTY_FUNCTION__)) |
|
32 #define PRINT(S) __KTRACE_OPT(KDMA, Kern::Printf("%s = 0x%08x", #S, (S))) |
|
33 |
|
34 /* |
|
35 * The list of DMA logical channels. |
|
36 * Use these values to populate iCookie when openning DMA channel. |
|
37 */ |
|
38 enum ENaviengineDmaChannels |
|
39 { |
|
40 EDMAChannelSD0, ///< Internal, clients get value from HCR |
|
41 EDMAChannelSD1, ///< Internal, clients get value from HCR |
|
42 |
|
43 EDMAChannelI2S0RX, ///< Internal, clients get value from HCR |
|
44 EDMAChannelI2S0TX, ///< Internal, clients get value from HCR |
|
45 EDMAChannelI2S1RX, ///< Internal, clients get value from HCR |
|
46 EDMAChannelI2S1TX, ///< Internal, clients get value from HCR |
|
47 EDMAChannelI2S2RX, ///< Internal, clients get value from HCR |
|
48 EDMAChannelI2S2TX, ///< Internal, clients get value from HCR |
|
49 EDMAChannelI2S3RX, ///< Internal, clients get value from HCR |
|
50 EDMAChannelI2S3TX, ///< Internal, clients get value from HCR |
|
51 |
|
52 EDMAChannelUART0RX, ///< Internal, clients get value from HCR |
|
53 EDMAChannelUART0TX, ///< Internal, clients get value from HCR |
|
54 EDMAChannelUART1RX, ///< Internal, clients get value from HCR |
|
55 EDMAChannelUART1TX, ///< Internal, clients get value from HCR |
|
56 EDMAChannelUART2RX, ///< Internal, clients get value from HCR |
|
57 EDMAChannelUART2TX, ///< Internal, clients get value from HCR |
|
58 |
|
59 EDmaMemToMem0, ///< Internal, clients get value from HCR |
|
60 EDmaMemToMem1, ///< Internal, clients get value from HCR |
|
61 EDmaMemToMem2, ///< Internal, clients get value from HCR |
|
62 EDmaMemToMem3, ///< Internal, clients get value from HCR |
|
63 |
|
64 EDma32ChannelCount, //End of DMA32 channels |
|
65 |
|
66 //Enum indexes into KDMAChannelLocator array - it doesn't have a gap |
|
67 EDma64MemToMem0 = EDma32ChannelCount, |
|
68 EDma64MemToMem1, |
|
69 EDma64MemToMem2, |
|
70 EDma64MemToMem3, |
|
71 |
|
72 EDmaChannelCount, // End of DMA64 channels |
|
73 }; |
|
74 |
|
75 /* |
|
76 * The list of DMA controllers in NE SoC |
|
77 */ |
|
78 enum ENaviEngineDmaController |
|
79 { |
|
80 EDmaCtrlExBus, // not supported - there is no any H/W of interest |
|
81 EDMACtrl32, // DMAC32(8C) |
|
82 EDmaCtrl64 // DMAC64(4C) - DMA controller on 64 Bit AXI bus |
|
83 }; |
|
84 |
|
85 /* |
|
86 * Specifies H/W parameters of logical DMA channels (@see ENaviengineDmaChannels). |
|
87 */ |
|
88 struct TDMAChannelLocator |
|
89 { |
|
90 ENaviEngineDmaController iDMACtrl; |
|
91 TInt iGroup; // 0 for EDmaCtrlExBus & 0-4 EDMACtrl32 |
|
92 TInt iSubChannel; // 0-3 for EDmaCtrlExBus & 0-7 for each group of EDMACtrl32 |
|
93 TInt iDMACHCReg; // The content CHC register (excluding subchannel) |
|
94 TInt iTransferShiftSize;//0-Byte, 1-HalfWord, 2-Word, 4-FourWords, 5-EightWords, 6-SixteenWords |
|
95 }; |
|
96 |
|
97 const TInt KDmaHWCtrl32Count = 5; // The number of DMA32 controllers |
|
98 const TInt KDmaCtrl32HWSubChannelCount = 8; // The number of subchannels per controller. |
|
99 |
|
100 const TUint KDMAGroupOffset = 0x1000; // Regitsers' offset per cotroller |
|
101 const TUint KDMAChannelOffset = 0x20; // Registers' offset per subchannel |
|
102 |
|
103 /****** Offsets and bitmasks of DMA32 registers ************/ |
|
104 const TUint KHoDMASAB = 0x00; // Source Address Base |
|
105 const TUint KHoDMADAB = 0x04; // Destination Address Base |
|
106 const TUint KHoDMATCB = 0x08; // Transfer Count Base |
|
107 const TUint KHoDMASAW = 0x0c; // Source Address Work |
|
108 const TUint KHoDMADAW = 0x10; // Destination Address Work |
|
109 const TUint KHoDMATCW = 0x14; // Transfer Count Work |
|
110 const TUint KHoDMACHC = 0x18; // Channel Control Register |
|
111 const TUint KHmDMACHC_SEL = 7; // Channel selection mask |
|
112 const TUint KHvDMACHC_SW = 0xd1226000; // Settings for SW transfer. Word alignement for both source & dest. |
|
113 const TUint KHvDMACHC_SDR = 0xd0292600; // Settings for SD0 Read channel |
|
114 const TUint KHvDMACHC_SDW = 0xd0922610; // Settings for SD1 Write channel |
|
115 |
|
116 const TUint KHsDMACHC_HP = 28; // Sets the values output to HPROT[3:0] during DMA transfer. 1101 initial value |
|
117 const TUint KHvDMACHC_HP = 0xd; // initial value for KHsDMACHC_HP bits |
|
118 const TUint KHtDMACHC_TM = (1<<24); // transfer mode- 0:single transfer, 1:block transfer (memory-to-memory transfers only!) |
|
119 const TUint KHtDMACHC_DAD = (1<<23); // destination address count direction- 0:increment, 1:fixed |
|
120 const TUint KHtDMACHC_SAD = (1<<19); // source address count direction- 0:increment, 1:fixed |
|
121 const TUint KHsDMACHC_DDS = 20; // transfer data size at the DMA transfer destination. |
|
122 const TUint KHsDMACHC_SDS = 16; // transfer data size at the DMA transfer source. |
|
123 /* 000: Byte (8 bits) (initial value) |
|
124 001: Half-word (16 bits) |
|
125 010: Word (32 bits) |
|
126 100: 4 words (128 bits) |
|
127 101: 8 words (256 bits) |
|
128 110: 16 words (512 bits) |
|
129 Others: Setting prohibited */ |
|
130 const TUint KHtDMACHC_TCM = (1<<14); // Masks output to DMATCO[n]: 0: not mask the output, 1:mast the output |
|
131 |
|
132 const TUint KHsDMACHC_AM = 12; // Sets the DMAACK[n] output timing, 00: Pulse mode (active for one clock), |
|
133 // 01: Level mode (active as long as the selected DMAREQ inputs remain) 1x: Masks DMAACK[n]. |
|
134 const TUint KHtDMACHC_LVL = (1<<10); // DMA request is detected 1: at the level or 0: edge of the signal. |
|
135 const TUint KHtDMACHC_HIEN = (1<<9); // 1: high level or rising edge of signal, 0: does not recognize |
|
136 const TUint KHtDMACHC_LOEN = (1<<8); // 1: low level or falling edge of signal, 0: does not recognize |
|
137 const TUint KHtDMACHC_REQD = (1<<4); // Selects whether DMAREQ SEL bit is on the source or destination side. |
|
138 /* Also selects the timing at which DMAACK becomes active. |
|
139 0: Source side. DMAACK becomes active upon read (initial value). |
|
140 1: Destination side. DMAACK becomes active upon write.*/ |
|
141 const TUint KHsDMACHC_SEL = 0; // Selects one of eight DMAREQ/DMAACK/DMATCO signals. |
|
142 |
|
143 // Settings for I2S TX channels |
|
144 const TUint KHvDMACHC_I2SW = |
|
145 KHvDMACHC_HP << KHsDMACHC_HP | // use initial value for KHsDMACHC_HP bits |
|
146 KHtDMACHC_DAD | // destination address fixed, increment source only |
|
147 1 << KHsDMACHC_DDS | // transfer data size at the DMA transfer destination. |
|
148 1 << KHsDMACHC_SDS | // transfer data size at the DMA transfer source. |
|
149 0 << KHsDMACHC_AM | // 00: Pulse mode (active for one clock),01: Level mode (active as long as the selected DMAREQ inputs remain) 1x: Masks DMAACK[n]. |
|
150 KHtDMACHC_LVL | // DMA request is detected 1: at the level or 0: edge of the signal. |
|
151 KHtDMACHC_HIEN| // 1: high level or rising edge of signal, 0: does not recognize |
|
152 0 << KHsDMACHC_SEL; |
|
153 |
|
154 |
|
155 // Settings for I2S RX channels |
|
156 const TUint KHvDMACHC_I2SR = |
|
157 KHvDMACHC_HP << KHsDMACHC_HP | // use initial value for KHsDMACHC_HP bits |
|
158 KHtDMACHC_SAD | // source address fixed, increment destination only |
|
159 1 << KHsDMACHC_DDS | // transfer data size at the DMA transfer destination. |
|
160 1 << KHsDMACHC_SDS | // transfer data size at the DMA transfer source. |
|
161 0 << KHsDMACHC_AM | // 00: Pulse mode (active for one clock),01: Level mode (active as long as the selected DMAREQ inputs remain) 1x: Masks DMAACK[n]. |
|
162 KHtDMACHC_LVL | // DMA request is detected 1: at the level or 0: edge of the signal. |
|
163 KHtDMACHC_HIEN| // 1: high level or rising edge of signal, 0: does not recognize |
|
164 0 << KHsDMACHC_SEL; |
|
165 |
|
166 |
|
167 const TUint KHoDMACHS = 0x1c; // Channel Status Register |
|
168 const TUint KHtDMACHS_EN = 0x001;// Enables/disables DMA transfer. |
|
169 const TUint KHtDMACHS_EN_EN = 0x002;// Enables writing to EN bit. |
|
170 const TUint KHtDMACHS_STG = 0x004;// SW activation of DMA transfer. |
|
171 const TUint KHtDMACHS_FCLR = 0x008;// Clears TC, END, ERR & RQST bits. |
|
172 const TUint KHtDMACHS_RQST = 0x010;// Indicates that transfer request has been received - RO. |
|
173 const TUint KHtDMACHS_ACT = 0x020;// Indicates that DMAC is performing transfer - RO. |
|
174 const TUint KHtDMACHS_ERR = 0x040;// Error in transfer - RO. |
|
175 const TUint KHtDMACHS_END = 0x080;// DMA transfer from working set is completed. |
|
176 const TUint KHtDMACHS_TC = 0x100;// DMA transfer from working set is completed while BVALID is 0. |
|
177 const TUint KHtDMACHS_BVALID = 0x200;// Indicates valid values in base set. |
|
178 const TUint KHoDMACONT = 0x300; // Control Register |
|
179 const TUint KHvDMACONT_INIT_VALUE = 0; |
|
180 const TUint KHoDMASTAT = 0x304; // Status Register |
|
181 const TUint KHmDSTAT_TC_DMA32 = 0xff000000; |
|
182 const TUint KHsDSTAT_TC = 24; |
|
183 const TUint KHsDSTAT_END = 20; |
|
184 const TUint KHsDSTAT_ER = 16; |
|
185 const TUint KHmDSTAT_DMA32 = 0x01000001; |
|
186 |
|
187 |
|
188 static const TUint KMaxDMAUnitTransferLen = 0x10000;// max DMA transfer length in units. |
|
189 |
|
190 /** |
|
191 Constants for the 64 bit AXI DMA controller |
|
192 */ |
|
193 namespace Dma64 |
|
194 { |
|
195 const TInt KChannelCount = 4; // The number of channels on the controller. |
|
196 |
|
197 /** |
|
198 Hardware definitions used for DMA channels |
|
199 */ |
|
200 namespace Channel |
|
201 { |
|
202 /** |
|
203 Register set offsets |
|
204 */ |
|
205 namespace RegSet |
|
206 { |
|
207 enum TRegSets {ENext0, ENext1, ECurrent, ERegSetCount}; |
|
208 const TUint32 KHoBases[ERegSetCount] = {0x0, 0xc, 0x18}; |
|
209 const TUint32 KHoSrcAddr = 0x0; |
|
210 const TUint32 KHoDstAddr = 0x4; |
|
211 const TUint32 KHoTranByte = 0x8; // Transaction byte register |
|
212 }; |
|
213 |
|
214 /** |
|
215 Base offsets for each channel |
|
216 */ |
|
217 const TUint32 KHoBases[KChannelCount] = { 0x0, 0x40, 0x80, 0xC0 }; |
|
218 |
|
219 /** |
|
220 Offset and bit definitions for channel status register |
|
221 */ |
|
222 namespace Status |
|
223 { |
|
224 const TUint32 KHoBase = 0x24; |
|
225 |
|
226 const TUint32 KHtDescErr = KBit10; |
|
227 const TUint32 KHtDescWb = KBit9; |
|
228 const TUint32 KHtDescLoad = KBit8; |
|
229 const TUint32 KHtTc = KBit6; |
|
230 const TUint32 KHtEnd = KBit5; |
|
231 const TUint32 KHtSuspended = KBit3; |
|
232 const TUint32 KHtAct = KBit2; |
|
233 const TUint32 KHtRqst = KBit1; |
|
234 const TUint32 KHtEnabled = KBit0; |
|
235 } |
|
236 |
|
237 /** |
|
238 Offset and bit definitions for channel control register |
|
239 */ |
|
240 namespace Ctrl |
|
241 { |
|
242 const TUint32 KHoBase = 0x28; |
|
243 |
|
244 const TUint32 KHtSetEnable = KBit0; |
|
245 const TUint32 KHtSwTrigger = KBit2; |
|
246 const TUint32 KHtSwReset = KBit3; |
|
247 const TUint32 KHtClrEnd = KBit5; |
|
248 const TUint32 KHtClrTc = KBit6; //Clear the transfer complete status |
|
249 const TUint32 KHtSetSuspend = KBit8; |
|
250 const TUint32 KHtClrSuspend = KBit9; |
|
251 }; |
|
252 |
|
253 /** |
|
254 Offset and bit definitions for channel configuration register |
|
255 */ |
|
256 namespace Cfg |
|
257 { |
|
258 const TUint32 KHoBase = 0x2c; |
|
259 |
|
260 const TUint32 KHtLinkMode = KBit31; |
|
261 const TUint32 KHtCompMask = KBit25; |
|
262 const TUint32 KHtEndMask = KBit24; |
|
263 const TUint32 KHtTransMode = KBit22; |
|
264 |
|
265 const TUint32 KHsDestDataSize = 16; |
|
266 const TUint32 KHsSrcDataSize = 12; |
|
267 |
|
268 const TUint32 KHmDestDataSize = (0xF << KHsDestDataSize); |
|
269 const TUint32 KHmSrcDataSize = (0xF << KHsSrcDataSize); |
|
270 }; |
|
271 |
|
272 /** |
|
273 Offset and bit definitions for channel interval register |
|
274 */ |
|
275 namespace Interval |
|
276 { |
|
277 const TUint32 KHo = 0x30; |
|
278 |
|
279 const TUint32 KHm = 0x0000FFFF; |
|
280 }; |
|
281 |
|
282 const TUint32 KHoExt = 0x34; |
|
283 |
|
284 const TUint32 KHoNxtLnkAddr = 0x38; |
|
285 const TUint32 KHoCurrtLnkAddr = 0x3c; |
|
286 }; |
|
287 |
|
288 /** |
|
289 Registers common to all channels |
|
290 */ |
|
291 namespace Cmn |
|
292 { |
|
293 const TUint32 KHoCtrl = 0x300; |
|
294 const TUint32 KHoEn = 0x310; |
|
295 const TUint32 KHoErr = 0x314; |
|
296 const TUint32 KHoEnd = 0x318; |
|
297 const TUint32 KHoTc = 0x31C; |
|
298 const TUint32 KHoSus = 0x320; |
|
299 }; |
|
300 |
|
301 const TUint KDma64MaxTransferBytes = KMaxTUint32; |
|
302 |
|
303 /** |
|
304 Layout of the 64 bit DMAC's transfer descriptor |
|
305 */ |
|
306 struct TDma64Desc |
|
307 { |
|
308 TDma64Desc() {Clear();} |
|
309 void Clear() {memclr(this, sizeof(*this));} |
|
310 |
|
311 enum TTransferSize |
|
312 { |
|
313 E512Bit = 0x6, |
|
314 }; |
|
315 |
|
316 void SetSourceDataSize(TTransferSize aTransferSize) |
|
317 { |
|
318 iConfig &= ~Channel::Cfg::KHmSrcDataSize; |
|
319 iConfig |= (aTransferSize << Channel::Cfg::KHsSrcDataSize); |
|
320 } |
|
321 |
|
322 void SetDestDataSize(TTransferSize aTransferSize) |
|
323 { |
|
324 iConfig &= ~Channel::Cfg::KHmDestDataSize; |
|
325 iConfig |= (aTransferSize << Channel::Cfg::KHsDestDataSize); |
|
326 } |
|
327 |
|
328 #ifdef _DEBUG |
|
329 void Print() |
|
330 { |
|
331 FUNC_LOG; |
|
332 PRINT(iHeader); |
|
333 PRINT(iSrcAddr); |
|
334 PRINT(iDestAddr); |
|
335 PRINT(iTransactionByte); |
|
336 PRINT(iConfig); |
|
337 PRINT(iInterval); |
|
338 PRINT(iExtension); |
|
339 PRINT(iNextLink); |
|
340 |
|
341 PRINT(Epoc::LinearToPhysical((TUint32)this)); |
|
342 } |
|
343 #endif |
|
344 |
|
345 TUint32 iHeader; |
|
346 TUint32 iSrcAddr; |
|
347 TUint32 iDestAddr; |
|
348 TUint32 iTransactionByte; |
|
349 TUint32 iConfig; |
|
350 TUint32 iInterval; |
|
351 TUint32 iExtension; |
|
352 TUint32 iNextLink; |
|
353 }; |
|
354 |
|
355 /** Bit defs for hardware descriptor header */ |
|
356 namespace HwDesHeader |
|
357 { |
|
358 const TUint32 KHtDim = KBit3; // Descriptor header load interrupt mask: 1: do not issue irq; 0: issue irq. |
|
359 const TUint32 KHtWbd = KBit2; // Write back disable. Set to 1 to disable writeback |
|
360 const TUint32 KHtLe = KBit1; // 1: This is the final link |
|
361 const TUint32 KHtLv = KBit0; // 1: This link is valid |
|
362 }; |
|
363 |
|
364 }; |
|
365 |
|
366 #endif // #ifndef __NAVIENGINEDMA_H__ |