1 /*

     2 * Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies).

     3 * All rights reserved.

     4 * This component and the accompanying materials are made available

     5 * under the terms of "Eclipse Public License v1.0"

     6 * which accompanies this distribution, and is available

     7 * at the URL "http://www.eclipse.org/legal/epl-v10.html".

     8 *

     9 * Initial Contributors:

    10 * Nokia Corporation - initial contribution.

    11 *

    12 * Contributors:

    13 *

    14 * Description:  

    15 *

    16 */

    17 

    18 

    19 

    20 #ifndef _PCI_NE_H

    21 #define _PCI_NE_H

    22 

    23 #include "allocator.h"

    24 #include "mapman.h"

    25 #include "chunkman.h"

    26 #include <pci.h>

    27 #include "pci_priv.h"

    28 

    29 typedef TUint32 TCnfgAddr;

    30 

    31 const TUint32 KPciAddressSpaceSize = 0x80000000; //2GB

    32 

    33 const TInt32 KMinOutboundWindow = 0x400;

    34 

    35 const TUint16 KNecVendorId=0x1033;

    36 const TUint16 KInternalPciBridgeId=0x0175;

    37 const TUint16 KExternalPciBridgeId=0x0174;

    38 

    39 class TNaviEngineChunkCleanup : public TChunkCleanup

    40 	{

    41 public:

    42 	TNaviEngineChunkCleanup(TChunkManager& aChunkMan, TUint32 aPhysicalAddress);

    43 	~TNaviEngineChunkCleanup();

    44 	void Destroy();

    45 	

    46 private:

    47 	TChunkManager& iChunkMan; //< The chunk manager used by the NaviEngine host bridge

    48 	TUint32 iPhysicalAddress; //< Required to free physical memory and unmap memory from Pci

    49 	};

    50 

    51 

    52 

    53 /**

    54 This represents a PCI host bridge controller on the NaviEngine, there are

    55 two identical ones, one for external peripherals and one dedicated

    56 to the OHCI and EHCI usb host controllers.

    57 

    58 The main job of the class is to manage the address mappings which control

    59 access across the bridge. For access to a PCI address from the AHB bus, there

    60 is a window region in AHB space for which accesses will be forwarded to the bridge.

    61 The bridge can then convert that AHB address before accessing the PCI bus.

    62 

    63 It is also possible for devices on the PCI side to access addresses on the AHB side (DMA).

    64 This is done by configuring the BARs on the bridge device to respond to selected PCI

    65 addresses and forward these accesses on to the AHB bus. This is functionallity

    66 is accessed with the CreateChunk method.

    67 */

    68 class DNaviEnginePciBridge : public DPciBridge

    69 	{

    70 public:

    71 	DNaviEnginePciBridge(TUint aBaseAddress, TUint32 aVirtualWindow);

    72 	TInt Initialise();

    73 	~DNaviEnginePciBridge();

    74 

    75 	TPciFunction* Function(TInt aBus, TInt aDevice, TInt aFunction);

    76 	void ConfigurationComplete();

    77 	TInt CreateChunk(DPlatChunkHw*& aChunk, TInt aSize, TUint aAttributes, TUint32& aPciAddress);

    78 	TInt CreateChunk(DChunk*& aChunk, TChunkCreateInfo &aAttributes, TUint aOffset, TUint aSize, TUint32& aPciAddress);

    79 	TInt RemoveChunk(DPlatChunkHw* aChunk);

    80 

    81 	TInt CreateMapping(TUint32 aPhysicalAddress, TInt aSize, TUint32& aPciAddress);

    82 	TInt RemoveMapping(TUint32 aPhysicalAddress);

    83 	TInt GetPciAddress(TUint32 aPhysicalAddress, TUint32& aPciAddress);

    84 	TInt GetPhysicalAddress(TUint32 aPciAddress, TUint32& aPhysicalAddress);

    85 

    86 	void ErrorPrint();

    87 

    88 	TUint8 ReadConfig8(TInt aBus, TInt aDevice, TInt aFunction, TUint aOffset) const;

    89 	TUint16 ReadConfig16(TInt aBus, TInt aDevice, TInt aFunction, TUint aOffset) const;

    90 	TUint32 ReadConfig32(TInt aBus, TInt aDevice, TInt aFunction, TUint aOffset) const;

    91 

    92 	void WriteConfig8(TInt aBus, TInt aDevice, TInt aFunction, TUint aOffset, TUint8 aValue);

    93 	void WriteConfig16(TInt aBus, TInt aDevice, TInt aFunction, TUint aOffset, TUint16 aValue);

    94 	void WriteConfig32(TInt aBus, TInt aDevice, TInt aFunction, TUint aOffset, TUint32 aValue);

    95 

    96 	void ModifyConfig8(TInt aBus, TInt aDevice, TInt aFunction, TUint aOffset, TUint8 aClearMask, TUint8 aSetMask);

    97 	void ModifyConfig16(TInt aBus, TInt aDevice, TInt aFunction, TUint aOffset, TUint16 aClearMask, TUint16 aSetMask);

    98 	void ModifyConfig32(TInt aBus, TInt aDevice, TInt aFunction, TUint aOffset, TUint32 aClearMask, TUint32 aSetMask);

    99 

   100 private:

   101 	void InitialiseRegisters();

   102 	void ClearRegisters();

   103 	void ClearErrors();

   104 

   105 	TInt SetupInterrupts();

   106 	static TCnfgAddr MakeConfigAddress(TInt aBus, TInt aDevice, TInt aFunction, TUint aDwordOffset);

   107 	inline void Wait() const

   108 		{NKern::FMWait(&iConfigLock);}

   109 	inline void Signal() const

   110 		{NKern::FMSignal(&iConfigLock);}

   111 

   112 	TUint ProbeBar(TAddrSpace& aCs, TUint32 aBarOffset);

   113 

   114 

   115 	// ISRs //

   116 	static void PciISR(void* aP);

   117 	static void ParityErrorISR(void* aP);

   118 	static void SystemErrorISR(void* aP);

   119 

   120 	const TUint32 iBaseAddr;

   121 	const TUint32 iVirtualWindow; //The kernel-side virtual address which is used to access PCI bus

   122 

   123 	mutable NFastMutex iConfigLock; //make access to config addrss and data ports atomic

   124 

   125 	TAddressAllocator iAllocator;

   126 	TMappingManager iMapMan;

   127 	TChunkManager iChunkMan;

   128 	const TUint16 iVid;

   129 	const TUint16 iDid;

   130 	};

   131 #endif //_PCI_NE_H