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1 /* |
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2 * Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies). |
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3 * All rights reserved. |
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4 * This component and the accompanying materials are made available |
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5 * under the terms of "Eclipse Public License v1.0" |
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6 * which accompanies this distribution, and is available |
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7 * at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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8 * |
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9 * Initial Contributors: |
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10 * Nokia Corporation - initial contribution. |
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11 * |
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12 * Contributors: |
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13 * |
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14 * Description: |
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15 * naviengine_assp\assp.cpp |
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16 * |
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17 */ |
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18 |
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19 |
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20 |
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21 #include <naviengine_priv.h> |
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22 |
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23 #ifdef __SMP__ |
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24 TSpinLock AsspLock(TSpinLock::EOrderGenericIrqLow1); |
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25 #endif |
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26 |
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27 // |
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28 // |
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29 // MHA - Modular Hardware Adaption |
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30 // |
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31 // Register Access |
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32 // |
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33 // |
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34 |
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35 |
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36 // |
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37 // We need spin locks around read, modify, write operations because another CPU |
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38 // may access the same memory in between operations and potentially cause |
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39 // memory corruption. |
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40 // |
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41 EXPORT_C void AsspRegister::Modify8(TLinAddr aAddr, TUint8 aClearMask, TUint8 aSetMask) |
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42 { |
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43 TUint irq = __SPIN_LOCK_IRQSAVE(AsspLock); |
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44 TUint8 value = *(volatile TUint8 *)aAddr; |
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45 value &= ~aClearMask; |
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46 value |= aSetMask; |
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47 *(volatile TUint8 *)aAddr = value; |
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48 __SPIN_UNLOCK_IRQRESTORE(AsspLock,irq); |
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49 } |
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50 |
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51 EXPORT_C void AsspRegister::Modify16(TLinAddr aAddr, TUint16 aClearMask, TUint16 aSetMask) |
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52 { |
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53 TUint irq = __SPIN_LOCK_IRQSAVE(AsspLock); |
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54 TUint16 value = *(volatile TUint16 *)aAddr; |
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55 value &= ~aClearMask; |
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56 value |= aSetMask; |
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57 *(volatile TUint16 *)aAddr = value; |
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58 __SPIN_UNLOCK_IRQRESTORE(AsspLock,irq); |
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59 } |
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60 |
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61 EXPORT_C void AsspRegister::Modify32(TLinAddr aAddr, TUint32 aClearMask, TUint32 aSetMask) |
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62 { |
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63 TUint irq = __SPIN_LOCK_IRQSAVE(AsspLock); |
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64 TUint32 value = *(volatile TUint32 *)aAddr; |
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65 value &= ~aClearMask; |
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66 value |= aSetMask; |
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67 *(volatile TUint32 *)aAddr = value; |
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68 __SPIN_UNLOCK_IRQRESTORE(AsspLock,irq); |
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69 } |
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70 |
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71 // |
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72 // 64 bit operations may be more complex than 8/16/32 bit operations, depending |
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73 // upon hardware support for 64 bit accesses. |
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74 // |
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75 // For example, one platform required an assembly language function to prevent |
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76 // the compliler optimising the accesses into 2 x 32 bit accesses and causing a |
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77 // bus error. |
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78 // |
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79 // Spinlocks are required for non-atomic operations and are therefore |
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80 // recommended for 64 bit accesses on current platforms. |
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81 // |
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82 extern TUint64 DoRead64(TLinAddr aAddr); |
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83 |
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84 EXPORT_C TUint64 AsspRegister::Read64(TLinAddr aAddr) |
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85 { |
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86 TUint irq = __SPIN_LOCK_IRQSAVE(AsspLock); |
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87 TUint64 value = DoRead64(aAddr); |
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88 __SPIN_UNLOCK_IRQRESTORE(AsspLock,irq); |
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89 return value; |
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90 } |
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91 |
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92 extern void DoWrite64(TLinAddr aAddr, TUint64 aValue); |
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93 |
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94 EXPORT_C void AsspRegister::Write64(TLinAddr aAddr, TUint64 aValue) |
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95 { |
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96 TUint irq = __SPIN_LOCK_IRQSAVE(AsspLock); |
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97 DoWrite64(aAddr, aValue); |
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98 __SPIN_UNLOCK_IRQRESTORE(AsspLock,irq); |
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99 } |
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100 |
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101 EXPORT_C void AsspRegister::Modify64(TLinAddr aAddr, TUint64 aClearMask, TUint64 aSetMask) |
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102 { |
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103 TUint irq = __SPIN_LOCK_IRQSAVE(AsspLock); |
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104 TUint64 value = DoRead64(aAddr); |
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105 value &= ~aClearMask; |
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106 value |= aSetMask; |
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107 DoWrite64(aAddr, value); |
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108 __SPIN_UNLOCK_IRQRESTORE(AsspLock,irq); |
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109 } |
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110 |