1 /*

     2 * Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies).

     3 * All rights reserved.

     4 * This component and the accompanying materials are made available

     5 * under the terms of "Eclipse Public License v1.0"

     6 * which accompanies this distribution, and is available

     7 * at the URL "http://www.eclipse.org/legal/epl-v10.html".

     8 *

     9 * Initial Contributors:

    10 * Nokia Corporation - initial contribution.

    11 *

    12 * Contributors:

    13 *

    14 * Description:  

    15 * naviengine_assp\uart\uart16550.h

    16 *

    17 */

    18 

    19 

    20 

    21 /**

    22  @file

    23  @internalTechnology

    24 */

    25 

    26 #ifndef __UART16550_H__

    27 #define __UART16550_H__

    28 #include <e32def.h>

    29 

    30 //

    31 // reg_def.h

    32 //

    33 const TUint K16550OffsetShift = 2;

    34 const TUint KNum16550Uarts = 3;

    35 const TInt KUart16550ThreadPriority = 27;

    36 _LIT(KUar16550tDriverThread,"UART16550_Thread");

    37 

    38 

    39 //								 

    40 // Register Definitions for 16550-type UARTs

    41 //

    42 

    43 const TUint8 K16550TXHROffset=0<<K16550OffsetShift;			// Transmit Holding Register

    44 const TUint8 K16550RXHROffset=0<<K16550OffsetShift;			// Receive Holding Register

    45 const TUint8 K16550BDLoOffset=0<<K16550OffsetShift;			// Baud Rate Divisor Low

    46 const TUint8 K16550IEROffset=1<<K16550OffsetShift;			// Interrupt Enable Register

    47 const TUint8 K16550BDHiOffset=1<<K16550OffsetShift;			// Baud Rate Divisor High

    48 const TUint8 K16550ISROffset=2<<K16550OffsetShift;			// Interrupt Status Register

    49 const TUint8 K16550FCROffset=2<<K16550OffsetShift;			// FIFO Control Register

    50 const TUint8 K16550LCROffset=3<<K16550OffsetShift;			// Line Control Register

    51 const TUint8 K16550MCROffset=4<<K16550OffsetShift;			// Modem Control Register

    52 const TUint8 K16550LSROffset=5<<K16550OffsetShift;			// Line Status Register

    53 const TUint8 K16550MSROffset=6<<K16550OffsetShift;			// Modem Status Register

    54 const TUint8 K16550ScratchpadOffset=7<<K16550OffsetShift;	// Scratchpad Register

    55 

    56 // Interrupt Enable Register

    57 

    58 const TUint8 K16550IER_RDAI=1;				// Received Data Available

    59 const TUint8 K16550IER_THREI=2;				// Transmit Holding Register Empty

    60 const TUint8 K16550IER_RLSI=4;				// Receive Line Status (error or break)

    61 const TUint8 K16550IER_MSI=8;				// Modem Status

    62 

    63 // Interrupt Status Register

    64 

    65 const TUint8 K16550ISR_NotPending=1;		// Not Interrupt Pending

    66 const TUint8 K16550ISR_IntIdMask=6;			// Mask for Interrupt Identification

    67 const TUint8 K16550ISR_RDAI=4;				// Received Data Available

    68 const TUint8 K16550ISR_THREI=2;				// Transmit Holding Register Empty

    69 const TUint8 K16550ISR_RLSI=6;				// Receive Line Status

    70 const TUint8 K16550ISR_MSI=0;				// Modem Status

    71 const TUint8 K16550ISR_RxTimeout=8;			// Set if FIFO timeout (in conjunction with RDA)

    72 

    73 // FIFO control Register

    74 

    75 const TUint8 K16550FCR_Enable=1;			// Enable TX and RX FIFOs

    76 const TUint8 K16550FCR_RxReset=2;			// Reset RX FIFO (self-clearing)

    77 const TUint8 K16550FCR_TxReset=4;			// Reset TX FIFO (self-clearing)

    78 const TUint8 K16550FCR_TxRxRdy=8;			//

    79 const TUint8 K16550FCR_RxTrig1=0;			// RX FIFO triggers when >=1 char received

    80 const TUint8 K16550FCR_RxTrig4=64;			// RX FIFO triggers when >=4 chars received

    81 const TUint8 K16550FCR_RxTrig8=128;			// RX FIFO triggers when >=8 chars received

    82 const TUint8 K16550FCR_RxTrig14=192;		// RX FIFO triggers when >=14 chars received

    83 

    84 // Line Control Register

    85 

    86 const TUint8 K16550LCR_Data5=0;				// 5 bit characters

    87 const TUint8 K16550LCR_Data6=1;				// 6 bit characters

    88 const TUint8 K16550LCR_Data7=2;				// 7 bit characters

    89 const TUint8 K16550LCR_Data8=3;				// 8 bit characters

    90 const TUint8 K16550LCR_Stop1=0;				// 1 stop bit

    91 const TUint8 K16550LCR_Stop2=4;				// 2 stop bits

    92 const TUint8 K16550LCR_ParityEnable=8;		// Use parity

    93 const TUint8 K16550LCR_ParityEven=16;		// Use even parity

    94 const TUint8 K16550LCR_ParityMark=40;		// Use mark parity

    95 const TUint8 K16550LCR_ParitySpace=56;		// Use space parity

    96 const TUint8 K16550LCR_TxBreak=64;			// Transmit a break

    97 const TUint8 K16550LCR_DLAB=128;			// Divisor Latch Access

    98 

    99 // Modem Control Register

   100 

   101 const TUint8 K16550MCR_DTR=1;

   102 const TUint8 K16550MCR_RTS=2;

   103 const TUint8 K16550MCR_OUT1=4;

   104 const TUint8 K16550MCR_OUT2=8;

   105 const TUint8 K16550MCR_LocalLoop=16;

   106 

   107 // Line Status Register

   108 

   109 const TUint8 K16550LSR_RxReady=1;			// Received data ready

   110 const TUint8 K16550LSR_RxOverrun=2;			// Receiver overrun

   111 const TUint8 K16550LSR_RxParityErr=4;		// Receiver parity error

   112 const TUint8 K16550LSR_RxFrameErr=8;		// Receiver framing error

   113 const TUint8 K16550LSR_RxBreak=16;			// Receive break detect

   114 const TUint8 K16550LSR_TXHREmpty=32;		// Transmit Holding Register Empty (FIFO empty)

   115 const TUint8 K16550LSR_TxIdle=64;			// Transmitter Idle

   116 const TUint8 K16550LSR_RxErrPending=128;	// FIFO contains an error or break indication

   117 

   118 // Modem Status Register

   119 

   120 const TUint8 K16550MSR_DeltaCTS=1;

   121 const TUint8 K16550MSR_DeltaDSR=2;

   122 const TUint8 K16550MSR_TERI=4;

   123 const TUint8 K16550MSR_DeltaDCD=8;

   124 const TUint8 K16550MSR_CTS=16;

   125 const TUint8 K16550MSR_DSR=32;

   126 const TUint8 K16550MSR_RI=64;

   127 const TUint8 K16550MSR_DCD=128;

   128 

   129 // Wrapper class

   130 

   131 class T16550Uart

   132 	{

   133 public:

   134 	void ModifyFCR(TUint aClearMask, TUint aSetMask);

   135 	void ModifyLCR(TUint aClearMask, TUint aSetMask);

   136 	void ModifyMCR(TUint aClearMask, TUint aSetMask);

   137 	void ModifyIER(TUint aClearMask, TUint aSetMask);

   138 	void SetFCR(TUint aValue);

   139 	void SetLCR(TUint aValue);

   140 	void SetMCR(TUint aValue);

   141 	void SetIER(TUint aValue);

   142 	inline TUint FCR()

   143 		{return iFCR;}

   144 	inline TUint LCR()

   145 		{return iLCR;}

   146 	inline TUint MCR()

   147 		{return iMCR;}

   148 	inline TUint IER()

   149 		{return iIER;}

   150 	inline void SetTxData(TUint aData)

   151 		{iBase[K16550TXHROffset]=(TUint8)aData;}

   152 	inline TUint RxData()

   153 		{return iBase[K16550RXHROffset];}

   154 	inline TUint ISR()

   155 		{return iBase[K16550ISROffset];}

   156 	inline TUint LSR()

   157 		{return iBase[K16550LSROffset];}

   158 	inline TUint MSR()

   159 		{return iBase[K16550MSROffset];}

   160 	inline TUint TestISR(TUint aMask)

   161 		{return iBase[K16550ISROffset]&aMask;}

   162 	inline TUint TestLSR(TUint aMask)

   163 		{return iBase[K16550LSROffset]&aMask;}

   164 	inline TUint TestMSR(TUint aMask)

   165 		{return iBase[K16550MSROffset]&aMask;}

   166 	inline void SetScratch(TUint aValue)

   167 		{iBase[K16550ScratchpadOffset]=(TUint8)aValue;}

   168 	inline TUint Scratch()

   169 		{return iBase[K16550ScratchpadOffset];}

   170 	inline void SetBaudRateDivisor(TUint aValue)

   171 		{iBase[K16550BDHiOffset]=(TUint8)(aValue>>8); iBase[K16550BDLoOffset]=(TUint8)aValue;}

   172 public:

   173 	volatile TUint8* iBase;					// base address

   174 	TUint8 iFCR;							// FCR follower

   175 	TUint8 iLCR;							// LCR follower

   176 	TUint8 iMCR;							// MCR follower

   177 	TUint8 iIER;							// IER follower

   178 	};

   179 

   180 #endif